MOS Sample/Hold Ampliers

Ideal

Sample/hold Amplier Deviations from Ideality MOS Sample/Holds Practical Implementations

PRG, SHAs, 1

Ideal Sample/Hold vi t
T/H in

vi
T H T

S/H

Vout

t T/H in

T/H out

t
S/H out

PRG,SHAs, 2

vi

Important Deviations from Ideality

vi

S/H

vo

T/H in T H H 1. Hold to Track Transition Finite acquisition time 2. Track Mode DC offset Finite Bandwidth 3. Track-Hold Transition S/H Offset Aperture Delay Aperture Jitter 4. Hold Mode Droop T

T/H

PRG,SHAs, 3

Performance Limits in SHAs:

What Ultimately Limits Performance in A/D Interface Systems?
Fundamental Device limitations in SH function Practical Design Issues in SH function

Can We Do this?:

LPF
Antenna

S/H

ADC

All-Digital TV

500Mhz,18bit ADC Key Issue: For a given technology, what limits sampling bandwidth and rate?
PRG, SHAs, 4

A Frequency Domain View

Ideal S/H

Sample

f sig Real S/H

fs

f sig

fs

Sample

f sig

fs

f sig

fs

Beat Freq Test

Distortion Products plus noise Sample

f sig

fs

f sig

fs

Sources of Noise: Jitter, kT/C Sources of Distortion: Nonlinear switch behavior Signal-dependent charge Injection Cap nonidealities

PRG,SHAs, 5

The Sampling Jitter Problem

dV t dt

2 Vf

Assume Nyquist Sampling at fs = 2 f sig Result: V t V 2 Ts Key Point: For Nyquist sampling, need: RMS Jitter <
1 1 Ts 6 B 2

PRG, SHAs, 6

Jitter Requirements at Various Sampling Rates SR 1 MHz 10MHz 100MHz 1GHz 8 bits 700ps 70ps 7ps 0.7ps 10 bits 175ps 17.5ps 1.75ps 0.175ps 12 bits 44ps 4.4ps 0.44ps 0.044ps

PRG, SHAs, 7

S/(N+D)

90 80 Low frequency signal 70 60 50 40 30 20 10 High Frequency Signal

-70dB

0 dB

Input level o V
dV dV in in + = Vos + Vin ( 1 + ) + 1 2 dt 3 dt

2
+ higherterms

PRG, SHAs, 8

MOS Sample/Hold Circuits

Vg Vo Vin Cs

Fundamental Limits to Performance

kT/C Noise Sampling Jitter Sample-Mode Bandwidth

Practical Limits to Performance

Charge-injection errors

PRG, SHAs, 9

kT/C Noise Limitation

2 o

Vo Vin Cs

2 v n

4kTR f v 2 o

f 2 v o df = kT C

kT C
6.4uV 21uV 64uV 210uV 0.64mV

Probability

100pF 10pF 1pF 100fF 10fF

Variance=kT/C

V
PRG, SHAs, 10

Vsample

Another Interpretation:

Vo Vin Cs

1 CV2 E 2
=

kT

ExpectedNoiseEnergy
=

sig

SignalEnergy

1 CV2 sig 2

SNR

sig kT

PRG, SHAs, 11

Sample/Hold Offset
Vg Vo Vin Cs Vin Vo Vg (vin+VT) vin t v in
+ ( v )

Whats happening in the device? G

G

S
S Substrate D

Sub

Limiting Case1: Slow gate fall time, channel equilibrates Limiting Case 2: Fast gate fall time, 1/2 of qc goes each way
PRG, SHAs, 12

Vg t

Fast Case
G Vg S is Sub Vg t id,is
Vout

D id
Vout

L t=0s
x

L t=0+ s x L t=0++ s x

t
dV

PRG, SHAs, 13

Fast Case, Cont.

V = C
q ol V V 1 channel CL C H L 2 L

V =

ol V V 1 C H L 2 L

L 2L WLC V V V d ox H T i C L

V = V ( 1 + ) + V i os Where: =1 2 W L 2D ) C C C V os
=

ox

C OL ( V V ) 1 ( V V ) 2 H L 2 H L C C L L

ox

L 2L W d

PRG, SHAs, 14

Slow Case
Example: V = Col v + V V i T L C +C s ol V = Col v + V V i T L C s V = Vin 1 + ) + V where:
=

Vg

20/1.5 Vo Cs =1.0pF

os VT = 1V Col = (0.18fF/u)(20u)
=

ol C L

VH= 5V VL = 0V C Vi = 2V Col = 0.18fF/ micron

3.6fF 1pF

0.0036

V = V V ol os T L C L

Vos = (1v)(0.36%) =3.6mV

PRG, SHAs, 15

Fast Case Example

Vg 20/1.5 Vo Vin=1V VT = 1V VH = 5V Refs: Wilson,JSC,12/85 Shieh, JSC, 4/87 Vittoz, JSC, 6/85 Critical params:
(V V ) L UC s

Cs =1.0pF VL = 0V Vi = 2V Col = 0.18fF/micron

Result: 20 ( 1.14 ) 1ff 2 1 1pF 2

=

Cox = 1ff/square micron

0.014 0.014 0.0036

= C fast slow U
=

W ox L

Vos = 6.3mV

dV

6.3mV Vos 3.6mV fast

PRG, SHAs, 16

g dt

slow

Speed-Accuracy Trade-off
Sample-Mode Bandwidth: q
=

1 R C on L

chan ( 2 V ) 2 2 L C L L

( V ) =

2 L 2

12(mV)(ns)

0.5u

1u

1.5u

2u
Ref- Temes, Electronics Letters

Channel Length
PRG, SHAs, 17

Practical Implementations of CMOS SHAs

Key Issue: Control of Charge Injection

1. Dummy Switch

Problem: No way to balance over Clock fall time variations

Cs 2. Dummy Switch w/Charge Balance Cap

Problem: R must be big, limits samplemode bandwidth

Cs
PRG, SHAs, 18

Implementations, Contd 3. Complementary NMOS, PMOS

Vh

Cs

Vl
t

Assume fast case 1 (V V 1q = V )W L C TN i N N oxN 2 CN 2 H 1q 2 CP

=

1 (V V V )W L C TP L P P oxP 2 i , os where: V os
=

Key Point: 1. Offsets Partially Cancel 2. Gain errors ADD!!

V = Vin 1 + ) + V
=

W L C L C +W P P oxP N N oxN C L

OSN

ol OSP C L

PRG, SHAs, 19

Implementations, Contd
4. Get rid of offset- Go Differential

V g

v vi
+

o1 o2

i1 i2

( 1 + ) + V

os1 os2

Cs

Vo

( 1 + ) + V

v ( 1 + ) i

vi-

Cs

Vo

PRG, SHAs, 20

Implementations, Contd
4. Get rid of Signal-Dependent Error- Bottom Plate Sampling 1 1. Turn off 1
+ +

2. Turn off 2 3. Use Active Ckt to sense 2

vi

Cs

Vo

vi-

Cs

Vo

2
PRG, SHAs, 21

Implementations, Contd
6. Add active device for signal sensing vi+ 1C Cs 2 AZ 1B 1 vo1

2 vo+

1A

vi 1B 1C 1A 2

Cs

Example: Ohara JSC 12/87 Vos<100uV S/M BW = 30Mhz

Nulling Switch gives 4x better gure of merit

PRG, SHAs, 22

Stand-Alone Building-Block SHAs

Important Characteristic:
Low-Impedance NRZ Output Usually Bipolar or BICMOS

Common Congurations:

Open Loop:

Closed Loop:

Closed Loop with Summing Node Sampling

refs: Chambers ISSCC91,Real, ISSCC91, Wooley ISSCC90 PRG, SHAs, 23

Stand-Alone SHAs, Contd

Example: Wooley JSC 12-89, Stafford JSC 12/74

S/H

vin + + CL
Bottom-Plate Sampling- Different Implementation Output amp always active and valid Widely used in building blocks Disadvantage- Sample Mode Bandwidth limited by active devices Disadvantage- Offset, Noise limited by Amps

RL

PRG, SHAs, 24

Nonlinear Transient Charge Injection in MOS SHAs

i=C(dV/dT) Two Key Effects: 1. R 1, R 2 = f(v ). Creates on on in Signal-dependent charge-inj. Must match R s on 2. v differences at turnoff gives ds dv/dt dependent charge

vi

Ron1

Cs

+ v -

Vo

= R C(dv/dt) ds on

vi

Ron2 i=C(dV/dT)

Cs

Vo + v

injection mismatch. Must optimize switch sizes

= -R C(dv/dt) ds on -

2
Ref: Lin, JSC, April 91 PRG, SHAs, 25

Summary of S/H Charge-Injection Errors

os

V 1 in

dV dV in in + = 2 dt 3 dt

2
+ etc

Error Term

Ckt Techniques Differential S/H AZ Amplier Bottom-plate sampler Limits S/M Bandwidth Nonlinear Chg Inj.
PRG, SHAs, 26

Vos

1 2 3

Diode Bridge Samplers

Ibias isw
on off t Vout

vin isw isw

on off t

Cs Ibias

Can be very fast if diodes are fast (i.e. Schottky) Hard to control pedestal- currents must match and must clamp to Vout Matches ECL Bipolar well Best suited to High-speed/low accuracy
Refs- Corcoran, ISSC87 PRG, SHAs, 27

Speed-Accuracy Trade-off in Diode Samplers

Ibias isw vin isw
Neglect Parasitics

Ron As

Cs Ibias I

on

1 kT gm qI d
=

3db

1 R C on s

bias C kT sq
)

stored q

bias f I
=

kT f q
( L)

(W =

2
(Bipolar Figure of Merit)

b 2

stored C s

bias f C s

(MOS Figure of Merit)

PRG, SHAs, 28

Performance Examples

Author Ohara JSC 12/87 Wool. JSC 12/89 Real ISSCC 91 Chamb ers ISSCC 91

Techn 3u CMOS

Supply V 10V

Pwr 50mW

S.M. BW 100Mhz

S.M. Vos 0

S/H Vos 100uV

T/H delay 500ns

Sampl e Rate 500khz

Type MOS Passiv Sampl

1.2u BiCMOS

10V

1.2W

250Mhz

10mV

500uV

12ns

20Mhz

CL/FB

2u BICMOS 5Ghz/ 2.5Ghz Comp bipolar

10V

100m W

15Mhz

NR

500uV

15ns

4Mhz

OL/FB

+5,-5, +7 -10

1.2W

200Mhz

1mV

5ns

20Mhz

OL

PRG, SHAs, 29

References on SHAs
Stafford, et al JSC 12/74 Vittoz, et al, JSC, 6/85 Wilson, et al, JSC, 12/85 Shieh,et al, JSC, 4/87 Ohara, et al, JSC, 12/87 Wooley, et al, JSC, 12/89 Chambers,et al, ISSCC91 Real, et al, ISSCC91 Corcoran, et al, ISSCC87 Lin JSC 4/91

PRG, SHAs, 30