MN HC

ng dng Vi iu khin
(Microcontroller Applications)

By Trn Vn Hng Mechatronics Dept

http://www.ntu.edu.vn/
Email: tvh42th@gmail.com

Ti liu tham kho

1. Microprofessors and microcpmputers hardware and softwware, Ronaid J.Tocci, Frank J.Ambrosio, Prentice Hall, 2003 2. Interfacing Sensors To The Pc, Willis J.Tompkin, Jonh G.webster, Prentice Hall, 1998 3. Vi x l, V n Th Minh, NXB Gio Dc. 4. H vi iu khin 8051, Tng Vn On. 5. K thut Vi iu khin AVR, Tng Vn On.

Ni dung chng trnh

n n n n n n

Ch01: Cc h m v m ho Ch02: H thng vi x l Ch03: B nh Ch04: H vi iu khin AVR Ch05: Ngn ng lp trnh CodevisionAVR Ch06: Input/Output

Cc bi ton
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

Thit k mch iu khin nh sng theo chng trnh nh trc Thit k mch trang tr bng n LED Thit k mch nhn dng im phc v (thm t nht 2IC) Thit k mch o lng ma Thit k mch iu khin nhit khng kh Thit k mch iu khin nhit dung dch Thit k mch ng h in t Thit k mch tnh thi gian cho cc mn in kinh Thit k bng quang bo Thit k mch kho in t Thit k mch iu khin thit b bng remote Kt ni bn phm my tnh vi VXL, hin th k t ln LCD Thit k mch iu khin Robot chy theo qy o (sd motor bc) Thit k mch iu khin tc ng c DC Thit k mch iu khin gc quay ca mt, n tc cho motor.

Chng 1: Cc h m v m ho

n n n

Cc h m dng trong my tnh Cc php ton s hc i vi h hai M ASCII

1.1 Cc h m dng trong my tnh

1.1.1 H mi v h hai
n

Con ngi th quen dng h c s mi (h mi) 1234,56 = 1.103 + 2.102 + 3.101 + 4.100 + 5.10-1 + 6.10-2 My tnh th ch lm vic vi h c s hai (h hai) 1011,01 = 1.23 + 0.22 + 1.21 + 1.20 + 0.2-1 + 1.2-2 MSB
n

LSB
0

Nibble gm 4 bit
3

Byte gm 8 bit
7 0

Word gm 16 bit
15 0

1.1.1 Chuyn i gia h mi v h hai n i h hai sang h mi

1011,012 = 1.23 + 0.22 + 1.21 + 1.20 + 0.2-1 + 1.2-2 = 11,2510
n

i h mi sang h hai
4610 = 1011102
46 0 2 23 1 2 11 2 5 1 1

2 2 0

2 1 1

2 0

Hnh 1. Mt cch i h mi sang h hai

1.1.1 Chuyn i gia h mi v h hai (tip) n i s thp phn h mi sang h hai

0,12510 = 0,0012
0,125 0,250 0,500
n

x x x

2 2 2

= = =

0 ,250 0 ,500 1 ,000

S BCD (s h mi m ho bng h hai)

S BCD thch hp cho cc thi b o c hin th s u ra. 123410 = 0001 0002 0003 0004BCD

H mi su
123410 = 0100 1101 00102 = 4D216

1.2 Cc php ton s hc i vi h hai

1.2.1 Php cng
ana(n-1) ... a2a1a0 + bmb(m-1) ... b2b1b0 = ckc(k-1) ... c2c1c0 (h c s x) ci
=

(ai + bi + (ai-1 + bi-1)%x )/x

1101 1001 + 0001 1011 1111 0100

V d cng h hai

1.2.2 Php tr v s b hai

a. Php tr
ana(n-1) ... a2a1a0 - bmb(m-1) ... b2b1b0 = ckc(k-1) ... c2c1c0 (h c s x) ci ci
= =

(ai Bi-1) bi (ai Bi-1 + x) bi

1101 1001 0001 1011 1011 1110

(nu (ai Bi-1) >= bi v Bi = 0) (nu (ai Bi-1) < bi v Bi = 1)

V d tr h hai

1.2.2 Php tr v s b hai (tip)

b. S b hai
Ta c th thay php tr bng php cng: cng s b tr vi i s ca s tr. tm s b hai ca mt s A ta lm theo cc bc sau: + Biu din s A s h hai ca n. + Tm s b mt (b logic) ca s (o bt). + Cng mt vo s b mt trn nhn c s b hai ca A.

1.2.3 Php nhn

V d nhn 2 s h hai c di 4 bt a 0 0 1 1 b a.b 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 01 01 01 0

Bng 1. Quy tc php nhn

0 00 1 10 1 11

1 01

1.2.2 Php chia

b. Chia trc tip
V d: 35/5 = 7 1 00 01 1 0 00 1 00 0 10 1 11 1 10 1 1 01 1 01 0 10 1 01 11

b. Chia gin tip Ly s b chia tr i s chia, kt qu s l s b chia ca php ton tip theo, lp li n khi s b chia nh hn s chia hoc bng 0.

Chng 2: H thng vi x l
n n n n

u v nhc im h nhng Vi x l, vi iu khin Cc h vi iu khin Ngt v x l ngt

2.1 Ti sao li s dng h nhng?

2.1.1 u im
n n n n n n

Kh nng thch nghi cao Tnh linh ng Kh nng thay i d dng Kh nng ti s dng ti nguyn (th vin,) Gi thnh r ... Tc phn ng chm n nh thp Khng x l c ga tr lin tc ...

2.1.2 Nhc im
n n n n

2.2 Vi iu khin, vi x l
Data bus

CPU GeneralPurpose Microprocessor

RAM ROM I/O PORT Timer, Wdg, ADC, DAC, USB,
UARST,

I2C,

Address bus

TERMINOLOGY
n n

Microcontroller vs. Microprocessor vs. Microcomputer A microprocessor is a central processing unit on a single chip. A microprocessor combined with support circuitry , peripheral I/O components and memory (RAM & ROM) used to be called a microcomputer. A microprocessor where all the components mentioned above are combined on the same single chip that the microprocessor is on, is called a microcontroller.

2.3 Kin trc vi iu khin

n n n n n

n v s l s hc (ALU) B nh Input Output n v iu khin

2.3.1 n v x l s hc (ALU)
n

Thc hin php ton v php logic trn d liu n D liu c th ly trn b nh hoc I/O n Kt qu c th c a ra ngoi hoc vo b nh (kt qu c lu li) General Purpose Registrers

ALU

2.3.2 B nh
Lu tr lnh hay d liu n C th lu tr d liu tm th i n C th ghi/c c bi b iu khin
n
Program Memory $000 Program Flash (4K x 16) Data Memory 32 Gen. Purpose $0000 Working Resisters $001F $0020 64 I/O Resisters $005F $0060 Internal SRAM (512 x 8) $025F $FFF Data Memory $000 EEPROM (512 x 8) $1FF

2.3.3 Input
n

Thit b cho php thng tin v d liu vo bn trong b vi iu khin V d: ADC, I2C, UART,

2.3.4 Output
n

Thit b chuyn i thng tin v d liu t b nh ra thit b ngoi vi. Thit b ngoi vi: LED, LCD, my in,

2.3.5 n v iu khin
n n n n n n

Cung cp xung nhp v iu khin tn hiu Tm np lnh v d liu Chuyn d liu ti/t I/O Gii m lnh Thc hin php tnh s hc/logic p ng tn hiu ngoi (Reset/Ngt)

2.3.6 Mt s h vi iu khin
n

Vi iu khin 8051
n

8051, 89Cxx, 89Sxx, 89Dxx,

Vi iu khin AVR
n

AVR 8 bt, AVR 16 bt,

Vi iu khin PIC
n

PIC 8 bt, PIC 16 bt,

Vi iu khin MCUs ca Philips

n

P8xCxx,

2.3.6 Cc h vi iu khin (tip so snh)

n n n n n n n n

Tc x l (clock, clock cycle execution) Kh nng tch hp (ADC, DAC, UART, I2C,) Di in p hot ng (Operating Voltages) Cng sut u ra (DC current per I/O pin) Kh nng chng nhiu (Noise Reduction) Tp lnh (Instruction) Cng sut IC (Power consumption) ...

2.4 Ngt v x l ngt (Interrupt)

2.4.1 Khi nim
n

Ngt l s dng thc hin chng trnh chnh (CTC) thc hin chng trnh con ph v ngt(ctc)

Main Prog ISRi n: IRQi n + 1: m: IRQj m + 1: ISRj

iret

iret

2.4.2 Cu trc ngt

n Xut n Phc n Tch n C

hin khng c bo trc v gn ging chng trnh con hp nhiu loi ngt

u tin ngt

2.4.3 X l ngt
n n n n n n n

Xut hin v cho php ngt Hon thnh lnh hin ti Lu tr a ch lnh tip theo vo ngn xp Np a ch ISR vo PC Thc hin ISR Kt thc ISR l lnh RETI Khi phc a ch lnh tip theo trong ngn xp, chng trnh tip tc thc hin

2.4.4 Phn loi ngt

n

Ngt mm (software interrupt)

L vic gi 1 ctc (Subroutine) c xy dng ring m ctc ny cn c th c gi bi thit b ngoi vi

Ngt cng (hardware interrupt)

Do port pht tn hiu n CPU

Ngt trong (internal interrupt)

Trong mt s CPU by/x l cc s kin trong khi thc hin

Ngoi l (exceptions)
L vn hay iu kin CPU dng cng vic ang thc hin, tm a ch v thc hin 1 ctc, c thit k x l s kin ny.

Chng 3: B nh
n n n n

B nh bn dn Gii m a ch cho b nh Phi gh ghp b nh M rng b nh

3.1 B nh bn dn
Cc nh nh m t tn hiu n ROM (read only memory) n RAM (random access memory)
n

Memory
ROM
PROM EPROM EEPROM
Read Only Memory

RAM
SRAM
Static RAM

Radom Access Memory DRAM

Dynamic RAM

Programmable ROM Erasable PROM Electrically EPROM

CACHE
L1, L2, L3

3.1.1 C Cc nh nhm t tn hiu

Address

A0 A1 A2 . . . An

D0 D1 D2 . . . Dm

Data

WR

WE CS OE

Select IC

RD

Hnh 3. S khi ca b nh

a. Nh Nhm t tn hiu a ch
n n

C tc dng chn ra mt nh c th S ng a ch s quyt nh c c ti a bao nhiu nh. V V d c m ng a ch vy th th ti a 2m nh.

b. Nh Nhm t tn hiu d liu

n n n

Th ng l l u ra ca ROM v v l vo/ra i vi RAM Cc mch nh th ng c c u v vo/ra l l 3 trng th thi. S ng dy d liu quyt nh di t nh ca mi nh.

c. Nh Nhm t tn hiu chn vi mch

Chn vi mch s trao i d liu. n Cc t tn hiu n ny th ng c ni vi u ra ca b gii m a ch. n Vi mch khng c chn th th bus d liu ca n n b treo ( trng th thi tr kh khng cao).
n

d. Nh Nhm t tn hiu iu khin

Cho ph php d liu ra bus. n Bus d liu b treo nu khng c c tn hiu iu khin. n Mch th ng ch c mt t tn hiu iu khin c/ghi.
n

3.1.2 ROM
B nh c ni dung ghi sn ch c ra n Ch np v vo mt ln duy nht n Khng b mt thng tin khi mt in
n
A0 A1 A2 . . . An WR WE CS
Select IC

Address

D0 D1 D2 . . . Dm

Data

OE RD

Hnh 3. B nh ROM

3.1.3 ROM c c th lp tr trnh c a. PROM (Programmable ROM)

n n n

Thi gian truy cp nhanh 120120-250ns Ch np mt ln duy nht bng c cc t ch chy c cc cu ch ch in p khi lp tr trnh khong 1010-13V
VCC

A0

Address Bus

Address decoder

A1

A2

D2

D1

D0

b. EPROM (erasable PROM)

Thi gian truy cp khong 120 450 ns n in p lp tr trnh khong 1010-25V n N c th c xo xo to ton b bng tia cc t tm. n Th i gian lp tr trnh cho mt nh lu (khong 50ms)
n

c. EEPROM (electrically EPROM)

n n

Xo Xo tng n v nh bng in, khng cn tia cc t tm. Thi gian lp tr trnh cho mt nh khong 5ms.

d. Flash memory
n n n

Thi gian truy cp nhanh (khong 120ns). Thi gian ghi nhanh 10s Xa tng khi nh

3.1.4 RAM
n n

B mt d liu khi mt in. Thi gian truy cp nhanh (c loi 15ns).

Input buffers R/W

Decoder 6 line to 64 line

Register 0 Register 1 Register 2 . . . Register 62 Register 63

Output buffers

Address input

CS

Hnh 3. Cu to bn trong ca 64 x 4 RAM

3.1.4 RAM (tip)

n

SRAM (static RAM)

n n n

Ch to n gin D dng bo tr Thng c s dng trong h thng c b nh nh

DRAM (dynamic RAM)

n n n n

Gi thnh thp i h i mch ph tr Phi lm ti (refresh) thng xuyn Thng c s dng trong h thng c b nh ln

3.2 Gii m a ch cho b nh

n n n

Phn nh khng gian tng th th thnh c cc v vng nh kh khc nhau m bo t tnh n tr ca xung chn Khi thit k th ng c c d phng (spare) c th m rng m khng phi thit k li mch.

Tn hiu a ch Mch gii m a ch Tn hiu iu khin Hnh 3. Mch gii m a ch Cc tn hiu chon chip

3.2.1 Gii m bng c cc mch NAND

n

Mch gii m a ch n gin vi u ra hn ch

A0 A10 Memory D0 - D7

CE

OE

A11 A19 IO/M

RD

Hnh 3. Mch gii m n gin dng NAND

3.2.2 Gii m bng c cc mch 74138

n

L mch gii m 3 u v vo, 8 u ra

A0 A12 Memory D0 D7

74LS138 15 14 13 12 11 10 9 7

CE
Y0 Y1 Y2 Y3 Y4 Y5

OE

A13 A15 A16 A18 IO/M A19

6 5

A B C G2A

RD

G2B 4 G1

Y6 Y7

Hnh 3. S gii m dng 74LS138

3.2.2 Gii m bng c cc mch 74138 (tip)

Mc t tch cc l l mc 0 n Ch duy nht mt u ra mc t tch cc
n

3.2.3 Gii m d dng ROM

n

Cng mt chc nng nh 74138 n Gim thiu s mch ph tr

A0 A12 Memory D0 D7

CE
A0 A1 A2 A3 A4 A5 A6 A7 G1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7

OE

A13 A19

RD

IO/M Hnh 3. S gii m dng PROM

3.2.3 Gii m d dng ROM (tip)

n

Ch s dng 8 byte u tin, c cc byte kh khc u cha c cng mt gi gi tr FFh

Cc u v vo
G A7 A6 A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 A4 A3 A2 A1 A0 O7 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

Cc u ra
O6 O5 O4 O3 O2 O1 O0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1

1 1 1 1 1 Cc a ch kh khc

3.3 Gh Ghp ni b nh
n n n

nh a ch cc nh. Dung l ng b nh. Tc b nh ko p ng c tc VK th th ta phi c c mch tng thm chu k i

B to xung tr

A0 A11 Memory

D0 D7

Ready

CS
74LS138 15 14 13 12 11 10 9 7 A Y0 Y1 Y2 Y3 Y4 Y5 G2B Y6 Y7 G1

CE
F8000-F8FFF

OE

A15 A19

A12 A14
6

B C G2A

RD
FF000-FFFFF

IO/M +Vcc

5 4

Hnh 3. Phi ghp b nh

3.3 Gh Ghp ni b nh (tip)

n

S dng b dn knh gim s chn, chn, tng dung l ng b nh ln

A0/A7
-------

A6/A13
CAS

7 bit Column address register

A7 A8 A9 A10 A11 A12 A13

RAS

Column address decoder

-----------

A0 A1 R/W A2 A3 A4 A5 A6

A0/ A7 A6/A13

7 bit Row address register

Row address decoder

| | | | | | | |

128 x 128 Cell array

Data in Data out

Hnh 3. Kin trc ca b nh 4116

10

3.4 M rng b nh
3.4.1 M rng k kch th c nh
Address bus (AB0 AB3)
R/W CS A3 R/W CS I/03 A2 A1 A0 R/W CS I/00 I/03 A3 A2 A1 A0

RAM-0 16 x 4
I/02 I/01

RAM-1 16 x 4
I/02 I/01 I/00

Data bus (DB0 DB7) Hnh 3. Kt hp hai b nh 16 x 4 thnh 16 x 8

3.4.1 M rng k kch th c nh (tip)

Address bus (AB0 AB10)

R/W

R/W

R/W

R/W

RAM-0 2K x 8
CS I/00 - I/07 CS

RAM-1

RAM-2

RAM-3

2K x 8
CS I/08 - I/015

2K x 8
CS I/016 - I/023

2K x 8
I/024 - I/031

Data bus (DB0 DB31)

Hnh 3. Kt hp bn b nh 2K x 8 thnh 2K x 32

11

3.4.2 M rng dung l ng nh

Address bus (AB0 AB3)
R/W AB4 A3 R/W CS I/03 A2 A1 A0 R/W CS I/00 I/03 A3 A2 A1 A0

RAM-0 16 x 4
I/02 I/01

RAM-1 16 x 4
I/02 I/01 I/00

Data bus (DB0 DB3) Hnh 3. Kt hp hai b nh 16 x 4 thnh 32 x 4

12

Chng 4: H vi iu khin AVR

n n n

Gii thiu chung Cc chc nng iu khin Tp lnh v ngn ng lp trnh

4.1 Gii thiu chung

n

AVR - Kin trc RISC

Khong hn 100 lnh, hu ht thc hin mt chu k my n 32 thanh ghi a nng 8 bit n C th ln t i 16 MIPS t i t n s 16MHz
n

B nh :
n

8..256K Flash Mem cho chng trnh, ghi/xo c 10.000 ln n 512..4K Byte EEPROM, ghi/xo 100.000 n 5128K Byte SRAM

4.1 Gii thiu chung (tip)

n

Cc modul vo ra (I/O moduls)

n n n n n n n

ADC 10bit v t 8..16 knh Analog 1 n 2 Programmable UART Master/Slave ISP Serial Interface 3..4 Timer/Counter: 1 x 16 bit, 2 x 8 bit WatchDog Timer Analog Comparator PWM

Cng sut (Power Management): - 3 ch ngh (Sleep Mode):

n n n n

Idle : 1.9 mA Power-Down: <1A PowerSave (ch chy bnh thng: 6mA)

4.1 Gii thiu chung (tip)

in p lm vic :
n

Vcc 4.0-6.0V vi AT90S8535 n Vcc 2.7-6.0V vi AT90LS8535 0-8MHz vi AT90S8535 n 0-4MHz vi AT90LS8535 n 0-16MHz vi Atmegaxx
n

Tn s CLOCK

4.1 Gii thiu chung (tip)

4.1.1 Cc b nh
Program Memory $000 Program Flash (4K x 16) Data Memory $0000 32 Gen. Purpose Working Resisters $001F $0020 64 I/O Resisters $005F $0060 $1FF Internal SRAM (512 x 8) Data Memory $000

EEPROM (512 x 8)

$025F $FFF

4.1.1 Cc b nh (tip)
Register File R1 R2 R30 R31 I/O Register $00 $01 $3E $3F Data Address Space $0000 $0001 $001E $001F $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $085E $085F

ZL ZH

SRAM Organization

4.1.2 Cc thanh ghi a nng

a. Cc thanh ghi a nng
n n n

Bao gm 32 thanh ghi 8 bit c thc hin trc tip t ALU Cc cp thanh ghi R26, 27; R28, 29; R30, 31 to thnh cc thanh ghi 16 bit

b. Cc thanh ghi ngn xp

n

lu tr d liu tam thi, v tr bin v a ch tr v sau khi phc v chng trnh con ngt v chng trnh con n Lun tr vo nh ca ngn xp n Ngn xp lun bt u t v tr cao ca b nh

c. Cc thanh ghi trng thi

n

Cha thng tin hin ti ca CPU n C 8 bit cha thng tin n Thng tin c th b thay i khi c ch ng trnh con phc v ngt

d. Thanh ghi che ngt v c ngt

Cho php hay khng cho php mt ngt bt k n Thng bo khi c ngt, nu ngt c php n Thanh ghi che ngt c thit lp bng phn mm
n

e. Thanh ghi iu khin

Cho php iu khin ton b vi iu khin n Chc nng ny gm:
n
n

Truy cp b nh SRAM n Ch ng n Ch ngt ngoi

f. Mt s thanh ghi khc

Thanh ghi trng thi b x l n Cc thanh ghi iu khin timer/counter0 n Cc thanh ghi iu khin timer/counter1 n Thanh ghi iu khin Watchdog n Cc thanh ghi iu khin vo ra EEPROM n Cc thanh ghi iu khin SPI n Cc thanh ghi iu khin UART n Cc thanh ghi iu khin b ADC
n

4.1.3 Ngt v x l ngt

Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ProgramAddress $000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 $022 $024 $026 $028 Reset INT0 INT1 INT2 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMP TIMER0 OVF SPI, STC USART, RXC USART, UDRE USART, TXC ADC EE_RDY ANA_COMP TWI SPM_RDY Source Interrupt Difinition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset External Interrupt Request 0 External Interrupt Request 1 External Interrupt Request 2 Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Capture Match A Timer/Counter1 Capture Match B Timer/Counter1 Overflow Timer/Counter0 Compare Match Timer/Counter0 Overflow Serial Transfer Complete USART, Rx Complete USART Data Register Empty USART, Tx Complete ADC Conversion Complete EEPROM Ready Analog Comparator Two-wire Serial Interface Store Program Memory Ready

4.1.3 Ngt v x l ngt (tip)

16 vect ngt (2 Byte) n T a ch $000 trong b nh ch ng trnh n Ngt c ch s thp, u tin cng cao n Mi ngt c mt bt cho php ngt ring n s dng mt ngt th bit ny phi thit lp cng vi c I (Global Interrupt Enable) trong thanh ghi SREG c thit lp n Mt 4 chu k ng h vo (hoc ra khi) ch ng trnh con phc v ngt
n

4.1.3 Ngt v x l ngt (tip)

Bit $3F ($5F) Read/Write Initial Value
n n n n n n n n

7 I
R/W

6 T
R/W

5 H
R/W

4 S
R/W

3 V
R/W

2 N
R/W

1 Z
R/W

0 C
R/W

SREG

I Global Interrupt Enable T Bit Copy Storage H Haft Carry Flag S Sign Bit S = N V V Overflow Flag N Negative Flag Z Zero Flag C Carry Flag

4.2 Cc chc nng iu khin

n n n n n n

Timer/Counter WatchDog Timer Cc cng vo ra ADC UART EEPROM

4.2.1 Timer/Counter C 3 b m/nh thi gian

n

T/C0 :
8 bit n Ngun ng h t mch chia thi gian hoc t chn T0 (theo sn ln/xung) n Ngt trn
n

T/C1:
16 bit n Ngun ng h t mch chia thi gian hoc t chn T1 (theo sn ln/xung) n C ngt trn, ngt thch ng so snh v ngt cho php bt tn hiu t chn ICP
n

4.2.1 Timer/Counter (tip)

n

T/C2:
n n

8 bit Ngun ng h t mch chia thi gian hoc t dao ng bn ngoi (chn TOSC1 v TOSC2 n i vi t thch anh 32768Hz) C ngt trn v ngt thch ng so snh Cho php a tn hiu ra chn OC2 khi c tn hiu thch ng so snh

n n

4.2.2 WatchDog Timer

Watchdog Timer Restart

Reset Processor

Clock

10

4.2.2 WatchDog Timer (tip)

n

Hot ng t b dao ng c lp trn chip n Lnh WDR Reset li WatchDog Timer n Sau khong thi gian > time_out ch ng trnh s b Reset li n Thanh ghi iu khin: WDTCR
7
R

Bit $21 ($41) Read/Write Initial Value

6
R

5
R

4 WDTOE
R/W

3 WDE
R/W

0 WDP0
R/W

WDP2 WDP1
R/W R/W

WDTCR

4.2.2 WatchDog Timer (tip)

n

WDP2, WDP1, WDP0 : xc nh thi gian time_out

WDP2 WDP1 WDP0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Number of WDT Oscillator Cycles 16K 32K 64K 128K 256K 512K 1M 2M

Typical Time_out at Vcc = 3.0V 17.1ms 34.3ms 68.5 0.14s 0.27s 0.55s 1.1s 2.2s

Typical Time_out at Vcc = 5.0V 16.3ms 32.5ms 65ms 0.13s 0.26s 0.52s 1.0s 2.1s

11

4.2.2 Cc cng vo ra

4.2.2 Cc cng vo ra (tip)

C 4 cng vo ra 8 bit PA, PB, PC, PD n Mi cng u c 3 thanh ghi (8 bit), v d cng A :
n

Thanh ghi d liu : PORTA n Thanh ghi iu khin hng d liu : DDRA n Thanh ghi a ch cc chn vo : PINA
n

Cho php thao tc vo ra trn tng bt (mt cng c th va c bit vo va c bit ra)
bit DDRAi=1, chn PAi l chn ra ( = PORTAi) n bit DDRAi=0, chn PAi l chn vo (= PINAi)
n

12

4.2.2 Cc cng vo ra (tip)

Phi nh ngha cng trc khi s dng n Kh nng chu ti cao (Isink khong 20mA/Pin) n Vo ra ba trng thi n C kh nng vo tng t n Pull_up, I = 33A160A
n

4.2.3 ADC
n

c im:
phn gii ti a 10 bit, xp x lin tip n chnh xc tuyt i n 2 LSB n Thi gian chuyn i: 65-260 s, 13 chu k cho mt ln chuyn i n 2 ch hot ng: chuyn i n v chuyn i t do
n

Cc thanh ghi
n

Thanh ghi d liu: ADCL, ADCH

13

4.2.3 ADC (tip)

n

Thanh ghi chn knh : ADMUX

Bit $21 ($41) Read/Write Initial Value
7 REFS1
R/W

4 MUX4
R/W

3 MUX3
R/W

2 MUX2
R/W

1 MUX1
R/W

0 MUX0
R/W

REFS0 ADLAR
R/W R/W

ADMUX

Thanh ghi iu khin trng thi: ADCSRA

7 ADEN
R/W

Bit $21 ($41) Read/Write Initial Value

6 ADSC
R/W

5 ADATE
R/W

4 ADIF
R/W

3 ADIE
R/W

0 ADPS0
R/W

ADPS2 ADPS1
R/W R/W

ADCSRA

4.2.4 USART
n

c im:
Truyn song cng n Truyn ng b hoc khng ng b n Master hoc Slave cp xung nhp n Khun dng d liu a dng (5=>9 bit d liu, 1 hoc 2 bt dng) n Kim tra bit chn l bng phn cng n T pht hin l i trn d liu, khung d liu l i n Kh nng lc nhiu n 3 ngt truyn, nhn v truyn ht n Nhiu ch kt ni n Kh nng nhn i tc truyn thng
n

14

4.2.4 USART (tip)

n

Cc thanh ghi
n Thanh

ghi tc Baud : UBRR

BaudRate =
n VD:

Fclk 16 * (UBRR + 1)

fck = 4MHz,cn tc 14400bps n UBRR =16 (16.3), tc thc t l 14705bps, li 2.1% n Khng nn s dng tc c li > 1%

4.2.4 USART (tip)

n n

Thanh ghi d liu: UDR (gm hai thanh ghi c lp c cng a ch vo ra): cha d liu nhn v truyn Thanh ghi iu khin v trng thi: UCSR (Control and Status Register)
7 RXC
R

Bit $0B ($2B) Read/Write Initial Value

6 TXC
R/W

5 UDRE
R

4 FE
R

3 DOR
R

PE
R

U2X
R/W

MPCM UCSRA
R/W

Bit $0A ($2A) Read/Write Initial Value

7 RXCIE
R/W

6 TSCIE
R/W

5 UDRUE
R/W

4 RXEN
R/W

3 TXEN
R/W

0 TXB8
R/W

UCSZ2 RXB8
R/W R

UCSRB

15

4.2.4 USART (tip)

Hot ng:
n

Thit lp tc truyn, 8/9 bit d liu, truyn/nhn hoc c hai, c s dng ngt hay khng? Truyn d liu:
n n

a byte d liu cn truyn vo UDR i n khi UDRE = 1 (hoc s dng ngt) th truyn tp byte tip theo

4.2.4 USART (tip)

n

Nhn d liu:
St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2]
(St/IDLE)

(IDLE)

i n khi c RXC=1 (hoc s dng ngt) bo hiu nhn c byte d liu Kim tra c FE v OR c byte d liu t UDR

n n

16

4.2.5 EEPROM
n n

EERIE (EEPROM Ready Intr En) EEMWE (EEPROM Master Write En) : cho php ghi. Bit ny s t ng b xo sau 4 chu k ng h EEWE (EEPROM Write En) : khi bit ny c thit lp v EEMWE=1 th thao tc ghi mi c thc hin EERE (EEPROM Read En): cho php c EEPROM. Khi c xong, bit ny s t ng b xo v CPU s dng 4 chu k ng h trc khi lnh tip theo c thc hin

n n

4.2.5 EEPROM (tip)

n

Quy trnh ghi:

n n n n

i n khi EEWE=0 Ghi a ch m i vo EEARL v EEARH Ghi d liu mi vo EEDR Ghi mc logic 1 vo bit EEMWE v mc logic 0 vo EEWE ng thi Trong vng 4 chu k ng h sau ghi gi tr logic 1 vo EEWE

17

4.2.6 SPI (Serial Peripheral Interface)

4.2.6 SPI (Serial Peripheral Interface tip)

n Truyn n Chn n Bit

song cng

ch ch hoc t

cao hoc bit thp truyn trc bt thit lp tc truyn ngt truyn ht bo v xung t ghi thc t ch ngh nhn i tc

n By n C n C

n nh n Ch

18

4.2.7 So snh tn hiu tng t (Analog Comparator)

n

Mch so snh tn hiu tng t: so snh tn hiu analog gia hai chn AIN1 v AIN2

4.1 Gii thiu chung (tip)

J5 1 2 3 4 5 6 Program MOSI MISO SCK Reset +5V U1 1 2 3 4 5 6 7 8 14 15 16 17 18 19 20 21 11 CON8 +5V R1 10K S1 Reset + Reset C3 4.7u 9 RESET AGND AREF ATMEGA32 10 PB0/XCK/T0 PB1/T1 PB2/INT2/AIN0 PB3/OC0/AIN1 PB4/SS PB5/MOSI PB6/MISO PB7/SCK PD0/RXD PD1/TXD PD2/INT0 PD3/INT1 PD4/OC1B PD5/OC1A PD6/ICP PD7/OC2 GND VCC XTAL1 AVCC PA0/ADC0 PA1/ADC1 PA2/ADC2 PA3/ADC3 PA4/ADC4 PA5/ADC5 PA6/ADC6 PA7/ADC7 PC0/SCL PC1/SDA PC2/TCK PC3/TMS PC4/TDO PC5/TDI PC6/TOSC1 PC7/TOSC2 XTAL2 40 39 38 37 36 35 34 33 22 23 24 25 26 27 28 29 C4 12 Y1 8MHz 13 +5V 30 31 32 22p

MOSI MISO SCK

C5

22p

+5V

19

4.3 Tp lnh v ngn ng lp trnh

4.3.1 Tp lnh
n

109 lnh
Ton hc v logic (22) n Lnh r nhnh (34) n Lnh chuyn i d liu (31) n Lnh bt v kim tra bt (31)
n

4.3.1 Tp lnh (tip) Cc ch nh a ch

ch trc tip (Direct Addressing) n a ch qua ch s (Indexed Addressing) n a ch tc th i (Immediate Addressing) n a ch tng i (Relative Addressing) n .
n a

20

4.3.2 Mt s ngn ng lp trnh

Assembler n AVR Edit 3.5 (lp trnh C) n CodeVisionAVR (lp trnh C)

n AVR

21

Chng 5: CodevisionAVR
n n n n

IDE (Integrated Development Environment) Tr Trnh dch (Compiler) Hm th vin (Library Functions) T ng sinh m (Automatic Program Generator)

Hnh 5. Giao din chnh ca CodevisionAVR

5.1 IDE 5.1.1 File

n To n M

file file

n Chnh sa n Lu

5.1.2 Project
n n n n n

To mt project M Project Thm ch ch th thch/din gii Cu h hnh cho Project Quan s st chng trr trrnh dch

5.1.3 Cng c
n n n n

G ri (debugger) Lp tr trnh (programmer) Terminal Cu h hnh (Configuring)

5.1.4 Thit lp mi tr ng
n n n n n

Tng quan Son tho Hin li ng dn tr trnh g li Cu h hnh np

5.2 Tr Trnh dch

n n n n n n n n n n n n n

Tin x l Ch thch T kho D liu chun, d liu t nh ngha Hng, bin Chuyn kiu Php ton Hm Con tr Thanh ghi I/O Truy cp EEPROM Ngt Assembly

5.3 H Hm chun
n

Hm IO chun
n

char getchar(void)
Returns a character received by the UART, using polling.

void putchar(char c)
Transmits the character c using the UART, using polling.

Hm to ton hc
n

unsigned char cabs(signed char x)

returns the absolute value of the byte x.

unsigned int abs(int x)

returns the absolute value of the integer x.

LCD
n n n
n

void lcd_write_byte (unsigned char addr, unsigned char data)

write a byte to the LCD character generator or display RAM

unsigned char lcd_read_byte(unsigned char addr);

read a byte from the LCD character generator or display RAM

void lcd_gotoxy(unsigned char x, unsigned char y);

set the LCD display position x=0..39 y=0..3 ...

n I2C
n n

void i2c_init(void)
this function initializes the I2C bus.

unsigned char i2c_start (void)

issues a START condition. Returns 1 if bus is free or 0 if the I2C I2C bus is busy.

n
n

void i2c_stop (void)

issues a STOP condition. ...

5.4 T ng sinh m
n n n n n n n n n n n n n

Ci t c cc thng s Thit lp RAM ngo ngoi Thit lp cng v vo ra Thit lp ngt Thit lp b m/nh thi Thit lp UART/USART Thit lp b so s snh tng t Thit lp ADC Thit lp SPI Thit lp USI Thit lp I2C Thit lp LCD ...

Chng 6: Input/Output
n n n n

Tng quan Mt s v d vo/ra Lp tr trnh iu khin thit b Thit b vo ra chun

Tng quan
n

Vo ra s
Vo ni tip Vo ra song song

Vo ra tng t
ADC DAC

Vo ra ca 8051

Vo ra ca AVR

Bn phm 4x4
S901 K0 K4 S911 K5 S921 K6 S931 K7 S932 S933 S934 S922 S923 S924 S912 S913 S914 S902 K1 S903 K2 S904 K3

Bn phm 4x4
n n

c bn ph phm Chng rung

Key Board

Key Board
n

AT keyboard go gom mo mot ma tra tran l ln ca cac ph phm, ta tat ca ca c gia giam sa sat b bi mo mot bo bo x ly ly onon-board. Bo Bo x ly ly kha khac bie biet nhau t ba ban ph phm na nay en ba ban ph phm kha khac( chip thong du dung ng go gom 8048, 8049, 6868 va va 6805) nh nhng ta tat chu chung ng c ba ban la lam gio giong ng mo mot vie viec : Gia Giam sa sat nh nhng ph phm c nha nhan / tha tha va va g gi d lie lieu tng xng ng t ti ma may chu chu. Bo Bo x ly ly na nay cham so soc ta tat ca ca d lie lieu ra va va em ba bat c d lie lieu na nao va vao bo bo em 1616-byte cu cua no no ne neu ca can. Ta Tat ca ca vie viec giao tie tiep gi gia ma may chu chu va va ba ban ph phm du dung ng PS/2 protocol.