Successive approximation ADC 1.

1
S/H N-bit DAC
Comparator Successive
Approximation RegisterSAR controller N-bit Successive
approximation ADC N

Vin

S/H

CMP
-

N-bit DAC
N-bit

Vref

N-bit

SAR controller

Digital output
1.1

Successive approximation ADC

-bit Successive approximation ADC

VinS/H
Comparator N-bit DAC
SAR controller binary search

 DAC 3-bit controller 100

binary

DAC VDAC

Vref
2

Vref

Vin
VinVDACMSB 1
VDAC VDAC

Vref 2
2

controller 110

0 VDAC VDAC

Vref 2
2

controller

010Vin Vin
VDAC 1 VDAC VDAC
Vref 4
2

controller X11 0

VDAC VDAC

Vref 4
2

controller X01

Vin VinVDAC
LSB 1 controller XX1
0 controller XX0 successive
approximation ADC DAC
N N cycles
1.2 SAR ADC
3-bit 1.3 3-bit SAR ADC
clock1 Vin
1clock2 Vin
Vin

5Vref
8

3Vref
4

Vref
2

MSB

0clock3

LSB1 ADC 101binary

start
Sample/Hold VinVDAC(1) = Vref/2
N-bitn = N-1i = 1

yes

Vin > VDAC(i)

no

Bn = 1

Bn = 0

VDAC(i+1) = VDAC(i) + (Vref/2i+1)

VDAC(i+1) = VDAC(i) - (Vref/2i+1)

n = n-1i = i+1
yes

i>N
no

stop
1.2

VDAC
Vref

3Vref/4

Vin

Vref/2

(MSB)
OUT = 1

Time

(LSB)
0

1.3

3-bit SAR ADC

Jan Craninckx
SAR ADC VinVDAC
controller VDAC
Vin VDAC
Vin VDAC

Vin

Vin

Vdd
V
V
dd2 ddn
2
2
2

Vin

Vdd
V
V
V
V
dd3 dd3 ndd1 ndd1
2
2
2
2
2

Vdd
V
V
V
V
ndd1 dd dd3 ndd1
3
2
2
2
2
2

VQP

VQN

 VQP VQN
controller VQP VQN
N N cycles
.4
1.5 clock1 VQP VQN

start
Sample/Hold VQPVQNVQP(1) = Vin
VQN(1) = Vdd/2N-bitn = N-1i = 1

yes

Vin > VDAC

(VQP(i) > VQN(i))

no

Bn = 1

Bn = 0

VQP(i+1) = VQP(i)(Vdd/2i+2)
VQN(i+1) = VQN(i)(Vdd/2i+2)

VQP(i+1) = VQP(i)(Vdd/2i+2)
VQN(i+1) = VQN(i)(Vdd/2i+2)

n = n-1i = i+1
yes

i>N
no

stop

 1.4 charge-sharing SAR ADC

VDAC
Vdd

3Vdd/4

Vin
Vin Vdd/8 + Vdd/16

9Vdd/16
Vdd/2
Vin Vdd/8
Vdd/4

1
(MSB)
OUT = 1

3
(LSB)

Time

1.5 charge-sharing SAR ADC

Vin

Vdd
MSB1clock2 Vin
2

Vdd
V
V
V
dd dd 0clock3 Vin dd
8
2
8
8

Vdd
V
V
V
dd dd dd LSB1 ADC
16
2
8
16

101binary 3

 1.6 S/H
N-bit DAC
Comparator Successive Approximation RegisterSAR
control blockpassive charge-sharing
active charge redistribution
binary search ADC
reset CSP CSN
ST SS CTP CTN
INP INN ST SS CSP
CSNCTP CTN CTP CTN
CSP CSN CSP CSN

control block
cp[0N-2] cn[0N-2] B[0N-1]CU
capacitor array unit capacitor capacitor array
1.7 SAR ADC DAC
ADC pre-chargeVdd

charge sharing

Vdd
V
V
C dd C dd
2
4
8

ADC
INp

ST

SS
VTP

VQP

Capacitor
array
CTP

CSP

comp

CU

CTN

CSN
cn
cp
VQN

INn

Track

CLK

Sample

Reset

cp[0...N-2]
cn[0...N-2]

Control block

Precharge

Comparison result

B[0...N-1]

1.6 charge-sharing SAR ADC

Share1

Share2

Share3

VDD

16C

8C

4C

2C

Charge

Ground

Charge
Ground
Share1
Share2
Share3

1.7 Capacitor array

control block cp[0N-2] cn[0N-2]
capacitor array VQP
VQN CSVIN/2 CUVDD clock1 VQP
VQN VQPVQN cp[0]0cn[0]1
CU S/H VQP CSVINp/216C
VDDVQN CSVINn/216CVDDADC B[0]
1cp[0]1cn[0]0VQP CSVINp/2
16CVDDVQN CSVINn/216CVDDADC
B[0]0 clock2 VQP VQN
VQP VQN cp[1]0cn[1]1VQP CSVQP
8CVDDVQN CS VQN 8CVDDADC

B[1]1cp[1]1cn[1]0VQP CS VQP
8CVDDVQN CSVQN 8CVDDADC B[1]
0 ADC