Gii thiu v VHDL

Very High Speed Intergrated Circuit Hardware Description Language Tiu chun IEEE-1076-1987 Trc khi VHDL ra i, c kh nhiu ngn ng m t phn cng: Khng thng nht Mang cc c trng gn vi thit b ca nh cung cp Thuc s hu nh cung cp

Cc u im ca VHDL
Tnh cng cng: VHDL l mt tiu chun ca IEEE Khng thuc s hu ca bt k c nhn hay t chc no. c h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng.

Cc u im ca VHDL
Kh nng h tr nhiu cng ngh v phng php thit k: VHDL cho php thit k bng nhiu phng php nh thit k t trn xung, hay t di ln da vo cc thvin c sn. VHDL cng h tr cho nhiu loi cng ngh xy dng mch nh s dng cng nghng b hay khng ng b, s dng ma trn lp trnh c hay s dng mng logic ngu nhin. VHDL c th phc v tt cho nhiu mc ch thit k khc nhau, t vic thit k cc phn t ph bin n vic thit k cc IC ng dng c th (Application Specified IC - ASIC).

Cc u im ca VHDL
c lp vi cng ngh: Hon ton c lp vi cng ngh ch to phn cng. VD: mt m t h thng dng VHDL thit k mc cng c thc chuyn thnh cc bn tng hp mch khc nhau ty thuc vo cng ngh ch to phn cng no c s dng (dng CMOS, nMOS, ). Kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc h thng s (hp en) cho n mc cng. VD: c th m phng mt bn thit k bao gm c cc h con c m t mc cao v cc h con c m tchi tit

Cc u im ca VHDL
Kh nng trao i kt qu: V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL c th chy trn mi b m phng p ng c tiu chun VHDL. Kh nng h tr thit k mc ln v kh nng s dng li cc thit k: L mt ngn ng lp trnh bc cao nn VHDL c th s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi. Bn trong VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia s thit k. VHDL cng cho php dng li cc phn c sn.

CU TRC M LNH
Cc n v c bn ca VHDL Khai bo th vin (Library) Thc th (Entity) Kin trc (Architecture) Cc v d

Cc n v c bn ca VHDL
M lnh VHDL gm 3 phn c bn sau: Khai bo LIBRARY (th vin): gm danh sch cc th vin s dng trong thit k (VD: ieee, std, work, ) ENTITY (thc th): m t cc chn vo-ra ca mch ARCHITECTURE (kin trc): m t hot ng ca mch LIBRARY: Tp hp cc on lnh thng c s dng Cho php s dng li cc on m lnh v chia s vi cc ng dng khc M lnh c vit theo khun dng ca cc FUNCTION, PROCEDURE hay COMPONENT v c t bn trong cc PACKAGE.

Cc n v c bn ca VHDL

Khai bo th vin (Library)

C php: LIBRARY library_name; USE library_name.package_name.package_parts; Thng s dng cc th vin sau: LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY std; USE std.standard.all;

LIBRARY work; USE work.all;

Khai bo th vin (Library)

Cc th vin std v work ngm nh c sn, khng cn khai bo. S dng th vin ieee khi dng cc kiu d liu STD_LOGIC, STD_ULOGIC, Th vin ieee gm cc gi (package): std_logic_1164: cc mc logic STD_LOGIC v STD_ULOGIC std_logic_arith: Cc kiu d liu SIGNED v UNSIGNED Cc thut ton x l d liu v cc php ton so snh Cc hm chuyn i d liu std_logic_signed: cho php x l d liu STD_LOGIC_VECTOR nh l d liu kiu SIGNED std_logic_unsigned: cho php x l d liu STD_LOGIC_VECTOR nh l d liu kiu UNSIGNED

Thc th (Entity)
Mi thc th bao gm hai thnh phn Cc thuc tnh, thng s (parameters) Cc ng kt ni vo, ra vi bn ngoi

Thc th (Entity)
C php: ENTITY entity_name IS GENERIC ( ... ); PORT ( Thc th (Entity)

port_name : signal_mode signal_type; port_name : signal_mode signal_type;

...); END entity_name; Trong : Signal mode: IN, OUT, INOUT, BUFFER Signal type: BIT, STD_LOGIC, INTEGER, Entity name: khng c dng cc tn ring ca VHDL

V d

Kin trc (Architecture)

Mi thc th phi i km vi t nht 1 kin trc C php: ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name; V d: ARCHITECTURE myarch OF nand_gate IS BEGIN x <= a NAND b; END myarch;

Cc kiu m t kin trc

M hnh cu trc (Structural Style): gm cc thnh phn (component) c lin kt vi nhau. M hnh lung d liu (Dataflow Style): gm cc lnh gn c thc hin ng thi. M hnh hot ng (Behavioral Style): gm cc lnh gn c thc hin tun t. Dng kt hp ca 3 kiu m hnh trn.

CC TON T V THUC TNH

Cc ton t Cc thuc tnh Cc thuc tnh do ngi dng nh ngha Chng ton t GENERIC

Ton t
VHDL cung cp mt s loi ton t sau: Ton t gn Ton t logic Ton t s hc Ton t so snh Ton t dch

Cc ton t gn
<= dng gn gi tr cho SIGNAL := dng gn gi tr cho VARIABLE, CONSTANT, GENERIC => dng gn gi tr cho tng phn t ca kiu vector hoc dng vi t kha OTHERS

VD v ton t gn
SIGNAL x : STD_LOGIC; VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL w : STD_LOGIC_VECTOR(0 TO 7); x <= '1'; y := "0000"; w <= "10000000"; w <= (0 =>'1', OTHERS =>'0');

Cc ton t logic
D liu cho cc ton t ny phi l kiu: BIT, STD_LOGIC, STD_ULOGIC, BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR. V d: y <= NOT (a AND b); y <= a NAND b;

Cc ton t s hc
Dng cho cc kiu d liu s nh l:INTEGER, SIGNED, UNSIGNED, REAL. Bao gm: + Ton t cng - Ton t tr * Ton t nhn / Ton t chia ** Ton t ly m MOD Ton chia ly phn nguyn (Y MOD X c du ca X) REM Ton chia ly phn d (Y REM X c du ca Y) ABS Ton ly gi tr tuyt i

 C cc ton t so snh sau: = So snh bng /= So snh khc nhau < So snh nh hn > So snh ln hn <= So snh nh hn hoc bng >= So snh ln hn hoc bng Ch tc ng ln 2 ton hng c cng kiu Kt qu l mt gi tr Boolean Cc ton hng ng vi php so snh bng v khc (= v /=) c th c kiu bt k. Vi cc kiu c cu trc, 2 gi trc coi l bng nhau nu tt c cc thnh phn tng ng ca chng l nh nhau. Cc ton t so snh cn li phi c ton hng l kiu v hng hoc kiu mng 1 chiu ca cc kiu ri rc.

Ton t so snh

Ton t dch
C php s dng ton t dch l: <left operand><shift operation><right operand> Trong : <left operand> : kiu l BIT_VECTOR <right operand> : kiu l INTEGER C hai ton t dch: Sll Ton t dch tri Rll Ton t dch phi

Ton t ghp ni
Ton t ghp ni (&) tc ng ln cc mng 1 chiu cho ra mt mng mi vi ni dung ca ton hng bn phi c ghp ni theo sau ni dung ca ton hng bn tri. N cng c s dng thm 1 phn t vo mng hoc hnh thnh 1 mng t 2 phn t. Ton t ny thng c s dng vi kiu xu k t .

Th tu tin ca cc ton t
Th tu tin gim dn t trn xung: ** abs not * / mod rem + (sign) - (sign) +- & = /= < <= > >= and or nand nor xor

Cc thuc tnh
Thuc tnh d liu: d'LOW Tr v gi tr nh nht ca ch s mng d'HIGH Tr v ch s ln nht ca ch s mng d'LEFT Tr v ch s bn tri nht ca mng d'RIGHT Tr v ch s bn phi nht ca mng d'LENGTH Tr v kch thc ca vector d'RANGE Tr v khong ch s ca vector d'REVERSE_RANGE Tr v khong ch s ca vector theo th to ngc

V d
Gi s d l mt vector c khai bo nh sau: SIGNAL d : S TD_LOGI C_VEC TOR(0 T O 7) Ta s c: d'LOW = 0, d 'HIGH = 7, d 'LEFT = 0, d 'RIGHT = 7, d'LENGT H = 8 , d'RANGE = (0 to 7), d'RE VERSE_R ANGE = (7 do wnto 0) Cc thuc tnh ny c th dng trong cc vng lp: FOR i IN RAN GE (0 T O 7) LOOP .. . FOR i IN d'R ANGE LO OP .. . FOR i IN RAN GE (d'L OW TO d'HIGH ) LOO P ... FOR i IN RAN GE (0 T O d'L ENGTH-1 ) LOO P ... Nu tn hiu c kiu lit k th: d'VAL(p os) Tr v gi t r phn t t i v t r po s d'POS(v al) Tr v v tr phn t c gi tr l val d'LEFTO F(val ue) Tr v gi t r phn t l in bn tri ca va lue d'RIGHT OF(va lue) Tr v gi t r phn t l in bn phi ca va lue d'PRED( value ) Tr v gi t r ca phn t c v tr nh hn v tr ca valu e 1 n v d'SUCC( value ) Tr v gi t r ca phn t c v tr ln h n v tr ca valu e 1 n v d'VAL(r ow,co lum) Tr v gi t r m t v tr rc bit

Cc thuc tnh (tip)

Thuc tnh tn hiu: Gi s s l mt SIGNAL th ta c : s'EVENT : Tr v True khi mt s kin xy ra i vi s s'STABLE: Tr v True nu khng c s kin no xy ra i vi s s'ACTIVE: Tr v True khi s = 1 s'QUIET <time>: Tr v True khi trong khong thi gian time khng c s kin no xy ra s'LAST_EVENT: Tr v thi gian tri qua k t s kin cui cng s'LAST_ACTIVE: Tr v thi gian qua k t ln s = 1 cui cng s'LAST_VALUE: Tr v gi tr ca s s kin trc

Cc thuc tnh do NSD nh ngha

NSD c thnh ngha ra 1 thuc tnh mi theo c php: Khai bo thuc tnh: ATTRIBUTE attribute_name: attribute_type; M t thuc tnh: ATTRIBUTE attribute_name OF target_name: class IS value; Trong : attribute_type: kiu d liu bt k (BIT, INTEGER, STD_LOGIC_VECTOR, ...) class: TYPE, SIGNAL, FUNCTION, ... value: '0', 27, "00 11 10 01", ...

V d
ATT RIB UT E nu mbe r_ o f_i npu ts : IN TEG ER ; ATT RIB UT E nu mbe r_ o f_i npu ts OF nan d3 : SI GNA L I S 3 ; ... inp uts < = na nd3 'n u mbe r_o f_ p ins ; - - k t qu = 3

V d
M ha kiu lit k: TYPE color IS (red, green, blue, white); Ngm nh th red = "00", green = "01", blue = "10", white = "11". thay i li ta c th dng: ATTRIBUTE enum_encoding OF color: TYPE IS "11 00 10 01"; Thuc tnh do ngi dng nh ngha c th khai bo bt c v tr no, ngoi tr trong thn ca PACKAGE.

Chng ton t
NSD c thnh ngha 1 ton t mi c trng tn vi 1 ton t c nh ngha sn. VD: nh ngha php + gia 1 s INTEGER v 1 BIT. FUNCTIO N "+" (a: IN TEGER , b: BI T) RE TURN IN TEGER IS BEGIN IF (b=' 1') T HEN RET URN a +1; ELSE RE TURN a; END IF; END "+" ; S dng: SIGNAL inp1, outp: INTEGER RANGE 0 TO 15; SIGNAL inp2: BIT; (...) outp <= 3 + inp1 + inp2; (...)

GENERIC
GENERIC l cch to ra 1 tham s tnh dng chung cho ton b thit k. => Lm cho chng trnh mm do hn v tng tnh s dng li. GENERIC phi c khai bo trong ENTITY vi c php nh sau: GENERIC (parameter_name : parameter_type := parameter_value);

V d
Tham s n sau y lun c gi tr ngm nh l 8: ENTITY my_entity IS GENERIC (n : INTEGER := 8); PORT (...); END my_entity; ARCHITECTURE my_architecture OF my_entity IS ... END my_architecture; C th khai bo nhiu hn 1 tham s GENERIC trong 1 ENTITY. GENERIC (n: INTEGER := 8; vector: BIT_VECTOR := "00001111");

VHDL Design Styles (Architecture)

VHDL Design Styles
BEHAVIORAL DATAFLOW STRUCTURAL NONSYTHESIZABLE SYNTHESIZABLE

concurrent components and sequential statements statements interconnects State Test

machines Registers Benches Modeling IP

VHDL subset most suitable for synthesis

M hnh Dataflow
M t cch di chuyn d liu thng qua h thng v cc bc x l khc nhau. o Lung d liu s dng hng lot cc cu lnh ng thi cho ra 1 kt qu logic.

o Dataflow l kiu khai bo hu ch nht khi 1 lot cc phng trnh Boolean c th

cho mt kt qu logic -> s dng thc hin logic t hp n gin o Dataflow code cng c gi l concurrent code (Pedroni)

Bo co ng thi c nh gi cng mt lc, do , th t ca cc bo co ny khng

quan trng Dataflow khng dng cho cc mch tun t / hnh vi This order
U1_out <= A XOR B; Result <= U1_out XOR C; Is the same as this order Result <= U1_out XOR C; U1_out <= A XOR B;

M hnh hnh vi v m hnh cu trc

M hnh hnh vi (behavioral model) M t hot ng ca h thng M t s thay i ca tn hiu u ra da trn s thay i ca tn hiu u vo -> Kh khn hn trong qu trnh tng hp (synthesize) M hnh cu trc (structural model) M t cu trc ca h thng -> D dng hn trong qu trnh tng hp (synthesize)

M t theo m hnh cu trc

Thnh phn cn thit: cc component, c th c 2 loi component Component l mt h thng ring l, c nh ngha vi entity v architecture ring Component c nh ngha ngay bn trong architecture ca entity chnh Phi khi to cc Component trc khi s dng

Khi to Component
Instance_name: entity work.entity_name(architecture name) Instance_name: tn i tng work: tn ca th vin cha cc thnh phn do ngi dng nh ngha (entity, cc kiu d liu) Entity_name: tn ca thc th cn khi to Architecture name: tn ca kin trc gn vi thc th cn khi to

Khi to Component

XOR3 Example

Entity xor3 (same for all architectures)

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY xor3 IS PORT( A : IN B : IN C : IN Result ); END xor3;

STD_LOGIC; STD_LOGIC; STD_LOGIC; : OUT STD_LOGIC

Dataflow Architecture
ARCHITECTURE dataflow OF xor3 IS SIGNAL U1_out: STD_LOGIC; BEGIN U1_out <= A XOR B; Result <= U1_out XOR C; END dataflow;

U1_out

Structural Architecture (xor3 gate)

ARCHITECTURE structural OF xor3 IS SIGNAL U1_OUT: STD_LOGIC; COMPONENT xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT;

A B C

XOR3

Result

BEGIN U1: xor2 PORT MAP ( A,

B, U1_OUT); U2: xor2 PORT MAP ( U1_OUT, C, Result); END structural;

I1 I2 XOR2

I1 => I2 => Y =>

U1_OUT

I1 => I2 => Y =>

A B

C XOR3

RESULT

Component and Instantiation

Named association connectivity (recommended)
COMPONENT xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP ( I1 => A, I2 => B, Y => U1_OUT); ...

LOCAL WIRE COMPONENT PORT NAME

Component and Instantiation

Positional association connectivity (not recommended)
COMPONENT xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP (A, B, U1_OUT); ...