B nh thi: MSP 340 c hai b nh thi 16 Bit l Timer_A v Timer_B n cng ng thi ng vai tr l b m.

Timer_A: c tnh ca Timer_A: L mt b Timer/Counter 16 bit. Vi ba thanh ghi lu tr v 3 thanh ghi so snh. L mt Timer a chc nng. m thi gian, so snh, PWM. Timer_A cng c kh nng ngt khi counter m trn hoc mi thanh ghi m trn. Cc c tnh chnh ca Timer_A bao gm: + L mt Timer/counter 16 Bit khng ng b vi 4 ch hot ng + C th la chn v cu hnh ngun xung + Hai ti 3 thanh ghi c th cu hnh capture/compare + Cu hnh u ra vi ch PWM + Cht ng vo v ng ra khng ng b

Hnh 1: S khi ca Timer_A

Timer hot ng ch Counter 16 Bit: ch Counter gi tr thanh ghi TAR tng hoc gim theo cnh ln ca xung clock (ty thuc vo ch hot ng). Gi tr ca thanh ghi TAR c th c ghi hoc c bi phn mm. N c kh nng to ra mt ngt khi m trn. Thanh ghi TAR c th b xa khi set bit TACLR. Vic set bit TACLR ng thi cng xa gi tr la chn cho b chia xung hoc ch m ln hay m xung. La chn ngun xung v b chia xung: Timer c th la chn ngun t xung t ACLK, SMCLK hoc s dng ngun xung ngoi thng qua TACLK hoc INCLK. Ngun xung c la chn nh bt TASSELx. Cc ngun xung c chn c th c chia 2, 4 hoc 8. B chia xung c reset khi set bit TACLR. Kch hot Timer: Timer c th c kch hot hoc kch hot li bng cc cch sau y: + Timer m khi MCx > 0 v ngun xung c kch hot. + Khi timer ang hot ng ch m ln hoc m xung. C th dng timer bng cch ghi TACCR0 = 0. Timer s kch hot tr li khi gi tr ghi vo TACCR0 khc 0. Gi tr m ln s bt u t 0. Cc ch hot ng ca Timer: Timer hot ng 4 ch : Ch dng, ch m ln, ch tip tc, ch m ln/xung. Cc ch ny c la chn bng bit MCx. MCx 00 01 10 11 Mode Stop Up Continuous Up/down Hot ng Timer c tm dng Timer m t 0 ti gi tr nh ca TACCR0 Timer m t 0 ti 0FFFFh Timer m t 0 n gi tr nh ca TACCR0 ri m v 0

Cc ngt ca Timer_A: C hai ngt c to ra do Timer_A: + Vector ngt TACCR0 cho TRCCR0 CCIFG. + Vector ngt TAIV cho tt c cc c ngt CCIFG khc v TAIFG. Trong ch lu tr CCIFG c set khi gi tr ca timer c lu tr do thanh ghi TACCRx. Trong ch so snh bt k c CCIFG c set nu TAR m ti gi tr TACCRx. C th s dng phn mm set hoc xa bt k c ngt CCIFG no. Tt c cc c ngt CCIFG yu cu mt ngt khi bit CCIE v GIE c set. Ngt TACCR0 CCIFG l ngt ca Timer_A c mc u tin cao nht. C ngt TACCR0 CCIFG t ng reset khi ngt TACCR0 c phc v.

Hnh 2: C ngt ch trong ch so snh v lu tr

Thanh g hi iu khin Timer_A :

Bng 1: Bng lit k cc thanh ghi iu khin Timer_A

Thanh ghi iu khin TACTL:

+ Bit 15-10: Khng s dng. + TASSELx Bit 9-8: La chn ngun xung clock: 00 01
10 11

TACLK ACLK SMCLK INCLK

+ Idx Bit 7-6: La chn b chia trc:

00 01 10 11 /1 /2 /4 /8

+ MCx Bit 5-4: La chn ch hot ng: 00 01 10 11 Dng ch Ch ln Tip tc ch Ch ln/xung

+ TACLR Bit 2: Xa Timer_A. Khi bit ny c set, gi tr m, gi tr b chia trc u c reset. + TAIE Bit 1: Cho php ngt. Khi bit =1 cho php ngt, bit = 0 cm ngt. + TAIFG Bit 0: C ngt ca Timer_A: Bit = 0 Khng c ngt no ang ch Bit = 1 C ngt ang ch phc v

Cc thanh ghi cn li cc bn c th tham kho trong datasheet. Timer_B: Timer_B l b nh thi 16 bt c th hot ng 2 ch Timer v counter. Timer_B p ng a chc nng capture/ so snh, PWM. Timer_B cng c kh nng to ra ngt khi n m trn, hoc cc thanh ghi capture/ so snh. Cc c tnh ca Timer_B: + L mt Timer/counter 16 Bit khng ng b vi 4 ch hot ng. + C th la chn v cu hnh ngun xung. + C t 3 ti 7 thanh ghi c th cu hnh capture/compare. + Cu hnh u ra vi ch PWM. + Cht ng vo v ng ra khng ng b.

Hnh 3: S khi ca Timer_B Nhng im ging v khc nhau giu Timer_A v Timer_B: Timer_B mang y c im ca Timer_A ngoi ra Timer_B c cc c tnh c bit sau: + Kch thc ca Timer c th lp trnh c c di 8, 10, 12 hoc 16 Bit. + Thanh ghi TBCCRx l 2 b m c th c nhm li. + Tt c cc u ra ca Timer_B u c th t trng thi tng tr cao. + Chc nng ca bit SCCI khng c thc hin trong Timer_B. Hot ng ca Timer_B: Timer hot ng ch Counter: Khi hot ng ch m gi tr thanh ghi TBR tng hoc gim (ty thuc vo ch hot ng) theo cnh ln ca xung clock. Thanh ghi TBR c th ghi hoc c. Timer_B c th to ra ngt

khi m trn. Thanh ghi TBR cng c th c xa bng cch set bit TBCLR. Khi bt ny c set ng thi cng reset li gi tr ca b chia v gi tr m. Ch : Bn nn dng hot ng ca Timer trc khi mun chnh sa. Nhng thay i ghi vo TRB s c thc thi ngay lp tc v vy nu thay i gi tr khi timer ang hot ng c th hot ng ca n khng cn chnh xc. C th c gi tr ca Timer khi n ang hot ng. di thanh ghi TBR:Xung cp cho Timer c th ly t ngun xung ACLK hoc SMCLK hoc t ngun xung ngoi TBCLK. Ngun xung c la chn nh bit TBSSELx, ngun xung c la chn c th c chi trc 2, 4, hoc 8. Gi tr ca b chia b reset khi set bit TBCLR. Kch hot timer: Timer c th c khi ng hoc khi ng li bng cc cch sau: + Timer m khi MCx >0 v ngun xung clock hot ng. + Khi timer hot ng mt trong hai ch up, up/down. C th dng hot ng ca timer bng cch t TBCL0=0. Timer c kch hot tr li khi gi tr ny khc 0. Khi kch hot tr li gi tr ca timer bt u t 0. Cc ch hot ng ca Timer: Timer_B hot ng 4 ch , cc ch c la chn nh bit MCx.
MCx 00 01 10 11 Mode Stop Up Continuous Up/down Hot ng Tm dng Timer Timer m t 0 ti gi tr nh ca TBCL0 Timer m t 0 ti gi tr c la chn bi bt CNTLx Timer m t 0 n gi tr nh ca TBCL0 ri m xung v 0

Cc ngt ca Timer_B: Timer_B c th to ra 2 ngt: + Vector ngt TBCCR0 cho TBCCR0 CCIFG.

+ Vector ngt TBIV cho cc c ngt CCIFG v TBIFG. Vector ngt TBCCR0: Vector ngt TBCCR0 l ngt c mc u tin cao nht do Timer_B to ra. C ngt TBCCR0 CCIFG t ng reset khi ngt TBCCR0 c phc v.

Hnh 4: C ngt TBCCR0 Cc thanh ghi ca Timer_B:

Bng 2: Thanh ghi ca Timer_B Thanh ghi iu khin TBCTL: + Bit 15: khng s dng + CNTLx Bit 12-11: di ca b m:

00 01
10 11

16-bit,TBR(max) = 0FFFFh 12-bit,TBR(max) = 0FFFh 10-bit,TBR(max) = 03FFh 8-bit,TBR(max) = 0FFh TBCLK ACLK SMCLK o TBCLK

+ TBSSELx bit 9-8: La chn ngun xung clock: 00 01

10 11

+ IDx Bit 7-6: la chn b chia xung:

00 01 10 11 /1 /2 /4 /8

+ MCx Bit 5-4: La chn ch iu khin: 00 01 10 11 Dng ch Ch ln Tip tc ch Ch ln/xung

+ TBCLR : Xa Timer_B Khi bit ny c set, gi tr b m, b chia xung u c xa v 0. + TBIE Bit 1: Cho php ngt Timer_B. Bit =1 cho php ngt, bit = 0 cm ngt. + TBIFG Bit 0: C ngt. Bit = 0 khng c ngt no ch, bit =1 c ngt ang ch phc v. Khi ngt c phc v Bit t ng c xa v 0.