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1

. Normal -

1.
AVR.
2.
.
3.
AVRStudio .
4.
.

1. .
2.
3. ,
.
16- -.
4. AVRStudio.
5. .
6. .

1. /
1.1.
,
.
/
.
, ,
.

.
.

.
Mega (
AVR)
/
//.
( SBI CBI), .
/,
( )
( ).
1.2. /
/.
/ 3 ,

: PORTx,
DDRx PINx.
. ,
PORTA, DDRA, PINA, - PORTB, DDRB, PINB . .
PINx
, ,
, .

. 1.1. /
1.3. /
/ n
/ . 1.1.
/: PORTxn
( PORTx), DDxn ( DDRx) INxn ( PINx).

n.
. ,
, .

0.
DDxn DDx
/ 1, n- ,
0 .

ORTxn PORTx .
(DDxn = 1), .
1, .
0, .
(DDxn = 0), PORTxn
.
ORTxn 1
.
.
( ) PUD
SFIOR.

. 1.2. SFIOR
PUD 0 ( ),
PORTxn .
PUD 1,
.
( DDxn)
PINxn PINx. ,
PINx
. , ,
. 1.1, PINxn -.
-
INxn
. , 0.5 1.5
.

NOP. OUT
SYNC LATCH 1 ,
.

. 1.1.
1.1.
DDxn PORTxn
PUD

0
0
X

0
1
0

0
1
1

1
0
1

1
X
X







0
1

.
0 1 1, 2 3 0. 4...7

, 6 7
.

ldi
ldi
out
out
nop
in

r16,(1PB7)|(1PB6)|(1PB1)|(1PB0)
r17,(1DDB3)|(1DDB2)|(1DDB1)|(1DDB0)
DDRB,rl7
;
PORTB,rl6
;
;
;
r16,PINB
;

2. /
ATmega128 16- / 1 T3. 8 / 0 2,
, ,
(- ).
16- /
/. 16- /
.
/ /:
16- TCNTn;
16- ICRn;
16- OCRnA, OCRnB, OCRnC;
8- TCCRnA, Rn, TCCRnC.
16-
/,
( ) L ( ). / T1 TCNT1,
, TCNT1H:TCNT1L. / 1 T3
:
;
(
);
.
16- /
TIFR/ETIFR, /
/ TIMSK/ETIMSK.
/ TCNTn
.
,
/ clk Tn.
, .
TCNTn .
/, ,
Vn .
1 OIn .
OCRnA/OCRnB/OCRnC .
/ ( )
TCNTn.
OCFnA/OCFnB/OCFnC
( ).

n/n/n . /

- ,
( DDRx 1).
ICRn ,
/
.
In , ( / 1)
.
ICFn .
1 TICIEn .
/ :
TCCRnA, TCCRnB, TCCRnB. . 2.12.3,
. 2.12.3.

)
. 2.1. TCCR1A (a), TCCR3A ()
2.1. TCCRnA

n1:n0
n1:n0
n1:n0

.
n .

/

WGMnl:WGMn0

/.
WGMn3:WGMn2 Rn
/ n (. . 7.25)

FOCnA

n.
FOCnx . 1 n
n1:n0x
TCCR/jA.
( ) .
,
. 0

FOCnB

, n = 1,3; = , .

)
. 2.2. TCCR1B (a), TCCR3B ().
2.2. TCCRnB

ICNCn

.
0, (
).
1,
,

ICESn

. \CESn
0,
.
1,
.

ICF/i

, 0

4,3 WGMn3:WGMn2

/. WG
n1:WGn TCCRnA
/ In (. 7.25)

2-0 CSn2...CSn0

.
(.
7.6.2)

)
. 2.3. TCCR1C (), TCCR3C ()
2.3. TCCRn

7

FOCnA

FOCnB

FOCnC

n.
n1 . 1 n
n1 n0 TCCRnA
(
) . ,

0

4..0 , 0
, = 1, 3, = ,
2.1.
16- / clk Tn (n = 1,3,)
. clk Tn
/ 1 T3, :
(clkTn = clkI/0);
(clkTn = clkI/0/N);
, 1 (T3) ( clk Tn =
clkEXT).
,
/ CSn2...CSn0
TCCRnB . 2.4.
2.4. 16- /
CSn2
CSn1
CSn0

0

clkI/0

clkI/0/8

clkI/0/64

clkI/0/256

clkI/0/1024

n,

n,

, n = 1,3.
2.2.
/ 1 T3
WGMn3:WGMn2 TCCRnB WGMn1:WGMn0
Rn. /
. 2.5.

2.5. 16- / 1 T3
W W W W


G G G G
/

M M M M
n
(TOP)
OCRnx
n3 n2 n1 n0
0

Normal

$FFFF

TOVn

$FFFF

Phase correct PWM, $00FF


8-

TOP

$0000

Phase correct PWM, $01FF


9-

TOP

$0000

Phase correct PWM, $03FF


10-

TOP

$0000

CTC
(
)

$FFFF

Fast PWM, 8-

$00FF

TOP

TOP

Fast PWM, 9-

$01FF

TOP

TOP

Fast
PWM,

10- $03FF

TOP

TOP

Phase and Frequency ICRn


Correct PWM

$0000

$0000

Phase and Frequency OCRnA


Correct PWM

$0000

$0000

10

Phase correct PWM

ICRn

TOP

$0000

11

Phase correct PWM

OCRnA

TOP

$0000

12

CTC
(
)

$FFFF

13

14

Fast PWM

ICRn

TOP

15 1
1
1
1
, n = 1,3.

Fast PWM

OCRnA

TOP

OCRnA

ICRn

2.2.1. Normal
/.
.
clk Tn .
$FFFF , $0000.
clkTn, TCNTn,
TOVn 1.
,
. n/n/n 16 / nx1:nx0
TCCRnA, . 2.6.
2.6. n/n/n Normal
COMnxl COMnx0

/ n nx

1
1
1
, n = 1,3,4,5; = , .

, . 1 FOCnA/FOCnB/FOCnC TCCRnC.
.
2.3. 16- /
/
:
1. /;
2. /;
3. OCRnA ICRn
( );
4. , /,
.
.
.org 0x0000
jmp main

//, ,
//
// .
//

.org 0x001C
jmp timer1ovf

//
// 1
timer1ovf:
//
// 1
{ ,
}
reti
//
main:
{ /, }
ldi r16,0x04
out TIMSK,r16
// 1
sei
//
{ }

2 (4 )
CTC -.


1. AVR.
2. CTC.

1.
:

" ".
;
.
INT0INT3

.
2. AVRStudio.
3. .
4. .

1. ATMega128
1.1.

.
PC
. , ,
.
RETI,
.
1.2.
AVR Mega
. , $0002,
.
, .

: , .
2 . ,
JMP.
.
,
,
.
MCUCR,
$35 ($55).


ATmega128 . 1.1.
, ,
.
1.1. ATmega128

INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
TIMER2COMP
TIMER2 0VF
TIMER1
TIMER1
TIMER1
TIMER1 OVF
TIMER0COMP
TIMER0OVF
SPI, STC
USARTO, RX
USARTO, UDRE
USARTO, TX
ADC
EE_RDY
ANA_COMP
TIMER1
TIMER3CAPT
TIMER3
TIMER3
TIMER3
TIMER3 OVF
USART1,RX
USART1,UDRE
USART1,TX
TWI
SPM_RDY

0
1
2
3
4
5
6
7
/ 2
/ 2
/ 1
/ 1
/ 1
/ 1
/
/
SPI
USARTO,
USARTO
USARTO,

EEPROM

/ 1
/ T3
/ T3
/ T3
/ T3
/ T3
USART1,
USART1
USART1,
TWI
SPM

M103C=1

1
$0002
2
$0004
3
$0006
4
$0008
5
$000A
6
$000C
7
$000E
8
$0010
9
$0012
10
$0014
11
$0016
12
$0018
13
$001A
14
$001C
15
$001E
16
$0020
17
$0022
18
$0024
19
$0026
20
$0028
21
$002A
22
$002C
23
$002E
24
$0030
25
$0032
26
$0034
27
$0036
28
$0038
29
$003A
30
$003C
31
$003E
32
$0040
33
$0042
34
$0044

M103C=0

1
$0002
2
$0004
3
$0006
4
$0008
5
$000A
6
$000C
7
$000E
8
$0010
9
$0012
10
$0014
11
$0016
12
$0018
13
$001A
14
$001C
15
$001E
16
$0020
17
$0022
18
$0024
19
$0026
20
$0028
21
$002A
22
$002C
23
$002E
-

,
.
1.3.
/ I
SREG. 1,
0. ()

/
, .
I SREG ,
.
1
. (
RETI) I .
.
,
. , ,
.
. , . 1
, .

, , .
, , ,
, .
,
SREG .

( ) RETI.
Mega ,
:
, (
), 1
.
.
4 .
.
.
, ,
.
,
4 5 .
4 ,
.
,
.
1.4.
Mega
.
.
.
/
EIMSK.

EIFR.

.1.1. EIMSK

.1.2 EIFR

INT0...INT7 /
.
INT0...INT3
EICRA. INT7...INT4
EICRB.

)
.1.3. EICRA () EICRB ()
1.2.
ISCn1
ISCn0

0
0
INTn
0
1

1
0
INTn
1
1
INTn
1.3.

PD0
INT0
0
PD1
INT1
1
PD2
INT2
2
PD3
INT3
3
PE4
INT4
4
PE5
INT5
5
PE6
INT6
6
PE7
INT7
7

2. /
ATmega128 16- / 1 3. 8 / 0 2,
, ,
. 16- /
/.
16- / .
/ /:
16- TCNTn;
16- ICRn;
16- OCRnA, OCRnB, OCRnC;
8- TCCRnA, Rn, TCCRnC.
16-
/,
( ) L ( ). / T1 TCNT1,
, TCNT1H:TCNT1L. / 1 3
:
;
(
);
.
16- /
TIFR/ETIFR, /
/ TIMSK/ETIMSK.
/ TCNTn
.
,
/ clk Tn.
, .
TCNTn .
/, ,
Vn .
1 OIn .
OCRnA/OCRnB/OCRnC .
/ ( )
TCNTn.
OCFnA/OCFnB/OCFnC
( ).

n/n/n . /
- ,
( DDRx 1).
ICRn ,
/
.
In , ( / 1)
.
ICFn .
1 TICIEn .
/ :
TCCRnA, TCCRnB, TCCRnC. . 2.12.3,
. 2.12.3.

)
. 2.1. TCCR1A (a), TCCR3A ()
2.1. TCCRnA

n1:n0
n1:n0
n1:n0

.
n .

/

WGMnl:WGMn0

/.
WGMn3:WGMn2 Rn
/ n (. . 7.25)

FOCnA

n.
FOCnx . 1 n
n1:n0x
TCCR/jA.
( ) .
,
. 0

FOCnB

, n = 1,3; = , .

)
. 2.2. TCCR1B (a), TCCR3B ().
2.2. TCCRnB

ICNCn

.
0, (
).
1,
,

ICESn

. \CESn
0,
.
1,
.

ICF/i

, 0

4,3 WGMn3:WGMn2

/. WG
n1:WGn TCCRnA
/ In (. 7.25)

2-0 CSn2...CSn0

.
(.
7.6.2)

)
. 2.3. TCCR1C (), TCCR3C ()
2.3. TCCRn

7

FOCnA

FOCnB

FOCnC

n.
n1 . 1 n
n1 n0 TCCRnA
(
) . ,
.
0

4..0 , 0
, n = 1, 3, x = ,

2.1.
16- / clk Tn (n = 1,3,)
. clk Tn
/ 1 T3, :
(clkTn = clkI/0);
(clkTn = clkI/0/N);
, 1 (T3) ( clk Tn =
clkEXT).
,
/ CSn2...CSn0
TCCRnB . 2.4.
2.4. 16- /
CSn2
CSn1
CSn0

0

clkI/0

clkI/0/8

clkI/0/64

clkI/0/256

clkI/0/1024

n,

n,

, n = 1,3.
2.2.
/ 1 T3
WGMn3:WGMn2 TCCRnB WGMn1:WGMn0
Rn. /
. 2.5.
2.5. 16- / 1 T3
W W W W


G G G G
/

M M M M
n
(TOP)
OCRnx
n3 n2 n1 n0
0

Normal

$FFFF

TOVn

$FFFF

Phase correct PWM, $00FF


8-

TOP

$0000

Phase correct PWM, $01FF


9-

TOP

$0000

Phase correct PWM, $03FF


10-

TOP

$0000

CTC
(
)

$FFFF

OCRnA

Fast PWM, 8-

$00FF

TOP

TOP

Fast PWM, 9-

$01FF

TOP

TOP

Fast
PWM,

10- $03FF

TOP

TOP

Phase and Frequency ICRn


Correct PWM

$0000

$0000

Phase and Frequency OCRnA


Correct PWM

$0000

$0000

10

Phase correct PWM

ICRn

TOP

$0000

11

Phase correct PWM

OCRnA

TOP

$0000

12

CTC
(
)

$FFFF

13

14

Fast PWM

ICRn

TOP

15 1
1
1
1
, n = 1,3.

Fast PWM

OCRnA

TOP

ICRn

( )

,
clkTn.
, ,
A OCRnA (WGMn3:0 = 0100), ICRn
(WGMn3:0 = 1100).
$0000. Normal, TOVn
$FFFF $0000.
:
OCFnA, OCRnA
(WGMn3:0 = 0100);
ICFn, ICRn (WGMn3:0=1100).
n
. n:1:n0
TCCRnx, . 2.6.
2.6. OCnA/OCnB/n
COMnxl COMnx0

/ n nx

1
1
1
, n = 1,3,4,5; = , .
Normal, n/n/n
, . 1

FOCnA/FOCnB/FOCnC Rn. ,
.
2.3. /
ATmega128 / /
/: TIMSK ETIMSK.
, : TIFR
ETIFR.
, /
/, . 2.4, . 2.7.
- /
1 TIMSK(ETIMSK) , , I
SREG.

)
. 2.4. TIMSK () ETIMSK ()
2.7. TIMSK, ETIMSK

TOIEn
/
Tn
OCIEn

/ Tn
OCIEnA
A
/ Tn
OCIEnB
B
/ Tn
OCIEnC
C
/ Tn
TICIEn

/ Tn
,
/, . 2.5, . 2.8.

)
. 2.5. TIFR () ETIFR ()
2.8. TIFR ETIFR

TOVn
/ Tn
OCFn
/ Tn
OCFnA
A /
Tn
OCFnB
B /
Tn
OCFnC
C /
Tn
ICFn
/ Tn
-
TIFR/ETIFR 1.
0. ,
. 0.
2.4. /

/ clkT0, clkT1, clkT2, clkT3.
/, ,
10- .
/ .
2.4.1.
/,
,
.
SFIOR. . 2.6 (,
/, X).

. 2.6. / SFIOR
/ PSRx .
. 1 /
. 0
. , ,
/,
/, .

. 1
TSM SFIOR.
TSM . 0. , ,
/. TSM PSRx

. TSM PSRx
/ .

3 (4 )


1.
ATmega128.
2.
ATmega128.

1. 8- CTC .
2. CTC T0,
/ .
3. , 0
f
f
f
f
: f OCn = clk _ IO , f OCn = clk _ IO , f OCn = clk _ IO , f OCn = clk _ IO .
8
128
256
512
.
4. 0 - ,
0, 25%, 50%,
75%.

5. .
6. .
1.
1.1.
ATmega128 /
:
8- / 0;
16- / 1;
8- / 2;
16- / 3.
/ .
,
- ()
( )
.
/ 1
. ,
. / ,
2- 3- - , .
/ 2 / ,
, ,
.
/
T3

/ 1.

,
.
,
.
1.2. /
/ .
/ , ,
/,
.
, /
, . 1.1. .
/

.
1.1. , /

OC0
PB4
0
T1
PD6
1
ICP1
PD4
1
OC1A
PB5
OC1B
PB6
1
OC1C
PB7
T2
PD7
2
OC2
PB7
2
T3
PE6
3
ICP3
PE7
3
OC3A
PE3
OC3B
PE4
3
OC3C
PE5
1.3. /
ATmega128 / /
/: TIMSK ETIMSK.
, : TIFR
ETIFR.
, /
/, . 1.1, . 1.2.
- /
1 TIMSK(ETIMSK) , , I
SREG.

)
. 1.1. TIMSK () ETIMSK ()
1.2. TIMSK, ETIMSK

TOIEn
/
Tn
OCIEn

/ Tn
OCIEnA
A
/ Tn
OCIEnB
B
/ Tn
OCIEnC
C
/ Tn
TICIEn

/ Tn
,
/, . 1.2, . 1.3.

)
. 1.2. TIFR () ETIFR ()
1.3. TIFR ETIFR

TOVn
/ Tn
OCFn
/ Tn
OCFnA
A / Tn
OCFnB
B / Tn
OCFnC
C / Tn
ICFn
/ Tn
-
TIFR/ETIFR 1.
0. ,
. 0.

1.4. /

/ clkT0, clkT1, clkT2, clkT3.
/, ,
10- .
/ .
1.4.1.
/,
,
.
SFIOR. . 1.3 (,
/, X).

. 1.3. / SFIOR
/ PSRx .
. 1 /
. 0
. , ,
/,
/, .
. 1
TSM SFIOR.
TSM . 0. , ,
/. TSM PSRx

. TSM PSRx
/ .
1.5. /
2
,
8- -. 0 2
, (
).
, 1- -.
1.4. /

TCCR0

TCNT0

OCR0

TCCR2

TCNT2

OCR2

ASSR

/ TCNTn
.
,
/ clkT0 (clkT2).
, ,
, . ,

/. TCNTn
. /
( )
TOVn; TIFR/ETIFR.
1 OIEn TIMSK/ETIMSK. ,
I SREG 1.
OCRn .
/ ( )
TCNTn.
n
( ). ,
n .
/ ,
( DDRx
1).
, .
Rn /.
. 1.4,
. 1.5.

. 1.4. TCCR0 () TCCR2 ()


1.5. TCCR0 (TCCR2)

7
FOCn
OCn
( Normal ). . 1
n
n1 :n.
( )
. Fast PWM Phase Correct PWM
0.
0.
6, 3
WGMn1
/.

5, 4

WGMn0
COMn1
COMn0

2..0

CSn2..CSn0

/ . 1.6.
.
n
.

/
.
/
/

1.6. /

WGMn1 WGMn2
/ 0

0
0
0
Normal
1
0
1
Phase Correct PWM
2
1
0
CTC ( )
3
1
1
Fast PWM
1.5.1.
/ clk T0 (clkT2)
. clk T0 (clkT2) / T2,
, :
(clkT0(2) = clkI/0);
(clkT0(T2) = clkI/0/n;
, (2) (1k0(2) =
1k).
/
clk I/0 (clkT0 (2) = clkI/0/n),
(clk T0(T2) =
clkTOSCI/n.
ASO ASSR.
,
/ CS02...CS00 (CS22...CS20)
TCCRn . 1.7.
1.7. / 2

CSn2 CSn1 CSn0 /
/
ASn=0
ASn=1
0
0
0
/
/
0
0
1
clkI/O
clkI/O
clkTOSCI
0
1
0
clkI/O/8
clkI/O/8
clkTOSCI/8
0
1
1
clkI/O/64
clkI/O/32
clkTOSCI/32
1
0
0
clkI/O/256
clkI/O/64
clkTOSCI/64
1
0
1
clkI/O/1024
clkI/O/128
clkTOSCI/128
1
1
0
n,
clkI/O/256
clkTOSCI/256


1
1
1
n,
clkI/O/1024
clkTOSCI/1024


1.5.2.
/ (2)
WGMn2:WGMnO TCCRn. /
. 1.8.
1.8. / 0 2

WGMn1 WGMn0

(TOP)
/

0
0
0
Normal
$FF
1
0
1
Phase
$FF
Correct
PWM
2
1
0
CTC
OCRn
(

)
3
1
1
Fast
$FF
PWM

OCRn

TOVn

TOP

$FF
$00

$FF

TOP

$FF

( )

,
clkTn. ,
,
OCRn. , ,
$00. $FF,
clkTn, ,
TOVn .
OCFn,
, IEn 1,
.
n . n1:n0
TCCR, . 1.9.
1.9. n
COMn1
COMn0

0
0
/ Tn n
0
1

1
0
0
1
1
1

n1:n 01 ( ).

f OCn =

f clk _ IO

2 N (1 + OCRnx )
N .
n
. 1 FOCn .
.
Fast PWM
Fast PWM ( )
- .

, , , -
.
,

clkTn. $00 ,
.
TOVn
,
Fn OCFn.
$FF.

OCRn, ,
,

.
() ,
.
n
n1:n0 TCCRn.
1.10. OCn Fast PWM

. 1.5. - Fast PWM



f clk _ IO
f OCn =
256 N
N .
2. ATMega128
2.1.

.
PC
. , ,
.
RETI,
.
2.2.
AVR Mega
. , $0002,
.
, .

: , .
2 . ,
JMP.
.
,
,
.
MCUCR,
$35 ($55).


ATmega128 . 2.1.
, ,
.
2.1. ATmega128

INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
TIMER2COMP
TIMER2 0VF
TIMER1
TIMER1
TIMER1
TIMER1 OVF
TIMER0COMP
TIMER0OVF
SPI, STC
USARTO, RX
USARTO, UDRE
USARTO, TX
ADC
EE_RDY
ANA_COMP
TIMER1
TIMER3CAPT
TIMER3
TIMER3
TIMER3
TIMER3 OVF
USART1,RX
USART1,UDRE
USART1,TX
TWI
SPM_RDY

0
1
2
3
4
5
6
7
/ 2
/ 2
/ 1
/ 1
/ 1
/ 1
/
/
SPI
USARTO,
USARTO
USARTO,

EEPROM

/ 1
/ T3
/ T3
/ T3
/ T3
/ T3
USART1,
USART1
USART1,
TWI
SPM

M103C=1

1
$0002
2
$0004
3
$0006
4
$0008
5
$000A
6
$000C
7
$000E
8
$0010
9
$0012
10
$0014
11
$0016
12
$0018
13
$001A
14
$001C
15
$001E
16
$0020
17
$0022
18
$0024
19
$0026
20
$0028
21
$002A
22
$002C
23
$002E
24
$0030
25
$0032
26
$0034
27
$0036
28
$0038
29
$003A
30
$003C
31
$003E
32
$0040
33
$0042
34
$0044

M103C=0

1
$0002
2
$0004
3
$0006
4
$0008
5
$000A
6
$000C
7
$000E
8
$0010
9
$0012
10
$0014
11
$0016
12
$0018
13
$001A
14
$001C
15
$001E
16
$0020
17
$0022
18
$0024
19
$0026
20
$0028
21
$002A
22
$002C
23
$002E
-

,
.
2.3.
/ I
SREG. 1,
0. ()

/
, .
I SREG ,
.
1
. (
RETI) I .
.
,
. , ,
.
. , . 1
, .

, , .
, , ,
, .
,
SREG .

( ) RETI.
Mega ,
:
, (
), 1
.
.
4 .
.
.
, ,
.
,
4 5 .
4 ,
.
,
.
2.4.
Mega
.
.
.
/
EIMSK.

EIFR.

.2.1. EIMSK

.2.2 EIFR

INT0...INT7 /
.
INT0...INT3
EICRA. INT7...INT4
EICRB.

)
.2.3. EICRA () EICRB ()
2.2.
ISCn1
ISCn0

0
0
INTn
0
1

1
0
INTn
1
1
INTn
2.3.

PD0
INT0
0
PD1
INT1
1
PD2
INT2
2
PD3
INT3
3
PE4
INT4
4
PE5
INT5
5
PE6
INT6
6
PE7
INT7
7
3. /
3.1.

,
.
/
.
, ,
.

.
.

.
Mega (
AVR)
/
//.
( SBI CBI), .
/,
( )
( ).

. 3.1. /

3.2. /
/.
/ 3 ,
: PORTx,
DDRx PINx.
. ,
PORTA, DDRA, PINA, - PORTB, DDRB, PINB . .
PINx
, ,
, .
3.3. /
/ n
/ . 1.1.
/: PORTxn
( PORTx), DDxn ( DDRx) INxn ( PINx).

n.
. ,
, .

0.
DDxn DDx
/ 1, n- ,
0 .
ORTxn PORTx .
(DDxn = 1), .
1, .
0, .
(DDxn = 0), PORTxn
.
ORTxn 1
.
.
( ) PUD
SFIOR.

. 3.2. SFIOR
PUD 0 ( ),
PORTxn .
PUD 1,
.
( DDxn)
PINxn PINx. ,
PINx
. , ,
. 3.1, PINxn -.
-

INxn
. , 0.5 1.5
.

NOP. OUT
SYNC LATCH 1 ,
.

. 3.1.
3.1.
DDxn PORTxn
PUD

0
0
X

0
1
0

0
1
1

1
0
1

1
X
X







0
1

.
0 1 1, 2 3 0. 4...7
, 6 7
.

ldi
ldi
out
out
nop
in

r16,(1PB7)|(1PB6)|(1PB1)|(1PB0)
r17,(1DDB3)|(1DDB2)|(1DDB1)|(1DDB0)
DDRB,rl7
;
PORTB,rl6
;
;
;
r16,PINB
;

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