Digital Integrated Circuits Adders

Digital Integrated Circuits Lecture 11: Adders
Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw
DIC-Lec11 cwliu@twins.ee.nctu.edu.tw
Outline

Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder
Single-Bit Addition
A B
A B C S
Half Adder S= Cout =

A 0 0 1 1 B 0 1 0 1
Full Adder
Cout S
S= Cout =
Cout
Cout
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Cout S
Single-Bit Addition
A B
A B C
Half Adder S = A B Cout = A B

A 0 0 1 1 B 0 1 0 1 0 0 0 1
Full Adder
Cout S
S = A B C Cout Cout = MAJ ( A, B, C ) S
Cout
S 0 1 1 0
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Cout S 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1
4
Cout = ABC + A BC + ABC + ABC = ( ABC + ABC ) + ( ABC + A BC ) + ( ABC + ABC ) = AB + AC + BC
Remarks
PGK
For a full adder, define what happens to carries
Generate: Cout = 1 independent of C G = Propagate: Cout = C P = Kill: Cout = 0 independent of C K =
PGK
For a full adder, define what happens to carries Generate: Cout = 1 independent of C G=AB Propagate: Cout = C P=AB Kill: Cout = 0 independent of C
K = A B = A + B
Remarks
Cout = AB + AC + BC = AB + C ( A + B )
= AB + C ( A + B ) = ( A + B ) (C + A B ) = AB + C ( A + B ) = MAJ( A, B, C )
1. Q MAJ( A, B, C ) = AB + C ( A + B) MIN( A, B, C ) = AB + C ( A + B)
2. Cout = MAJ( A, B, C ) = AB + C ( A + B)
S = A BC + ABC + ABC + ABC

= ABC + ABC + ABC + ABC = ABC + ( A + B + C )( AB + AC + BC ) = ABC + ( A + B + C )Cout
DIC-Lec11 cwliu@twins.ee.nctu.edu.tw 8
Full Adder Design I
Brute force implementation from eqns
S = A B C Cout = MAJ ( A, B, C )
A A B B
32 transistors
C C
gate
A B C A B C MAJ B S Cout
A B B
Cout = A B + C ( A + B)
S A C B B A A B B
9
C C B A B
C C B
Cout
C A
Full Adder Design II
Factor S in terms of Cout S = ABC + (A + B + C)(~Cout) Critical path is usually C to Cout in ripple adder
MINORITY A B C Cout S S
28 transistors
DIC-Lec11 cwliu@twins.ee.nctu.edu.tw Cout
10
Remarks

Feed the carry-in signal to the inner inputs Make all transistors in the sum logic whose gate signals are connected to the carry-in and carry logic minimum size (This will minimize the branching effort on the critical path) Build an asymmetric gate that reduces the logical effort from C to ~Cout at the expense of effort to S Use relatively large transistors on the critical path
11
Layout
Clever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters
12
CPL
Complementary Pass-transistor Logic Dual-rail form of pass transistor logic Avoids need for ratioed feedback Optional cross-coupling for rail-to-rail swing
S A S B S A S B L Y
13
Full Adder Design III
Complementary Pass Transistor Logic (CPL) Using transmission gate to form multiplexers and XORs Slightly faster, but more area
Cout = ABC + A BC + ABC + ABC = C ( AB + AB ) + AB = AB + C ( A B )
B B B B B B B C C C C
S = ( A B) C = P C
B B A B A B C S A Cout C C C A S
Cout
B DIC-Lec11 cwliu@twins.ee.nctu.edu.tw
14
Full Adder Design IV
Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers
C_h A_h B_h A_h B_h Cout _h C_l A_l B_l A_l B_l Cout _l
S_l C_h B_h A_h
C_l B_l C_h B_h A_l
S_h
S = A B C Cout = MAJ ( A, B, C )
15
Carry Propagate Adders (CPAs)
N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickly?
AN...1 BN...1 Cout Cin
Cout Cout
Cin
Cin carries A4...1 B4...1 S4...1
+ SN...1
00000 1111 +0000 1111
11111 1111 +0000 0000
16
Carry-Ripple Adder
Simplest design: cascade full adders Critical path goes from Cin to Cout Design full adder to have fast carry delay
A4 Cout S4
B4
A3 C3 S3
B3
A2 C2 S2
B2
A1 C1 S1
B1 Cin
17
Inversions
Critical path passes through majority gate

Built from minority + inverter Eliminate inverter and use inverting full adder
Because addition is a symmetric function, an inverting full adder receiving complementary inputs produces true outputs
A4 B4 A3 B3 A2 B2 A1 B1
Cout
C3 S4
C2
C1 S1
Cin
S3 cwliu@twins.ee.nctu.edu.tw S2 DIC-Lec11
18
Generate / Propagate

Equations often factored into G and P Generate and propagate for groups spanning i:j Gi: j =
Pi: j =
0:00:0 in
0 GC
Base case
Gi:i Gi = Pi:i Pi =
G0:0 G0 = P0:0 P0 =
Sum:
Si =
Propagate & Generate in Full Adder
For a full adder, Generate: Cout = 1 independent of C G=AB Propagate: Cout = C P=AB
A group of bits generates a carry if its carry-out is true independent of the carry-in A group of bits propagates a carry if its carry-out is true when there is a carry-in
20
Generate / Propagate

Equations often factored into G and P Generate and propagate for groups spanning i:j Gi: j = Gi:k + Pi:k Gk 1: j Step-3 0 GC P =P P
i: j i :k k 1: j
0:00:0 in
Base case
Gi:i Gi = Ai Bi Pi:i Pi = Ai Bi
G0:0 G0 = Cin P0:0 P0 = 0
Step-1
Sum:
Si = Pi Gi 1:0
Step-2
21
PG Logic
A4 B4 A3 B3 A2 B2 A1 B1 Cin
1: Bitwise PG logic G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
2: Group PG logic G3:0 C3 G2:0 C2 G1:0 C1 G0:0 C0 3: Sum logic
Routine steps
C4 Cout S4 S3 S2 S1
22
Carry-Ripple Revisited
An extreme case
Gi:0 = Gi + Pi
One-bit group
A4
Gi 1:0
B4 A3 B3 A2
4-bit carry-ripple adders

B2 A1 B1 Cin
G4
P4
G3
P3
G2
P2
G1
P1
G0
P0
3 AND-OR gates
G3:0 C3
G2:0 C2
G1:0 C1
G0:0 C0
C4 Cout S4DIC-Lec11 cwliu@twins.ee.nctu.edu.tw S3 S2 S1

23
Carry-Ripple PG Diagram
Bit Position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tripple = t pg + ( N 1)t AO + txor
Delay
AND-OR gate
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
24
PG Diagram Notation
Black cell i:k k-1:j Gray cell i:k k-1:j Buffer i:j
i:j G i:k P i:k G k-1:j P k-1:j G i:j G i:k P i:k G k-1:j
i:j G i:j
i:j
G i:j P i:j
G i:j P i:j
P i:j
Gi: j = Gi:k + Pi:k Pi: j = Pi:k Pk 1: j
Gk 1: j
25
Carry-Skip Adder

Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal
4-bit group
A16:13 B16:13 P16:13 A12:9 B12:9 P12:9 C12 + S16:13 1 0 + C8 1 0 + S8:5 A8:5 B8:5 P8:5 C4 1 0 + S4:1 Cin A4:1 P4:1 B4:1
Cout
1 0
Skip S12:9 Multiplexor
Also called Carry-bypass Adder

Carry-Skip PG Diagram
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
For k n-bit groups (N = nk)

tskip =
Remarks
The critical path begins with generating a carry from bit-1, and then propagating it through the remainder of the adder. The carry must ripple through the first n-bit group adder, but then may skip across the other n-bit group adder Finally, the carry must ripple through the final n-bit group adder to produce the sum. The final AND-OR and column 16 are not strictly necessary because Cout can be computed in parallel with the sum XORs
28
Carry-Skip PG Diagram
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
For k n-bit groups (N = nk)

Delay grows as O(sqrt(N))
tskip = t pg + 2 ( n 1) + (k 1) t AO + txor
Depend on the first and the last group and the number of groups
29
Variable Group Size

Groups of length [2, 3, 4, 4, 3]
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Delay grows as O(sqrt(N))

Carry-Lookahead Adder
Carry-lookahead adder computes Gi:0 for many bits in parallel. Uses higher-valency cells with more than two inputs.
A16:13 B16:13 Cout G16:13 P16:13 + S16:13 C12
A12:9 B12:9 G12:9 P12:9 + S12:9 C8
A8:5 B8:5 G8:5 P8:5 + S8:5 C4
A4:1 G4:1 P4:1 +
B4:1
Cin
S4:1
Tempt to replace the skip multiplexer with AND-OR gate to reduce delay
CLA PG Diagram
higher-valency cells
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
32
Higher-Valency Cells
i:k k-1:l l-1:m m-1:j
i:j
G i:k P i:k G k-1:l P k-1:l G l-1:m P l-1:m G m-1:j P m-1:j
G i:j
P i:j
33
Carry-Select Adder
Trick for critical paths dependent on late input X

Precompute two possible outputs for X = 0, 1 Select proper output when X arrives For both possible carries into n-bit group
A16:13 B16:13 + 0 C12 1 1 A12:9 B12:9 + 0 C8 + 1 0 A8:5 + B8:5 0 C4 + A4:1 B4:1
One assumes the carry-in of 0 The other is carry-in of 1
Carry-select adder precomputes n-bit sums
Cout + 1 0 S16:13
+ 0 S12:9
Cin
S8:5
S4:1
34
Remarks
The two n-bit adders are redundant in that both contain the initial PG logic and final sum XOR.
A4 B4 A3 B3 A2 B2 A1 B1 Cin
1: Bitwise PG logic G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
2: Group PG logic G3:0 C3 G2:0 C2 G1:0 C1 G0:0 C0 3: Sum logic
C4 Cout S4 S3 S2 S1
35
Carry-Increment Adder
Factor initial PG and final XOR out of carry-select

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Black cells are used to compute PG signals

15:12
13:12 14:12 11:8 10:8
9:8 6:4 7:4
5:4
About twice as many cells as carry-ripple adder
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
tincrement = t pg + ( n 1) + (k 1) t AO + txor
Variable Group Size
Also buffer noncritical signals
15
14
13
12
11
10
12:11 13:11 9:7
8:7
5:4 6:4
3:2
14:11 15:11
10:7
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
12:11 13:11 9:7
8:7
5:4 6:4 6:0
3:2 3:0
1:0
14:11 15:11
10:7
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
37
Tree Adder
The delay of passing the carry through the lookahead stages dominate the delay of carry-lookahead (or carry-skip, carry-select) adder
t adder t pg + (2 N )t AO + t xor
If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay
t adder t pg + (log 2 N )t AO + t xor
Many variations on tree adders
38
Brent-Kung
2-bit group
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
15:12
11:8
7:4
3:0
15:8
7:0
11:0
13:0
9:0
5:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Sklansky
15
14
13
12
11
10
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
15:12 14:12
11:8 10:8
7:4
6:4
3:0
2:0
15:8
14:8
13:8
12:8
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
40
Kogge-Stone
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14 14:13 13:12 12:11 11:10 10:9
9:8
8:7
7:6
6:5
5:4
4:3
3:2
2:1
1:0
15:12 14:11 13:10
12:9
11:8 10:7
9:6
8:5
7:4
6:3
5:2
4:1
3:0
2:0
15:8
14:7
13:6
12:5
11:4 10:3
9:2
8:1
7:0
6:0
5:0
4:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
41
Tree Adder Taxonomy
Ideal N-bit tree adder would have L = log2 N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels: L+l Fanout: 2f + 1 Wiring tracks: 2t Known tree adders sit on plane defined by l + f + t = L-1
Tree Adder Taxonomy

l (Logic Levels) 3 (7) f (Fanout) 2 (6) 3 (9) 2 (5) 1 (3) 0 (2) 0 (4) 0 (1)
1 (5)
1 (2)
2 (4)
3 (8)
t (W ire Tracks)
43
Tree Adder Taxonomy

l (Logic Levels) 3 (7) f (Fanout) Sklansky 3 (9) 2 (5) 1 (3) 0 (2) 0 (4) 0 (1) 2 (6) Brent-Kung
1 (5)
1 (2)
2 (4)
Kogge-Stone 3 (8)
t (W ire Tracks)
44
Han-Carlson
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
15:12
13:10
11:8
9:6
7:4
5:2
3:0
15:8
13:6
11:4
9:2
7:0
5:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
45
Knowles [2, 1, 1, 1]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14 14:13 13:12 12:11 11:10 10:9
9:8
8:7
7:6
6:5
5:4
4:3
3:2
2:1
1:0
15:12 14:11 13:10
12:9
11:8 10:7
9:6
8:5
7:4
6:3
5:2
4:1
3:0
2:0
15:8
14:7
13:6
12:5
11:4 10:3
9:2
8:1
7:0
6:0
5:0
4:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
46
Ladner-Fischer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
15:12
11:8
7:4
3:0
15:8
13:8
7:0
5:0
15:8
13:0
11:0
9:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
47
Taxonomy Revisited
(f) Ladner-Fischer
(b) Sklansky
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14
15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0
1 5
1 4
1 3
1 2
1 1
1 0
13:12
11:10
9:8
7:6
5:4
3:2
1:0
15:12
15:12 14:12 11:8 10:8 7:4 6:4 3:0 2:0
11:8
7:4
3:0
l (Logic Levels) BrentKung 3 (7)

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
15:8 13:8 7:0 5:0
15:8
14:8
13:8
12:8
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
f (Fanout) Sklansky 3 (9) 2 (5)

(e) Knowles [2,1,1,1]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LadnerFischer
LadnerFischer
15:8
13:0
11:0
9:0
2 (6)
(a) Brent-Kung
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 (5)
15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0
1 (3) 0 (2) New (1,1,1)
0 (4) 0 (1)
HanCarlson
15:12
11:8
7:4
3:0
15:8
7:0
15:14 14:13 13:12 12:11 11:10 10:9
9:8
8:7
7:6
6:5
5:4
4:3
3:2
2:1
1:0
15:12 14:11 13:10
12:9
11:8 10:7
9:6
8:5
7:4
6:3
5:2
4:1
3:0
2:0
Knowles [4,2,1,1]
11:0
13:0
15:8 14:7 13:6 12:5 11:4 10:3 9:2 8:1 7:0 6:0 5:0 4:0
9:0
5:0
1 (2)
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Knowles [2,1,1,1] 2 (4)
HanCarlson
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
(d) Han-Carlson
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(c) Kogge-Stone
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
15:14 14:13 13:12 12:11 11:10 10:9
9:8
8:7
7:6
6:5
5:4
4:3
3:2
2:1
1:0
Kogge3 (8) Stone
15:12
13:10
11:8
9:6
7:4
5:2
3:0
15:12 14:11 13:10
12:9
11:8 10:7
9:6
8:5
7:4
6:3
5:2
4:1
3:0
2:0
15:8
13:6
11:4
9:2
7:0
5:0
15:8
14:7
13:6
12:5
11:4 10:3
9:2
8:1
7:0
6:0
5:0
4:0
t (Wire Tracks)
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
48
Summary
Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application.
Architecture Carry-Ripple Carry-Skip n=4 Carry-Inc. n=4 Brent-Kung Sklansky Kogge-Stone (L-1, 0, 0) (0, L-1, 0) (0, 0, L-1) Classification Logic Levels N-1 N/4 + 5 N/4 + 2 2log2N 1 log2N log2N Max Fanout 1 2 4 2 N/2 + 1 2 Tracks 1 1 1 1 1 N/2 Cells N 1.25N 2N 2N 0.5 Nlog2N Nlog2N
49

Digital Integrated Circuits Adders

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Digital Integrated Circuits Adders

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Digital Integrated Circuits Lecture 11: Adders

Half Adder S= Cout =

Half Adder S = A B Cout = A B

S = A B C Cout Cout = MAJ ( A, B, C ) S

Cout = ABC + A BC + ABC + ABC = ( ABC + ABC ) + ( ABC + A BC ) + ( ABC + ABC ) = AB + AC + BC

For a full adder, define what happens to carries

Generate: Cout = 1 independent of C G = Propagate: Cout = C P = Kill: Cout = 0 independent of C K =

S = A BC + ABC + ABC + ABC

Full Adder Design I

Brute force implementation from eqns

Full Adder Design II

DIC-Lec11 cwliu@twins.ee.nctu.edu.tw Cout

Full Adder Design III

Full Adder Design IV

S_l C_h B_h A_h

C_l B_l C_h B_h A_l

Carry Propagate Adders (CPAs)

Cin carries A4...1 B4...1 S4...1

00000 1111 +0000 1111

11111 1111 +0000 0000

Critical path passes through majority gate

Propagate & Generate in Full Adder

G0:0 G0 = Cin P0:0 P0 = 0

2: Group PG logic G3:0 C3 G2:0 C2 G1:0 C1 G0:0 C0 3: Sum logic

4-bit carry-ripple adders

C4 Cout S4DIC-Lec11 cwliu@twins.ee.nctu.edu.tw S3 S2 S1

tripple = t pg + ( N 1)t AO + txor

i:j G i:k P i:k G k-1:j P k-1:j G i:j G i:k P i:k G k-1:j

Gi: j = Gi:k + Pi:k Pi: j = Pi:k Pk 1: j

Skip S12:9 Multiplexor

Also called Carry-bypass Adder

For k n-bit groups (N = nk)

For k n-bit groups (N = nk)

Variable Group Size

Delay grows as O(sqrt(N))

A16:13 B16:13 Cout G16:13 P16:13 + S16:13 C12

A12:9 B12:9 G12:9 P12:9 + S12:9 C8

A8:5 B8:5 G8:5 P8:5 + S8:5 C4

A4:1 G4:1 P4:1 +

i:k k-1:l l-1:m m-1:j

G i:k P i:k G k-1:l P k-1:l G l-1:m P l-1:m G m-1:j P m-1:j

Trick for critical paths dependent on late input X

One assumes the carry-in of 0 The other is carry-in of 1

Carry-select adder precomputes n-bit sums

2: Group PG logic G3:0 C3 G2:0 C2 G1:0 C1 G0:0 C0 3: Sum logic

Factor initial PG and final XOR out of carry-select

Black cells are used to compute PG signals

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9:8 6:4 7:4

About twice as many cells as carry-ripple adder

Variable Group Size

Also buffer noncritical signals

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12:11 13:11 9:7

5:4 6:4 6:0

t adder t pg + (log 2 N )t AO + t xor

Many variations on tree adders

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Tree Adder Taxonomy

Tree Adder Taxonomy

Tree Adder Taxonomy

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