Half Adder using Verilog

module halfadder(a,b,sum,carry); input a,b; output sum, carry; wire sum, carry; assign sum = a^b; // sum bit assign carry = (a&b) ;//carry bit endmodule

Full Adder using Verilog

module fulladder(a,b,c,sum,carry); input a,b,c; output sum,carry; wire sum,carry; assign sum=a^b^c; // sum bit assign carry=((a&b) | (b&c) | (a&c)); //carry bit endmodule

Half Subtractor
module half_subtractor ( a ,b ,diff ,borrow ); output diff ; output borrow ; input a ; input b ; assign diff = a ^ b; assign borrow = (~a) & b; endmodule

Full Subtractor
module fs(a, b, c, borrow, difference); input a; input b; input c; output borrow; output difference; wire d,e,f; xor(difference,a,b,c); and(d,~a,b); and(e,b,c); and(f,~a,c); or(borrow,d,e,f); endmodule

Multiplexer module mux ( y, I1, I2, I3, I4, S0, S1); input I1, I2, I3, I4, S0, S1; output y; wire S1bar, S0bar, a, b, c, d; not (S1bar, S1); not (S0bar, S0); and (a, S1bar, S0bar, I1); and (b, S1bar, S0, I2); and (c, S1, S0bar, I3); and (d, S1, S0, I4); or (y, a, b, c, d); endmodule

Demultiplexer
module mux ( Y1, Y2, Y3, Y4, I, S0, S1); input I, S0, S1; output Y1, Y2, Y3, Y4; wire S1bar, S0bar; not (S1bar, S1); not (S0bar, S0); and (Y1, S1bar, S0bar, I); and (Y2, S1bar, S0, I); and (Y3, S1, S0bar, I); and (Y4, S1, S0, I); or (y, a, b, c, d); endmodule