Dts Chuong III 2012

Logic Gates - Logic Circuits - Digital Integrated Circuits and Their SPECIFICATIONS
Cng logic - Mch logic - Mch tch hp s

(Logic Gates - Logic Circuits - Digital Integrated Circuits)
I. Cng logic
1. Mc logic (Logic Level) 2. Cng logic (Logic Gates) 3. Cc cng logic c bn (Basic Logic Gates)
II. Mch logic

1. Mch logic (Logic Circuits) v nguyn tc ghp ni cc cng logic 2. Phn loi mch logic (Combinational & Sequential Logic Circuits) 3. Bi ton phn tch & tng hp mch logic (Analysis & Synthesis Logic Circuits)
III. Chuyn i mc tch cc

1. Khi nim mc tch cc v mc thit lp (Active level 2. khi nim chuyn i mc tch cc 3. Chuyn i mc tch cc cho cng logic 4. Chuyn i Mc tch cc cho mch logic v ngha. Asserted level)
IV. Mch tch hp s

1. Khi nim mch tch hp s (Digital Integrated Circuit), mc tch hp (Scale of integration) 2. Cc h IC s (Digital IC Families), gii thiu cc h TTL, CMOS, NMOS, ECL ... 3. u ra ba trng thi (Tristate Output), u ra collector m (Open collector Output) 4. Cc c tnh ca IC s 5. Ghp ni cc IC s
Ging vin : TS. L Dng
Vin in t - Vin thng - H Bch Khoa H Ni
Mc logic (LOgic Level)
mc logic cc h IC s
cng logic (Logic Gate)

nh ngha : L mch in t thc hin hm logic c bn trn hai mc logic "HIGH" v "LOW" cng ging nh hm logic thc hin trn cc khi nim "True" v "False".
Nguyn L hot ng :
Cc cng logic c bn
Logic Gate Traditional Logic Symbol IEEE/ANSI Logic Symbol Function Truth Table INPUT OUTPUT
INVERTER (NOT)
B Z=A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AND
A B
A Z B A Z B A Z & B A Z B A Z =1 B A Z =1 B Z Z Z 1 & Z
Z = A.B
OR
A B
Z=A+B
NAND
A B
Z = A.B
NOR
A B
Z=A+B
XOR
A B
Z=AB
XNOR
A B
Z=A~ B =AB
A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Z 1 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 0 0 1
VI DU cng logic INverter VA IC 74LS04 (Hex inverters)
Inverter gate in 7400
Inverter gate in 74LS00

(Low power Shottkey)
VI DU cng logic NAND VA IC 7400 (Quadruple 2-input NAND Gate)
CAC VI DU KHAC
7410
Triple 3-input NAND gate
7420
Dual 4-input NAND gate
7486
Quad 2-input XOR gate
7454
4-Wide 2-Input AND-OR-Invert Gate
Mch Logic (Logic Circuit)

nh ngha : L mch in t c xy dng bng cch ghp ni cc cng logic li vi nhau, v thc hin mt m hnh bi ton logic no (cng lm vic vi 2 mc logic).
Nguyn Tc ghp ni :
Phi ph hp mc logic. Mt u ra c th ni n mt s u vo. Ni chung khng c ni cc u ra trc tip vi nhau. Khng nn u vo th ni (Floating).
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Phn loi Mch Logic

M hnh logic (otomat)
(Model Logic)
otomat khng nh Truth tables x ---F---> Z
otomat c nh State Tables (X,S) --- F ---> Z (X,S) --- G ---> S
x0 X xn-1
. . .
Mch logic t hp
Combinational Logic Circuit (F)
. . .
z0 Z zm-1
x0 X xn-1
S
. . .
Mch logic dy
Sequential Logic Circuit (F,G)
. . .
z0 Z zm-1
Memory
(S)
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Bi ton phn tch v tng hp Mch Logic

(Analysis & Synthesis logic circuits)
Bi ton thc t
Cc thc th
Cc Quan h cn c trn cc chc nng
xy dng M hnh logic Bi ton Phn tch ( analysis) thc hin bng mch in t
Bi ton Tng hp ( synthesis)
mch logic
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khi nim Mc tch cc

(Active Level
mc thit lp
Active Level - Active High - Active Low - Active by PGT - Active by NGT Active H - no bubble Active L - bubble Logic Signal - Asserted - Unasserted - Bistate Mch logic cht (Latch) OE
Asserted level)
t mc logic V d chn Clear HIGH Khng tc dng Mc khng tch cc inactive level = High Mc khng thit lp (unasserted level) Low C tc dng xo Mc tch cc active level = Low Mc thit lp (asserted level)
Active Negative Going Transition Active Positive Going Transition
Clock Up Clock Down Data Mch logic iu khin (Control) Data Latch
Active High
Data
Active High Active Low Bistate
LOAD Clear
Read/Write Enable
Active Low
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Khi nim Chuyn i Mc tch cc

Dng nh l De Morgan A.B = A + B A+B= A.B
Output ative WHEN ALL inputs active
A Active High B A.B LOW is Active level
Output ative WHEN ANY inputs active
A Active LOW B
A + B = A.B HIGH is Active level
Alternated Logic Gates or De Morgan Logic Gates
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Chuyn i Mc tch cc cho cng logic

GATE INV Standard Logic Gates Alternated Logic Gates
AND
OR
NAND
NOR
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Chuyn i Mc tch cc cho mch logic

ngha : gip vic phn tch mch logic d dng hn.
A B Z C D Cha tng ng cc mc tch cc Kh nhn xt c quan h Z (A, B, C, D)
A Chuyn i mc tch cc B C D Tng ng cc mc tch cc A B C D Z Active L Z = 0 ch khi (A=0 hoc B =0) v (C =0 hoc D =0) Z Active Hi h Z = 1 ch khi (A =1 v B =1) hoc (C =1 v D =1)
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Bi tp chuyn i mc tch cc
Phn tch cc mch logic sau :
Floppy Driver Controller
A7 A6 A5 A4 A3 A2 A1 A0 74HC30
Memory Access Controller

RD
74HC32 74HC02 Drive
MEM
ROM1
Bit Drive = 1 s iu khin Motor a mm quay.

74HC02
ROM2
RAM
IN OUT
Bit MEM = 0 s cho php truy nhp b nh
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Khi nim mch tch hp s

(Digital Integrated Circuits)
Cc linh kin c th ch to trn cng 1 phin bn dn (CHIP)
Cc cng logic c th ch to trn cng mt CHIP Cc mch logic c th ch to trn cng CHIP c ng gi (package) thnh mch tch hp (Digital IC)
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Mc tch hp (Scale of Integration)

nh ngha : c tnh theo s cng logic (logic gates) c trn mt IC n
Mc tch hp C nh - SSI Small-Scale Integerated C trung bnh - MSI Medium-Scale Integerated 12 n 99 S cng di 12 Cc ng dng Cho cc thit k kiu "tch ngn" (off-the-shelf). Gm cc IC s cha cc khi cng c bn v cc FLIP-FLOP. Cho cc thit k kiu "tch ngn"(off-the-shelf. Gm cc IC a ch ho, thanh ghi, b so snh, b m, b chuyn m, b chn/dn knh d liu v cc loi RAM c nh. C th cha cc chc nng ca c mt h thng. Gm c cc b nh thi s (Digital clock), b tnh ton (Calculator), b nh (Memory) RAM ROM, PROM, EPROM, b nh Flash v cc b vi x l (Microprocessor ).
C ln - LSI Large-Scale Integerated C rt ln VLSI Very-Large-Scale Integerated C cc ln - ULSI Ultra-Large-Scale Integerated
100 n 9.999
10.000 n 99.999
trn 100.000
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Cc H IC s (Digital IC Families)
nh ngha : L s phn chia theo kt cu v cng ngh c p dng thc hin cc cng logic bn trong mch tch hp. (c bit l cch thc hin Transistor)
Digital IC Family RTL (Resistor Transistor Logic) DTL (Diode Transistor Logic) HTL (High Threshold Logic) Standard TTL (Transistor Transistor Logic) Schottky TTL NMOS (N-channel MOSFET) PMOS (P-channel MOSFET) CMOS - Complementary symmetry Metal Oxide Semiconductor BiMOS BJT & MOSFET ECL (Emitter Coupler Logic) c im Kt hp BJT v in tr. Dng dng iu khin. Mc tch hp nh. Tiu th nng lng ln. Dng iot thay cho in tr iu khin Transistor. Gim tn hao, tng mc tch hp. Khc h DTL vic dng thm cc it Zener. Nng ngng chuyn trng thi nn chng nhiu tt hn. Chm v tiu th nhiu nng lng. Dng Transistor nhiu cc Emitter u vo. u ra c 2 transistor mc ni tip. D ghp ni. Tc c ci thin. Tiu th nng lng ln. Dng Transistor hiu ng Shottky tng tc chuyn trng thi. Dng MOSFET knh N. Kt cu nh gn nn mc tch hp cao. Khng dng in tr. Tiu th t nng lng. Cp dng nh. Dng MOSFET knh P. c tnh km hn so vi NMOS. Kt cu gm NMOS v PMOS kt hp. Mc tch hp cao. Tiu th nng lng rt t. Tc chm. Kt hp BJT v MOSFET. Ch yu ci thin tc . Dng kt cu khuch i vi sai, khng lm vic ch bo ho. Tc cao. Mch phc tp. Cp ngun m 5,2V. 2 u ra lin hp. Ph hp vic ghp ni truyn s liu. Tiu th nng lng nhiu.
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Gii thiu cc h IC s
Trong mt h logic cho, cc cng logic c tng hp t mt loi linh kin tch cc duy nht. Vic chn la linh kin ny c xc nh bi cng ngh ch to vn gn lin vi h logic . Trong cng mt h logic, cc cng d dng lin kt vi nhau. Trong h logic TTL (Transistor-Transistor Logic), tt c cc phn t logic c lm t cc cu trc BJT kiu npn, cc it v cc in tr. Cc linh kin trong h TTL c iu khin lm vic trong ch ct v ch bo ho t c cc trng thi logic cao v thp. TTL l mt trong nhng cng ngh s u tin c pht trin v cng l mt s chn la truyn thng trong cc h thng m cng i hi tc tnh ton kh cao nhng vn tiu th nng lng khng phi l mi quan tm chnh. Phn ln cc cng logic TTL c sn nh cc linh kin dng cho thit k tch ngn c ng khi thnh cc mch t hp c LSI c nhiu chn. So snh vi cc h logic ly c s l cu trc MOSFET th cc linh kin TTL t nhy cm hn i vi tc ng vt l bt li t s phng tnh in (ESD) l hin tng c th xy ra trong khi ngi s dng cm cc linh kin. V nhng l do , h logic TTL s l l tng cho cc th nghim nh ("breadboarding") ca nhng cng vic thit k h thng s. Vic s dng cc transistor BJT hiu ng Schottky thay cho cc transistor BJT thng trong mch tch hp to ra cc dng khc ca TTL c tc cao hn, tiu th t nng lng hn TTL chun. C th gi cc loi ny l cc h con ca h IC loi TTL (subfamily of TTL). Trong h ECL (Emitter-Coupled Logic), cc phn t logic c lm t cc cu trc BJT v cc in tr c ni di dng topo khuch a vi sai. Khng ging nh h TTL, cc phn t tch cc trong cc linh kin h ECL khng c iu khin n cc gii hn bo ho ca chng. Cc bin nh tn hiu trong cc mch logic ECL thng l nh nn i hi t thi gian np v phng cho cc in dung khc nhau trong mch. Nh vy, cc h thng s c thc hin bi cc linh kin h ECL s c kh nng hot ng vi tc rt cao. Ci gi phi tr y l mc tiu th nng lng ln v phi gi cho cc kt cu BJT ca mt cng ECL c nh thin trong min tch cc. Mt nhc im na l vic kt hp gia ECL vi cc h logic khc s kh khn hn do c s khc v mc in th, i hi cn c cc mch ghp ni chung gian. H logic ECL c s dng trong vic thit k cho cc "siu my tnh" tc cc cao v cc mch x l s.
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Trong h logic NMOS, cc cng logic c lm hon ton t cc cu trc MOSFET knh n ch tng cng (enhancement-mode) v ch suy gim (depletion-mode). Cc in tr hon ton khng c dng trong cc mch logic NMOS. Bi v cc cu trc MOSFET knh n c th c ch to d dng v vi mt kch thc rt nh nn "mt ng gi" (packing density) ca cc transistor NMOS c th t c mc rt cao. Bi vy, h NMOS rt thch hp vi thit k b vi x l VLSI v cc mch nh, trong cc mch ny i hi mt s lng ln cc linh kin. Cc phn t logic NMOS cng c kh nng to ra cc mch vi tc tnh ton kh cao. ng tic l cc mch NMOS ch c kh nng cp dng ti nh. Kh nng s dng ca h NMOS chim u th trong nhiu ng dng ca mch vi x l VLSI (p) v mch nh truy nhp ngu nhin (RAM). Trong cc mch ny, ni m cc cng logic ch iu khin cc u vo ca cc cng MOSFET khc, th s hn ch dng ti ca NMOS khng phi l mt vn ng ch . Tri li, nhiu mch NMOS c VLSI c cha thm cc linh kin iu khin c bit phc v cho vic giao tip vi cc mch bn ngoi. Tuy nhin, kh nng iu khin ti thp ca cc mch NMOS khin cho chng khng c kh nng thch ng nh cc linh kin dng cho thit k tch ngn (off-the-shelf). V l do ny, cc cng logic NMOS khng c sn trong cc ng gi logic chun nh l cc cng h TTL v h ECL. Trong mt h tng t l h CMOS (b MOS - Complementary MOS), tt c cc phn t logic c cu to ch t cc MOSFET knh n v knh p ch tng cng. Ging nh cc cng NMOS, cc cng CMOS d dng ch to v n gin trong thit k. Thm vo , cc mch CMOS tiu th rt t nng lng. Cc mch CMOS l mt la chn hin nhin cho cc mch in chy pin nh cc ng h s, cc my tnh ton cm tay, cc my in thoi trong mng t ong (cellular) v cc my tnh xch tay. Tc ca cc mch CMOS hon ton c th cnh tranh vi cc h logic khc, v th CMOS tr thnh mt h logic s a dng bao gm c hai u im l tiu th nng lng thp v tc cao. H logic BiCMOS (Bipolar-CMOS) cng nhanh chng tr thnh mt h logic quan trng. Trong h logic BiCMOS, cc kt cu MOSFET v BJT c ch to trn cng mt mch t hp v c phi hp vi nhau trong cng mt cng logic. Cc cu trc MOSFET
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c s dng nh cc thit b u vo to ra cc tr khng u ln, v cc cu trc BJT c dng t c tc cao v kh nng iu khin ti ln. So vi cc mch logic c lm t cc kt cu BJT, cc mch thuc h CMOS, BiCMOS v NMOS nhycm hn i vi tc ng bt li t hin tng vt qu ng sut tnh in EOS (electrostatic overstress) v hin tng phng tnh in ESD (electrostatic discharge). Vic cm khng ng ch ca cc linh kin MOS s dn n vic in tch tnh in truyn t ngi hoc vt n cc ng dn u vo ca cc IC. Do cu to ca lp SiO2 trong kt cu MOS rt mng v c tc dng nh cht dung mi trong t in nn c th b nh thng bi s phng tnh in trn. Nh vy, i vi cc linh kin MOS cha ni vo mch i hi phi c cch bc gi c bit chng tnh in. Trnh cc IC MOS trong cc vt cha khng c tnh dn in. Phi bo qun cc IC MOS ny trong bt dn in hoc t trn cc khay dn in v quay chn xung. Cn thn trong cch cm chng khi kt ni. Khi hn, khng nn dng m hn xoay chiu, m nn dng m hn chy acqui (cn gi l m hn tnh in). Trn quan im nh phn th mi h logic khc nhau c cp trn s to ra cc cng c mt chc nng nht nh. Trn quan im in t th mi h s c nhng tnh cht v nhng c tnh khc nhau.
) Ch : Trong thit k kiu tch ngn (off-the-shelf ) ta thng chn la cc cng logic t cc vi mch s chun (IC a dng)
c ng gi, ch yu l cc IC thuc hai h logic TTL v CMOS. Hin ti c rt nhiu loi IC kiu ny v chng cung cp nhiu chc chc nng c bn cn thit cho cc h thng s. V k hiu th chng c phn chia lm hai nhm : Nhm cc IC u 74 gm c h TTL v CMOS v nhm 4000 ch cho h CMOS. (Nhm IC u 54 l IC s c dng trong qun s. Trong mi nhm li c nhng nhm nh hn c phn chia theo h logic, nh sn xut, mc tiu th nng lng, tc .
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K hiu trn IC
DM 74 LS 08 N M nh sn xut Nhm 74 (54) H IC H TTL
(khng c k t h IC th l TTL chun ) C HC
Ch nh loi Package Chc nng
H CMOS
= cng cc chc nng v c cch b tr chn nh 74 h TTL. = High-speed CMOS. in p ngun cung cp +2 n 6V.
ALS = Advanced Low-power Schottky TTL logic. AS F H L LS S

= Advanced Schottky TTL logic. = FACT Fairchild Advanced Schottky TTL logic. = High-speed TTL logic. = Low-power TTL logic. = Low-power Schottky TTL logic. = Schottky TTL logic.
Cc IC loi FACT- Fairchild Advanced CMOS Technology tng ng v chc nng v cch b tr chn so vi h 7400 loi TTL. Gm c : 74AC,74ACQ,74ACT,74ACTQ, 74FCT, 74FCTA, 74HCT "Q" - l loi c mch kh nhiu, "T"- lm vic mc in p logic TTL.
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kt cu h TTL chun
Totem pole
E1
E2
P-CHIP
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Hot ng ca cng NAND h TTL chun
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Ko dng v cp dng ti u ra cng NAND h TTL
Current-sinking IIL
Current-providing IIH
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kt cu LOW-POWER Schottky TTL

Ko di lp kim loi cc base n tn mim collector (nhm hoc bch kim) E B C
VCC = 5V R1 20k NAND H LS TTL R2 8k R3 120k Q5 Q4 DX R4 4k Z = A.B Q3 R5 1.5k R6 3k Q6 Mch rt dng tch cc
n p n p nh dng it Schottky
DA A D1 Q2
DY DB B D2 Ni it Schottky Schottky-clamped BJT
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TTL c u ra 3 trng thi (Tristates or High-Z)

VCC
+5V
R1 Cng NAND A B Q1
R2
R4 Q3 Q2 D1 n BUS s liu Z Q4
Q4 Q3 Z =High-Z
R3 VCC R5 R6 Q7 CS Q5 Ghim ba trng thi Q6
K hiu
A Z = A.B B CE Chip Enable
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OPen Collector TTL

VCC R2 VCC
R1
External Pull-up Resister

A B Cng NAND Open Collector Output R3 Z Q3 Q1 Q2
OUTPUT
K hiu
A Z = A.B B
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H NMOS
+5V Q1 NMOS Z Q2 NMOS Q3 NMOS
+5V Q1 NMOS Z Q2 NMOS Q3 NMOS
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H CMOS
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H ECL - Emitter Coupler Logic
Mch c cu trc phc tp. Cng sut tiu th ln. Tc rt nhanh. Mch s dng cao th m (- 5,2V), mc in p logic khc bit vi cc mch logic khc nn kh ghp ni ( phi dng mch trung gian ). C hai u ra lin hp rt thun tin. Khi truyn i xa, vic kt hp hai u ra ny s trnh c s pht x gy nhiu ca cc mch khc. Tng tr ra nh, tng tr vo ln.
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Cc c tnh ca mch tch hp s
Current & Voltages Fanout Propagation Delay Noise Margin Power Dissipation Speed Power Product
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c tnh in p v d tr nhiu
(Voltages & Noise Margin)

VIH(min) VIL(max) VOH(min) VOL(max)
The minimum voltage level at the input to be recognised as H. The maximum voltage level at the input to be recognised as L. The minimum voltage at the output when in state H. The maximum voltage at the output when in state L.
iu kin
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c tnh dng in v kh nng mc ti

(Current & Fanout)

IIH The current flowing into the input when a specified H voltage is applied. IIL The current flowing into the input when a specified L voltage is applied. IOH The current flowing out of the output when in state H. IOL The current flowing out of the output when in state L.
V d : Standard TTL FANOUT = 10
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So snh c tnh dng in ca h TTL v H CMOS

H IC s Standard TTL Low Power Schottky (LS)
TTL
Dng ra IOH IOL IOH IOL IOH IOL IOH IOL IOH IOL IOH IOL IOH IOL IOH IOL = 400 = 16 mA = 400 = 8 mA = 400 = 8 mA = 1 mA = 20 mA = 400 = 400 = 4 mA = 4 mA = 24 mA = 24 mA = 15 mA = 64 mA
Dng vo IIH IIL IIH IIL IIH IIL IIH IIL Iin = 40 = 1.6 mA = 20 = 400 = 20 = 100 = 20 = 0.6 mA = 1
Advanced Low Power Schottky (ALS) FAST Fairchild Advanced Schottky TTL (F) 4000 Series 74HC00 Series
CMOS
Iin = 1 Iin = 1 Iin = 1
FAST Fairchild Advanced CMOS Technology Series (AC/ACT/ACQ/ACTQ) FAST Fairchild Advanced CMOS Technology Series (FCT/FCTA)
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c tnh lan truyn tr

(Propagation Delays)
VIN
VOUT
VIN V(1) 50% V(0) VOUT V(1) 50% V(0) t t
tPLH Time taken to go from L to H. tPHL Time taken to go from H to L. The average propagation delay is
tPHL
tPLH
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So snh c tnh lan truyn tr ca TTL v CMOS
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c tnh tiu tn nng lng

(Power Dissipation)
VOUT High Low iS t
ICCH The current when all gate outputs in the High. ICCL The current when all gate outputs in the Low. The average current drawn is
t
P Png t Ptnh
Therefore the average power consumed is
Tch s Tc -Nng lng (sPeed-Power Product)
DP = tD pD (watt-second) ---> picojoules (pJ)

trong
tD = t PHL + t PLH 2
pD = (png + pTnh) PD (ave)
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Biu ch s quan h gia tc & Nng lng cc h IC s
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Ni ghp IC s TTL, CMOS vi LED hoc n hin th
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Ni ghp gia TTL v CMOS
Nh nghin cu v mc in p logic ca cc h IC s phn trn th s khc nhau v mc in p logic ca CMOS v TTL khin vic ghp ni gia chng khng n gin nh ghp ni trong cng mt h. Xem hnh di y ta thy tuy dng u ra TTL tha iu khin u vo CMOS nhng in p ra li khng tng xng. Khong in p ra t 2,4V n 3,5V m u ra TTL c th a ra li nm trong khong khng xc nh mc logic ca CMOS. iu ny hon ton c th gy ra cc vn sai lch cho h thng. Gii quyt vn ny ta phi dng n mt in tr lm nhim v ko mc in p logic ra ca TTL ln ng vo khong xc nh u vo CMOS. in tr ny gi l in tr nng ( pull-up resistor ). Theo hnh v th in tr nng c dng l 1k , khi TTL ra mc cao in tr ny s nng mc in p vo CMOS ln gn 5V.
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Mt s ch khc
- H LS-TTL khi iu khin u vo CMOS phi dng in tr nng. Nhng bt c IC CMOS no cng c th iu khin trc tip LS - TTL v ALS - TTL.
- Cc nh sn xut to ra cc b m c bit v cc chip giao tip gip cho vic ghp ni tr nn n gin hn.( VD: IC s CMOS noninverting buffer 4050 cho php iu khin trc tip 2 u vo chun TTL). - Cc IC s h 74HCT c ch to c bit cho php lm cu ni gia TTL ( v c NMOS - c c tnh ra gn ging LS-TTL ) vi CMOS. ( VD :74HCT34 noninverting ).
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Mt s ch khc (tip)
- H FACT c fan-out ln nn c th iu khin trc tip cc u vo h TTL, CMOS, NMOS v c PMOS. - Dng TTL iu khin u vo IC cc loi HC, AC, ACQ th cn in tr nng. Nhng TTL li c th iu khin trc tip bt c loi IC CMOS no c k hiu "T" i km. ( xem cc hnh v di y ).
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Mt s ch khc (tip)
- Di y l cc cch ghp trong trng hp TTL v CMOS khc mc ngun cung cp:
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ghp ni TTL v CMOS vi Switchs, RELAY...
Khi dng n cc switch ti u vo IC s ta phi dng thm in tr nng ( hoc in tr h ) c tc dng khi switch trng thi m, u vo IC s vn c t mt trong hai mc logic thch hp. Gi tr cc in tr ny c tnh ton nh c tuyn dng ra / vo ca cc h IC s . C nhng h thng s cn iu khin cc thit b cng sut ln th thng phi iu khin qua mt thit b trung gian l RELAY. ( nh cc b p AVL, b lu in UPS...).
Ch : - Relay c th lm vic in p cao hn ta vn dng cch ghp ni trn ch cn chn transistor chu c dng, in p tng ng. - it dng y gi l it chn trnh cc in p nhn gy ra trong h thng.
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Mt s yu cu khi dng cc IC s TTL v CMOS
Cc yu cu khi s dng vi mch loi TTL:

1. in p cung cp cho vi mch VCC khng c vt qu 5,25V. 2. Cc u tn hiu vo khng c vt qu VCC v khng nn thp hn t (GND). 3. Cc u vo khng s dng ca mch tch hp nn t n mc ngm nh. Nu l mc ''H" hy ni vo VCC , nu mc thp hy ni xung GND. 4. Nn t cc u ra khng s dng ca cc cng mc cao tit kim dng. 5. i vi cc nhm t 5 n 10 khi cng ( gate packages ), 2 n 5 b m v thanh ghi hoc i vi mch mt xung ( one shot ) phi dng t nht mt t kh ghp c tr s t 0,01F - 0,1 F. T ny s lm nhim v trung ho cc xung nh nhn ca ngun cung cp khi cc u ra ca vi mch TTL/LS thay i trng thi. Ta ni cc t kh ghp t VCC n GND v t cng gn vi vi mch cng tt. Lu phi kim tra cc t ny khi thc hin mch trnh ngn mch ngun nui. 6. Trnh cc dy dn di trong mch. 7. Nu ngun cung cp khng nm trn cng mt bo mch th ti v tr a ngun nui vo nn t thm mt t 1F n 10F. 8. Nu c u ra no cho tn hiu iu khin nhiu u vo logic khc phi ch n ch s fan-out ca u ra . Dng cc IC loi c fan-out ln hoc c th tn dng cc cng khng dng ni ghp li dng chui chia tn hiu iu khin cho nhiu u ra cc cng khc. 9. Kim tra vic truyn tr.
Cc yu cu khi s dng vi mch loi CMOS:

1. 2. 3. 4. in p u vo khng nn vt qu VDD ( tr 4049 v 4050 ). Tt c cc u vo khng s dng cn ni vi VDD hoc GND. Khng bao gi ni mt tn hiu u vo vi mt mch dng vi mch CMOS khi ngt ngun cung cp. Do cu to ca lp SiO2 trong kt cu MOS rt mng v c tc dng nh cht dung mi trong t in nn c th b nh thng bi s phng tnh in. V vy trnh cc IC ny trong cc vt cha khng c tnh dn in.Phi bo qun cc IC MOS ny trong bt dn in hoc t trn cc khay dn in quay chn xung. Khng dng m hn xoay chiu, dng m hn cqui.

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Logic Gates - Logic Circuits - Digital Integrated Circuits and Their SPECIFICATIONS

Cng logic - Mch logic - Mch tch hp s

II. Mch logic

III. Chuyn i mc tch cc

IV. Mch tch hp s

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Mc logic (LOgic Level)

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

cng logic (Logic Gate)

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

VI DU cng logic INverter VA IC 74LS04 (Hex inverters)

Inverter gate in 7400

Inverter gate in 74LS00

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

VI DU cng logic NAND VA IC 7400 (Quadruple 2-input NAND Gate)

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Mch Logic (Logic Circuit)

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Phn loi Mch Logic

otomat khng nh Truth tables x ---F---> Z

otomat c nh State Tables (X,S) --- F ---> Z (X,S) --- G ---> S

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Bi ton phn tch v tng hp Mch Logic

Cc Quan h cn c trn cc chc nng

Bi ton Tng hp ( synthesis)

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

khi nim Mc tch cc

Active Negative Going Transition Active Positive Going Transition

Active High Active Low Bistate

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Khi nim Chuyn i Mc tch cc

Output ative WHEN ALL inputs active

A Active High B A.B LOW is Active level

Output ative WHEN ANY inputs active

A + B = A.B HIGH is Active level

Alternated Logic Gates or De Morgan Logic Gates

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Chuyn i Mc tch cc cho cng logic

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Chuyn i Mc tch cc cho mch logic

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni

Memory Access Controller

74HC32 74HC02 Drive

Bit Drive = 1 s iu khin Motor a mm quay.

Bit MEM = 0 s cho php truy nhp b nh

Ging vin : TS. L Dng

Vin in t - Vin thng - H Bch Khoa H Ni