3g Channel Codes

3GPP:fdd
3rd Generation Partnership Project (3GPP) Standard Compliant
3G FDD Library
Toolbox for MATLAB
&
Blockset for
Version 5.0
This page is intentionally blank
Table of Contents Table of Contents List of Figures Scope of this Document 3GPP FDD Library Version Number Distribution and Support 3GPP Standard Documentation 3GPP Web Site Key FDD Standard Document Numbers Comments and Support Requests This Document Licence 1 Introduction 1.1 3GPP Standard Compliance 1.2 FDD Library Version 1.3 Library Application 1.4 Installing the 3GPP:fdd Library 1.5 FDD Library Directory Structure Why FDD? - The 3GPP Proposal for IMT2000 2.1 Universal Mobile Telephone System (UMTS) 2.2 IMT-2000 Standardisation 2.3 Global Standardisation - Partnership Projects - 3GPP 2.4 Spectrum Allocation FDD Block Overview 3.1 Systems 3.2 PHY Channels 3.3 PHY Channel Components
3.3.1 Transport Channels 3.3.2 Physical Channels 3.3.3 General
iii vii ix ix ix ix ix x x xi 1 1 1 1 2 2 3 3 4 5 5 6 6 6 6
6 6 7
3.4 3.5 3.6 4
Propagation Channel Measurements & Synchronisation HSUPA
7 7 7 8 8 11 14
Using the Library 4.1 Uplink Transmit and Receive. 4.2 Downlink Transmit and Receive. 4.3 Block Processing
iii
4.3.1 The Delay Offset feature. 4.3.2 The No Leading Output feature
14 15
The 3GPP:fdd Library Blocks 5.1 Spectrum Spreading and Channelisation Waveform Generators
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 Orthogonal Variable Spreading Function (OVSF) Code Generator Uplink Short Scrambling Code Generator Uplink Long Scrambling Code Generator Downlink Long Scrambling Code Generator Spreader/Despreader OVSF Fast Hadamard Transform Pilot Symbol Generator Uplink Random Access Channel Preamble Generator Synchronisation Code Generator Physical Channel Generator / Multiplexer Downlink Dedicated Channel Generator
16 16
17 20 24 28 35 45
5.2
Code and Channel Generators

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5
48
50 55 58 62 68
5.3
Channel Coding
5.3.1 Cyclic Redundancy Coding (CRC) - Encoder/Decoder 5.3.2 Convolutional Encoder 5.3.3 Convolutional Decoder (Viterbi Algorithm) 5.3.4 Turbo Encoder 5.3.5 Turbo Decoder 5.3.6 Rate Matcher 5.3.7 Interleaver 5.3.8 De-Interleaver (DeIntLeave) 5.3.9 Transport Channel Coder 5.3.10 Transport Channel Multiplexer
77
78 83 86 90 93 96 99 102 104 110
5.4
Channel Generators
5.4.1 Uplink Generator 5.4.2 Downlink Generator 5.4.3 HSDPA Transmission Generator
114
115 122 134
5.5
Channel Models
5.5.1 5.5.2 5.5.3 5.5.4 Complex Gain Rayleigh Fading Channel Moving Channel Birth-Death Channel
140
141 143 147 150
5.6
Synchronisation
5.6.1 Synchronisation Acquisition 5.6.2 Clock Generator
153
154 158
5.7
Physical Measurements
5.7.1 Adjacent Channel Leakage 5.7.2 Bit Error Rate
163
164 167
5.8
Multiplexers, Demultiplexers and Integrators

5.8.1 5.8.2 5.8.3 5.8.4 I/Q Splitter I/Q Combiner 1 to 2 Demultiplexer Slot Field Demultiplexer
169
170 172 173 176
5.9
Averaging Blocks
5.9.1 Integrate and Dump 5.9.2 Frame Averaging
181
182 185
iv
Block-driven 3GPP:fdd Library Blocks 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Frame Scrambler Frame Spreader E-AGCH Coder E-HICH Coder E-RGCH Coder E-DPCCH Coder E-DCH Coder
187 188 189 190 192 193 195 196 197 199 201 202 203 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 226 230 231 232 233 234 235 236 237 239 240 242 244 247
Matlab Toolbox Functions 7.1 FddCRC 7.2 FddHSBitScrambling 7.3 FddTrCHCoding 7.4 FddTurboDecoding 7.5 FddConvolutionalDecoding 7.6 FddHSHarq 7.7 FddHSHarqRecovery 7.8 FddEHarq 7.9 FddEHarqRecovery 7.10 FddPhyChSegmentation 7.11 FddPhyChInterleaving 7.12 FddPhyChDeinterleaving 7.13 FddConstellationRearranging 7.14 FddConstellationDearranging 7.15 FddDLModulation 7.16 FddDLDemodulation 7.17 FddULModulation 7.18 FddULDemodulation 7.19 FddSpreading 7.20 FddDespreading 7.21 FddScrambing 7.22 FddDescrambling 7.23 FddHSSCCHCoding 7.24 FddHSSCCHCodingType3 7.25 FddHSSCCH 7.26 FddHSHARQACKEncoding 7.27 FddHSCQIEncoding 7.28 FddEDCHCoding 7.29 FddEDPCCHCoding 7.30 FddERGCHCoding 7.31 FddEHICHCoding 7.32 FddEAGCHCoding 7.33 FddHSDSCH 7.34 FddHSDSCHDecode 7.35 FddHSPDSCH 7.36 FddHSPDSCHDecode 7.37 FddFadingChan
Appendix A:3GPP Definitions
Appendix B:3GPP Abbreviations
251
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List of Figures 1 Introduction Figure 1.3.1: Simulation groupings for the library. Figure 1.5.1: FDD Library directory structure. 2 Why FDD? - The 3GPP Proposal for IMT2000 3 FDD Block Overview 4 Using the Library Figure 4.1.1: Uplink transmit - critical block paths in transport and physical channels. Figure 4.1.2: Uplink receive: critical block paths in transport and physical channels. Figure 4.2.1: Downlink transmit: critical block paths in transport and physical channels. Figure 4.2.2: Downlink receive: critical block paths in transport and physical channels. Figure 4.3.1: Interleaving with delay 5 The 3GPP:fdd Library Blocks Figure 5.1.1: Orthogonal code generation structure Figure 5.1.2: The modulo-4 and two modulo-2 sequence generators. Figure 5.1.3: Uplink short scrambling code generator. Figure 5.1.4: Uplink long scrambling code generator. Figure 5.1.5: Downlink long scrambling code generator. Figure 5.1.6: Output of spreader block in spreading mode Figure 5.1.7: Effect of the timing offset parameter in the operation of the spreader block Figure 5.1.8: Effect of the delay offset parameter in the operation of the spreader block Figure 5.1.9: Downlink spreading structure. Figure 5.1.10: DPCH uplink spreading structure Figure 5.1.11: Code tree for fast Hadamard transform. Figure 5.2.1: Effect of clock on data option. Figure 5.2.2: DPCCH slot structure Figure 5.2.3: DL DPCH slot format Figure 5.2.4: CPICH slot format Figure 5.2.5: Symbol sequence used in CPICH Figure 5.2.6: S-CCPCH slot format Figure 5.2.7: Random access transmission structure Figure 5.2.8: RACH generation. Figure 5.2.9: Position of primary SCH in slot Figure 5.2.10: Structure of SCH frame Figure 5.2.11: Dedicated Physical Channel Mapping. Figure 5.2.12: DPDCH and DPCCH on the uplink DPCH. Figure 5.2.13: DPDCH and DPCCH on the downlink DPCH. Figure 5.2.14: Uplink PRACH control channel. Figure 5.2.15: Downlink S-CCPCH. Figure 5.3.1: Output block structure of CRC encoder. Figure 5.3.2: CRC parity generator. Figure 5.3.3: CRC syndrome generator. Figure 5.3.4: The steps performed by the convolutional encoders block. Figure 5.3.5: The structure of the convolutional coder function generators. Figure 5.3.6: Turbo Coder. Figure 5.3.7: Turbo Decoder. Figure 5.3.8: Transport Channel Coder Functions (Downlink) Figure 5.3.9: Multiplexing of logical channels into a transport channel. Figure 5.3.10: Multiplexing of 3 transport channels into a radio frame. Figure 5.5.1: Multipath fading channel structure. Figure 5.5.2: Moving channel path positions. Figure 5.5.3: Path birth and death in birth-death channel. vii 1 1 2 3 6 8 9 10 12 13 14 16 19 22 23 26 34 39 40 41 42 42 45 52 52 53 53 53 54 56 57 59 59 65 65 65 66 66 79 81 81 84 85 92 94 108 111 112 144 148 151
Figure 5.6.1: Chip, symbol and slot clock signals. Figure 5.6.2: Relation between input/internal clock and chip clock Figure 5.6.3: Use of advance input and its effect on the chip clock. Figure 5.6.4: Use of retard input and its effect on the chip clock. Figure 5.7.1: Positioning of adjacent channels. Figure 5.8.1: Operation of IQ splitting. Figure 5.8.2: Demultiplexing three bit fields using two Demux12 block Figure 5.8.3: Demultiplexing of a DTCH using the Demux12 block Figure 5.8.4: Structure of downlink DPCH slot at 30 kbps Figure 5.8.5: Demultiplexing the DPCH slot into the different blocks outputs Figure 5.8.6: Parameters used to demultiplex DLDPCH slots at 30 kbps Figure 5.8.7: Assigning fields to outputs Figure 5.8.8: Assigning slot fields to outputs Figure 5.9.1: Integrate and dump operation over six samples (N = 6) Figure 5.9.2: General form for integrate and dump. Figure 5.9.3: Operation of the Frame Averaging block 6 Block-driven 3GPP:fdd Library Blocks 7 Matlab Toolbox Functions
160 160 161 161 165 171 174 175 177 178 179 179 180 183 184 186 187 197
viii
Scope of this Document
This document is the users manual for the Steepest Ascent 3rd Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) simulation library - 3GPP:fdd. The aim of the document is to define, describe and demonstrate by example the proper use of the various blocks within the 3GPP:fdd library.
ii
3GPP FDD Library Version Number
This manual is the FDD Library Version 5.0. You can establish the library version number of your installed software by right-mouse-clicking on the file: <install path>\FDD\fdd.dll To use this library you require Windows 2000 (or later) and Matlab/Simulink Version 7.3 (R2006b) or later for Windows.
iii
Distribution and Support
For pre and post sales support please contact: Steepest Ascent Ltd Ladywell 94 Duke Street Glasgow G4 0UW United Kingdom
Tel: Fax: Email: http: +44 (0) 141 552 8855 +44 (0) 141 552 8855 support@steepestascent.com www.steepestascent.com
iv
3GPP Standard Documentation
The functionality of this software library is defined by the standard release documents from the 3rd Generation Partnership Project (3GPP) Technical Specification Group (TSG) RAN WG4. The document numbers are from the TS25 series technical specification.
3GPP Web Site
The standard documents used for the development and specification of this simulation library are available from http://www.3gpp.org
ix
vi
Key FDD Standard Document Numbers
The reference documents used for the verification of the 3GPP:fdd library are:
Document Number TS25.101 Title UE Radio Transmission and Reception (FDD) Short Descriptor Establishes the minimum RF characteristics of the FDD mode of UTRA for the user equipment.
TS25.104
Establishes the base station miniUTRA (BS) FDD; Radio Transmismum RF characteristics of the FDD sion and Reception mode of UTRA. RF Parameters in Support of Radio Resource Management Transmission Establishes the base station minimum RF characteristics of the FDD mode of UTRA.
TS25.133
TS 25.201
Presents a general description of the Physical Layer - General Descripphysical layer of the UTRA radio ton interface. Describes the characterisation of the Physical channels and mapping of layer 1 transport channels and phystransport channels onto physical ical channels in the FDD mode of channels (FDD) UTRA. Multiplexing and channel coding (FDD) Spreading and Modulation (FDD) Describes the characteristics of the layer 1 multiplexing and channel coding in the FDD more of UTRA Describes the spreading a modulation for UTRA physical layer FDD mode. Specifies and establishes the characteristics of the physical layer procedures in the FDD mode of UTRA. Services provided by the physical layer of UTRA to the upper layers.
TS 25.211
TS 25.212
TS 25.213
TS 25.214 TS 25.302
Physical layer procedures Services provided by the physical layer.
The FDD Library Version 5.0 is compliant with Release 6 3GPP specifications including HSDPA and HSUPA, which indicates it is compliant with V6 series of the physical layer description documents TS25.211, TS25.212, TS25.213 and TS25.214.
vii
Comments and Support Requests
Please contact Steepest Ascent (support@steepestascent.com) or your local distributor with comments and for support information.
viii
This Document Licence
As the owner of the FDD library you have ownership of both a printed and an Acrobat PDF electronic version of this document. Duplication and/or distribution of either paper or electronic format is prohibited. The FDD Library is copyright Steepest Ascent Ltd 2005-2011. All asserted IPR Rights are reserved and retained by the owners and material developers.
xi
xii
1 Introduction
1 Introduction
This manual specifies the components of the 3GPP:fdd (3rd Generation Partnership Project - Frequency Division Duplex) library. The library provides a means of simulation of the physical layer between the basestation (BS) and mobile station (MS) (or user equipment (UE) terminals). Hence the FDD library contains a number of defined source and input/output blocks which can be used as building blocks to produce a complete standard compliant FDD system simulation as both a baseband simulation or an RF modulated simulation. 1.1 3GPP Standard Compliance
The FDD software library described in this document is standard compliant to the 3rd Generation Partnership Project (3GPP) release documents listed in Section iv on page xi of this document. The latest release of the standard documents are available at:
http://www.3gpp.org
1.2
FDD Library Version
For the latest revision of this library please check the Steepest Ascent website:
http://www.steepestascent.com/downloads
1.3
Library Application
The library is likely to be used in a number of applications within Universal Mobile Terminal System (UMTS) Terrestrial Radio Access (UTRA) design. Typically the uplink and downlink physical layer implementations (summarised in Figure 1.3.1) for the transmit and receive of UTRA can be simulated and analysed with the 3GPP:fdd library.
Universal Mobile Telephone System (UMTS) Terrestrial Radio Access with Frequency Division Duplex
Uplink
Downlink
Transmit
Receive
Transmit
Receive
Figure 1.3.1: Simulation groupings for the library.
1 Introduction
1.4
Installing the 3GPP:fdd Library
To install the FDD library, (assuming you have a valid licence for the simulator), ensure that the simulator is NOT running, and execute the installer from:
FDDLib_installer_vX.X.X.exe
This is the file which you will have downloaded from the website, or that was delivered on the FDD CD. 1.5 FDD Library Directory Structure
The directory structure of the installed FDD library is shown in Figure 1.5.1. The directory docs contains Adobe Acrobat portable document format (pdf) version of this manual. The latest Adobe Acrobat Reader can be downloaded from http://www.adobe.com. This document you are reading or viewing now is the file fdd.pdf. The FDDLib directory contain all necessary files to ensure the FDD library will run within the simulation environment. 3G simulation example files are located in the directory Examples. These simulations illustrate correct and typical use of the blocks and also include complete and advanced simulation designs for base station (BS) and mobile station (MS) physical layer implementations.
<installpath>
FDDLib
docs General Examples Compressed Mode Downlink

channel coding procedures spreading
HSDPA Uplink
Figure 1.5.1: FDD Library directory structure.
2 Why FDD? - The 3GPP Proposal for IMT2000

For the third generation (3G) mobile radio systems, the consumer market is expected to show an increasing demand for services ranging from low data rate voice communication (as provided by 2G standards such as GSM) to high data rates to support multimedia applications with integrated audio and video communications. These emerging demands lead to the technical requirements for IMT2000 - International Mobile Telephones in the Year 2000, which are now being standardised worldwide. Both dedicated circuit and packet switched services will be available and they will operated in environments with the aim of allowing data communication, anyplace, anytime, anywhere. Due to spectrum availability different parts of the world may be using different frequency bands and therefore an absolute fundamental standard is unlikely to be produced. However, in the different regions of the world (Europe, USA, Korea, Japan) very similar proposals have been put forward, and most recently the 3GPP (3rd Generation Partnership Projects) have had the objective of converging the various detailed standards. The evolution from 2G to 3G is being very carefully planned, as far as possible the 2G investment will be deployed and retained where appropriate. 2.1 Universal Mobile Telephone System (UMTS)
UMTS is the name of the European version of IMT-2000. Currently the UMTS group expect that in the year 2000 there will be more than 400 million 2G subscribers, and by 2010, some 1800 million. The 2G standards use digital data transmission and in Europe the standard is GSM, Global System for Mobile communications (in the USA it is IS-136 and IS-95, and PDC (personal digital cellular) and Personal Handyphone System (PHS) technology in Japan). The first generation (1G) mobile technology was based on analogue signalling and is now beginning to be phased out. 2G traffic and numbers of users are still on the increase, however data rates are limited - a single channel data rate with a GSM telephone (mobile station) is 9.6kbits/s. UMTS will bring a number of new services by virtue of its high data rates: Internet access, email, multimedia document transfer; Mobile video teleconferencing; Audio, video narrowcasting (download videos, computer games, newspapers). The data rates from UMTS are planned as high as 2Mbits/sec (some 200 xs GSM capability, and almost 40 xs faster than a 56k modem). More precisely, due to various environments that mobile stations will be used in, three upper limit data rates will emerge:
144kbits/sec: For vehicular (high speed) mobile stations environments; 384 kbits/sec: For outdoor and slow roaming environments; 2.048Mbits/sec: For indoor and wireless area network (WAN) environments (picocells). It is planned that 3G services will operate in all environments such as downtown urban areas, hilly and mountainous areas, and in indoor building environments. Therefore, with high data rates, global operating environments 3G will see an even wider application and exploitation than the current 2G. 2.2 IMT-2000 Standardisation
The standardisation for IMT-2000 has been carried out primarily in Europe, China, Japan, Korea and America: European Telecommunications Standard Institute (ETSI) - Special Mobile Group (SMG); Europe; Research Institute of Telecommunications Transmission (RITT), China; Association of Radio Industry and Business (ARIB), Japan Telecommunication Technology Committee (TTC), Japan; Telecommunications Technology Association (TTA), Korea; Telecommunication Industry Association (TIA), USA T1P1, USA. The International Telecommunication Union Radio Communication Standardisation Sector (ITU-R) called for proposals for radio transmission technology by June 1998 and for evaluation in late 1998. ETSI-SMG have been considering their input since 1996, and proposed wideband CDMA (WCDMA) in both paired bands (called FDD) and a shared band (called TDD) in January 1998. A key consideration was of course the economic feasibility and the compatibility with existing GSM systems, and emerging GSM-Edge. ETSI SMG have therefore submitted this proposal of UMTS Terrestrial Radio Access (UTRA) concept to the ITU-R for inclusion in IMT-2000. The Japanese ARIB standard is closed related to the European WCDMA, and was submitted to the ITU-R and subsequently frozen in mid-1999 - Japan aims to deploy commercial WCDMA services in mid-2001. The Chinese RITT has proposed a time-division (TD) CDMA technique for TDD services and wireless local loop applications. The TTA in Korea has two proposals, one very close to the Japanese ARIB WCDMA and one similar to the American TIA cdma2000 proposal. In the USA there are a number of proposals. In particular the TIA support the evolution and extension of the existing IS-95 standard (a 2G CDMA implementation) into
what is denoted cdma2000. TIA also have proposed a WCDMA standard called WIMS and UWC-136, which is an evolution of the 2G IS-136 DAMPs standard. The T1P1 support WCDMA-NA, which corresponds to UTRA FDD from ETSI. 2.3 Global Standardisation - Partnership Projects - 3GPP
If the various regional standards can be harmonised then a partial/quasi-global standard would be in place. This would of course lead to economical and convenience advantages for customers, equipment manufacturers, and network operators. Therefore two projects have been established: The Third Generation Partnership Project (3GPP): To harmonise and standardise in detail the similar proposals from ETSI, ARIB, TTC, TTA, T1P1. 3GPP2: To harmonise the cdma2000 proposals from TIA and TTA. In addition, major international operators have invoked a process of cooperation between 3GPP and 3GPP2 with the aim of a globally harmonised concept. 2.4 Spectrum Allocation
Following the 1992 World Administrative Radio Conference (WARC) the spectrum for 3G systems was identified. At present, all regions have NOT adhered to the this suggested allocation of bandwidth, and therefore no absolutely common spectrum band is available for 3G mobile radio.
3 FDD Block Overview

3GPP:fdd provides powerful, flexible and easy to use blocks to implement the latest release of the 3GPP standard for FDD. The blocks can be integrated with any standard blocks from the simulator, such as modulators, adaptive equalisers, and so on. The blocks in the library provide the functionality outlined below. 3.1 3.2 3.3 3.3.1 3.3.2
CRC
Systems
UL
DPCH GEN
DL
DPCH GEN
HSDPA
Uplink Generator Downlink Generator HSDPA Transmission Generator
PHY Channels
PHY CH CH
CODEC
Dedicated Physical Control Channel (DPCCH) Generator Transport Channel Coder Downlink Dedicated Channel Generator
PHY Channel Components Transport Channels Cyclic Redundancy Coding (CRC) - Encoder/Decoder Convolutional Encoder Convolutional Decoder (Viterbi Algorithm) Turbo Encoder Turbo Decoder Rate Matcher Interleaver De-Interleaver (DeIntLeave) Transport Channel Multiplexer Physical Channels Physical Channel Slot Field Demultiplexer Clock Generator Orthogonal Variable Spreading Function (OVSF) Code Generator Uplink Short Scrambling Code Generator Uplink Long Scrambling Code Generator
RM
OVSF
UL
SSCC
UL
LSCC
DL
LSCC
SPDR
PILOT
UL
RACH
DL
SCH
OVSF FHT
Downlink Long Scrambling Code Generator Spreader/Despreader Pilot Symbol Generator Random Access Channel Preamble Generator Downlink Synchronisation Code Generator Orthogonal Variable Spreading Factor (OVSF) Transform Frame Scrambler Frame Spreader General I/Q Splitter I/Q Combiner 1 to 2 Demultiplexer Integrate and Dump
3.3.3 3.4 3.5 3.6
Propagation Channel
MPTH
MOV
BD
Complex Gain Rayleigh Fading Channel Moving Channel Birth-Death Channel
Measurements & Synchronisation

ACLR
BER
DL Sync
Adjacent Channel Leakage Power Bit Error Rate Counter Frame Averaging Sychronisation Acquisition
HSUPA E-AGCH Coder E-RGCH Coder E-HICH Coder E-DPCCH Coder E-DCH Coder
4 Using the Library
4 Using the Library

4.1 Uplink Transmit and Receive.
Figure 4.1.1 shows the generic functionality of the blocks to produce an uplink transmitter simulation, and in Figure 4.1.2 the uplink receiver is shown. Note that these figures only indicate the critical block path and do not illustrate, for example multiuser or noisy simulations. It should also be noted that there is more than one way to produce the same desired output. Therefore in cases where a designer wishes to specify each component, discrete single function blocks are provided. If a standard compliant full uplink is required, then a single fully parameterised block is available.
4 Using the Library
3GPP FDD - Uplink Transmit

Information Bits
Cyclic Redundancy Coding
CRC
CRCGen Convolutional Coding Turbo Coding ConvEnc
or TurboEnc Transport Channel Codec TrChCdr

CODEC
1st Interleaving IntLeave
or
CH
Rate Matching
RM
RateM
Transport Channel Mux Physical Control Chan Gen. IntLeave TChMux
2nd Interleaving IntLeave

UL
Control Data
PHY CH
DPCCHGen In-Phase Data
DPCH GEN
UpLink
Quadrature data
OVSF
Spreader
SPDR
OVSF
OVSF Real and Imaginary
or
Imag Cplx Mpy
Real Short Code Gen. Long Code Gen. ULSCGen ULLCGen

SSCC
UL
SPRDR
or
UL
LSCC
Complex data path
Pulse Shaping RF Modulation
Cos Sin
Complex Gain, Channel Models
MPTH
or
MOV
or
BD
or Cplx Gain
Fading
Moving
Birth/Death
RF Output
Complex Data Output
RF Output
Figure 4.1.1: Uplink transmit - critical block paths in transport and physical channels.
4 Using the Library
10
3GPP FDD - Uplink Receive

RF Input Complex Data Input
Cos Sin
Pulse Shaping RF Demodulation
Complex Symbols
UL UL Short Code Gen. SSCC LSCC or Long Code Gen. ULLCGen ULSCGen
or
Clock Generator ClockGen
Cplx Mpy
Spreader or
SPDR
OVSF Real and Imaginary
OVSF OVSF
SPRDR
Cmplx Gain IntDump Data (real) Physical layer control (imag)
2nd Deinterleaving DeIntLev
Demultiplexing Demux12
Rate Recovery
RM
RateM Transport Channel Codec TrChCdr

CODEC
1st Deinterleaving DeIntLev Convolutional Decoding Turbo Decoding ConvDec
or
CH
or TurboDec
Cyclic Redundancy Decode
CRC
CRCGen
Information bits
Figure 4.1.2: Uplink receive: critical block paths in transport and physical channels.
4 Using the Library
11
4.2
Downlink Transmit and Receive.
Figure 4.2.1 shows the generic functionality of the blocks that produce a downlink transmitter simulation, whilst in Figure 4.2.2 the downlink receiver is shown. Note that again, these figures only indicate the critical block path and do not illustrate, for example, multiuser or noisy simulations. Also note that there is more than one way to produce the same desired output. Therefore in cases where a designer wishes to specify each component, discrete single function blocks are provided. However if a standard compliant full downlink link is required, then a single fully parameterised block is available.
4 Using the Library
12
3GPP FDD - Downlink Transmit

Information bits
Cyclic Redundancy Coding
CRC
CRCGen Convolutional Coding Turbo Coding ConvEnc
or TurboEnc Transport Channel Codec TrChCdr

CODEC
Rate Matching
RM
RateM
1st Interleaving IntLeave
Transport Channel Mux Physical Control Chan Gen. IntLeave TChMux
2nd Interleaving IntLeave

DL
PHY CH
IQSplit
DPCCHGen
Clock Generator Complex data path ClockGen
DPCH GEN
DownLink
Orthogonal Variable Spreading Function
OVSF
OVSF or
DL Downlink LSCC Code Gen. DLLCGen
Spreader
SPDR
Cplx Mpy
SPRDR
Complex data path
Pulse Shaping RF Modulation
Cos Sin
Complex Gain, Channel Models
MPTH
or
MOV
or
BD
or Cplx Gain
Fading
Moving
Birth/Death
RF Output
Complex Data Output
RF Output
Figure 4.2.1: Downlink transmit: critical block paths in transport and physical channels.
or
CH
4 Using the Library
13
3GPP FDD - Downlink Receive

RF Input Complex Data Input
Cos Sin
Pulse Shaping RF Demodulation
Complex Symbols
DL Downlink LSCC Code Gen. DLLCGen
or
Clock Generator ClockGen
Cplx Mpy or
SPDR
SPRDR
OVSF
OVSF
IntDump
Cmplx Gain
2nd Deinterleaving DeIntLev
Demultiplexing Demux12
Rate Recovery
RM
RateM or Transport Channel Codec TrChCdr

CODEC
1st Deinterleaving DeIntLev Convolutional Decoding Turbo Decoding ConvDec
CH
or TurboDec
Cyclic Redundancy Decode
CRC
CRCGen
Information bits
Figure 4.2.2: Downlink receive: critical block paths in transport and physical channels.
4 Using the Library
14
4.3
Block Processing
All the library blocks operate in a sample by sample processing fashion. If a block is required to operate on a specific frame of data (e.g. a block interleaver) then it will serialize and de-serialize this array of data internally during processing. To ensure that the boundaries of data frames remain aligned as they pass through consecutive processing blocks, the library provides a number of parameters to control the synchronization. 4.3.1 The Delay Offset feature.
Consider the following simple system, shown in Figure 4.3.1, consisting of a source which is interleaved and deinterleaved with an arbitrary delay in between. Assume that the interleaving and deinterleaving block lengths are 804 bits.
N
input
output
Figure 4.3.1: Interleaving with delay
In the case of the delay being zero ( N = 0 ), the deinterleaver will see a perfectly aligned block to deinterleave and the input and output will simply be shifted relative to each other by 1608 bits - just double the block length. However, if the delay is non-zero, say N = 5 sample delays, the data into the de-interleaver will be misaligned and a corrupted output will be produced. One method of working around this situation is to introduce enough further delay to resynchronise. In this case 8045 = 799 samples. This is an awkward solution and will mean an extra 799 samples will have to be processed before output data is available, thus unnecessarily extending the simulation length. In the case of blocks with the delay offset feature, all that is required is to enable the feature by specifying 5 in the delay offset and enabling the delay in samples check box. Alternatively, the time for 5 samples could be entered in the delay offset and the delay in samples check box left unchecked. See Section 5.3.8 on page 102 for dialog box example of these parameters. The delay offset mechanism is therefore an effective mechanism for coping with delays in data that requires to be synchronised for processing.
4 Using the Library
15
4.3.2
The No Leading Output feature
The No Leading Output functionality is not support in Simulink. The library is available for a number of different simulation platforms however not a simulators offer the same kind of scheduling features. The No Leading Output feature is only supported on platforms which combine both data-flow and event-driven aspects in their model of computation.
5 The 3GPP:fdd Library Blocks
16

This section specifies the parametric and functional operation of the FDD library blocks. The library blocks are outlined in the following subsections:
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Spectrum Spreading and Channelisation Waveform Generators Code and Channel Generators Channel Coding Channel Generators Channel Models Synchronisation Physical Measurements Signal Multiplexors and Demultiplexors
5.1
Spectrum Spreading and Channelisation Waveform Generators
The library provides a number of blocks which will produce standard compliant spreading codes for the uplink and downlink, and also orthogonal codes for channelisation. The following blocks are provided:
OVSF
Orthogonal Variable Spreading Function Code Generator (OVSF) Uplink Short Scrambling Code Generator (ULSCGen) Uplink Long Scrambling Code Generator (ULLCGen) Downlink Long Scrambling Code Generator (DLLCGen) Spreader/Despreader (Spreader) Orthogonal Variable Spreading Function Fast Hadamard Transform (OVSFTran)
UL
SSCC
UL
LSCC
DL
LSCC
SPDR
OVSF FHT
The blocks allow the designer to build the scrambling/spreading using combinations of blocks or to use the SPRDR block which provides a single block that will implement the standard compliant, short, long, and orthogonal codes as appropriate for either the uplink or downlink. Figure 4.1.1 to Figure 4.2.2 illustrate the cross-over functionality between these blocks.
17
5.1.1 Orthogonal Variable Spreading Function (OVSF) Code Generator Block Name: OVSFGen
OVSF
Abbreviation: OVSF
Synopsis: This block generates OVSF code sequences according to the specified class/spreading factor and code number within the class.
Parameter
Range
Default Value
Definition The OVSF code class and length. This determines the size of the Hadamard matrix SF x SF The code number. Selects a row within the Hadamard matrix Input high/low threshold True output voltage False output voltage
Code Class/Spreading factor
C1..C12 SF=2..4096
C7/128
Code Number Input Threshold True Output False Output
0..(SF-1) All All All
16 0 -1 1
Block Inputs: Clock: Normally the chip rate clock. The code advances on the rising edge of the clock input. Block Outputs: Output: The code output sequence, updated on the rising edges of the clock input.
18
Discussion: The OVSF codes are used as channelisation codes to maintain orthogonality between different physical channels. They are also known as Walsh codes or OVSF codes and are generated from a Hadamard matrix as show below: H1 = 0 H2 = 0 0 0 1 0 H4 = 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0
[5.1.1]
[5.1.2]
[5.1.3]
H2N =
HN HN HN HN
[5.1.4]
where N is a power of two and H N denotes the binary complement of H N . The channelisation code C ch, SF, k is the k th row of H SF whose binary elements have been mapped into real values where 0 +1 and 1 1 . The different codes generated are C ch, 1, 0 = 1 , for SF = 1 C ch, 2, 0 C ch, 2, 1 C ch, 2 ( n + 1 ), 0 C ch, 2 ( n + 1 ), 1 C ch, 2 ( n + 1 ), 2 C ch, 2 ( n + 1 ), 3 C ch, 2 ( n + 1 ), 2 ( n + 1 ) 2 C ch, 2 ( n + 1 ), 2 ( n + 1 ) 1 = = C ch, 1, 0 C ch, 1, 0 = 1 1 , for SF = 2 C ch, 1, 0 C ch, 1, 0 1 1 C ch, 2 n, 0 C ch, 2 n, 0 C ch, 2 n, 1 C ch, 2 n, 1 C ch, 2 n, 0 C ch, 2n, 0 C ch, 2 n, 1 C ch, 2n, 1
, for [5.1.5]
[5.1.6]
SF = 2
(n + 1)
[5.1.7]
C ch, 2n, 2 n 1 C ch, 2n, 2 n 1 C ch, 2n, 2 n 1 C ch, 2 n, 2 n 1
19
where n = 1, 2, , 12 . For a given SF, there are SF different orthogonal codes. The orthogonal channelisation codes can be easily generated using the tree structure shown in Figure 5.1.1.
C ch, 4, 0 = ( 1, 1, 1, 1 ) C ch, 2, 0 = ( 1, 1 ) C ch, 4, 1 = ( 1, 1, 1, 1 ) C ch, 1, 0 = ( 1 ) C ch, 2, 1 = ( 1, 1 ) C ch, 4, 3 = ( 1, 1, 1, 1 ) SF = 1 SF = 2 SF = 4 C ch, 4, 2 = ( 1, 1, 1, 1 ) C ch, 8, 0 C ch, 8, 1 C ch, 8, 2 C ch, 8, 3 C ch, 8, 4 C ch, 8, 5 C ch, 8, 6 C ch, 8, 7 SF = 8
Figure 5.1.1: Orthogonal code generation structure
The spreading code period is the symbol period, hence, for a given chip rate, the spreading code period depends on the symbol rate. Parameter Dialog Box: Default parameters shown.
References: 3G TS 25.213: Spreading and Modulation (FDD)
20
5.1.2 Uplink Short Scrambling Code Generator

UL
Block Name: UplinkSCGen Abbreviation: ULSCGen
SSCC
Synopsis: Uplink Short Scrambling Code Generator See Also: Uplink Long Scrambling Code Generator
Parameter User Index Input Threshold True Output False Output Range Default value Definition 24 bit user index in hexadecimal Input high/low threshold True output voltage False output voltage
0n2
All All All
24
0x1, 0x2, 0x3 0 -1 1
Block Inputs: Clock: Normally the chip-rate clock. The code advances on the rising edge of the clock input. Block Outputs: Real: Real (I) code sequence updated on the rising edge of the input clock signal. Imaginary: Imaginary (Q) code sequence updated on the rising edge of the input clock signal. Discussion: The uplink short scrambling code is a 256 chip length code generated from two sequences c short, 1, n ( i ) and c short, 2, n ( i ) , which are obtained from a quaternary sequence z ( i ) . The n th quaternary sequence z n ( i ), 0 n 16777215 is calculated by adding three modulo 4 sequences, a quaternary sequence a ( i ) and two binary sequences b ( i ) and d ( i ) . The initial value of the sequences is
21
determined from the code number n (specified in the parameter dialog box as 24 bit user index n). If n 23, n 22, , n 0 is the 24-bit binary representation of the code number n , the initial values of the registers are loaded as specified below: a ( 0 ) = 2 n 0 + 1 modulo 4 a ( i ) = 2 n i modulo 4, i = 1, 2, , 7 b ( i ) = n 8 + i modulo 2, i = 0, 1, , 7 d ( i ) = n 16 + i modulo 2, i = 0, 1, , 7
[5.1.8] [5.1.9] [5.1.10] [5.1.11]
The sequences a ( i ) , b ( i ) and d ( i ) are generated recursively according to the following equations a(i) = a(i 3) +a(i 5) + 3a(i 6) + 2 a ( i 7 ) + 3 a ( i 8 ) mod 4, i = 8, 9, , 254 b(i) = b(i 1) + b(i 3) + b ( i 7 ) + b ( i 8 ) mod 2, i = 8, 9, , 254 d(i) = d(i 1) + d(i 3) + d ( i 4 ) + d ( i 8 ) mod 2, i = 8, 9, , 254 z n ( i ) is generated as z n ( i ) = a ( i ) + 2 b ( i ) + 2 d ( i ) mod 4, i = 0, 1, , 254
[5.1.15] [5.1.12]
[5.1.13]
[5.1.14]
and is extended to length 256 chips by setting z n ( 255 ) = z n ( 0 ) . z n ( i ) is then mapped into the real sequences c short, 1, n ( i ) and c short, 2, n ( i ) by using the table below. zn ( i )
0 1 2 3
c short, 1, n ( i )
+1 -1 -1 +1
c short, 1, n ( i )
+1 +1 -1 -1
22
Finally the complex valued uplink short scrambling sequence C short, n is defined as i C short, n ( i ) = cshort,1, n ( i mod 256 ) 1 + j ( 1 ) c short,2, n ( 2 ( i mod 256 ) 2 for i = 0, 1, , 255 , where )
[5.1.16]
denotes rounding to nearest lower integer.
The system to generate the 255 chip sequence is shown in the block schematic section, the generated sequence still needs to be extended by one chip to obtain the required 256 chip sequence. Initial Values: The binary representation n 23, n 22, , n 0 of the initial value n is loaded in the shift registers as shown below
2 n 7 mod4 2 n 5 mod4 2 n 3 mod4 2 n 1 mod4 2 n 6 mod4 2 n 4 mod4 2 n 2 mod4 ( 2 n 0 + 1 ) mod4 a(0)
3 mod 4 2 mod 4 mod 4 mod 4 3 3
n 15
n 14
n 13
n 12
n 11
n 10
n9
n8 b(0)
delay mod n addition multiplication
mod 2
mod 2
mod 2
n 23
n 22
n 21
n 20
n 19
n 18
n 17
n 16 d(0)
mod 2
mod 2 mod 2
Figure 5.1.2: The modulo-4 and two modulo-2 sequence generators.
23
Block Schematic:
a(i)
3 mod 4
3 3
mod 4 mod 4 mod 4
2
b(i)
zn ( i )
mapper mod 4
c short, 1, n ( i ) c short, 2, n ( i )
mod 2
mod 2
mod 2
2
d(i)
delay mod n addition
mod 2
mod 2 mod 2 Figure 5.1.3: Uplink short scrambling code generator.
multiplication
Parameter Dialog Box: Default parameters shown.
24
5.1.3 Uplink Long Scrambling Code Generator

UL
Block Name: UplinkLCGen Abbreviation: ULLCGen
LSCC
Synopsis: This block generates the uplink long scrambling code sequence. See Also: Uplink Short Scrambling Code Generator
Parameter Code Number Code Period Input Threshold True Output False Output Range 0 - (225-2) Positive All All All Default value 10 38400 0 -1 1 Definition Scrambling code number Code repetition period Input high/low threshold True output voltage False output voltage
Block Inputs: Clock: Normally the chip-rate clock. The code advances on the rising edge of the clock input. Block Outputs: Real: Real (I) phase of the code sequence, updated on the rising edges of the clock input. Imaginary: Imaginary (Q) phase of the code sequence, updated on the rising edges of the clock input. Discussion: This block generates the long scrambling code used in the uplink. All physical channels can be scrambled by a long or a short scrambling code. There are 224 long and 224 short scrambling codes. The long scrambling codes c long, 1, n the result of adding modulo 2 two generator polynomials of degree 25. of the sequence c long, 1, n . and c long, 2, n are Gold sequences, which are m-sequences, x and y generated from two c long, 2, n is a 16777232 chip shifted version
25
Let n 23, n 22, , n 0 be the binary representation of the code number n provided by the user in the parameter dialog box. This value is used as initial condition to generate the sequence x n in a linear shift register. If x n ( i ) is the i th symbol of the sequence x n , then x n ( 0 ) = n 0, x n ( 1 ) = n 1, , x n ( 23 ) = n 23, x n ( 24 ) = 1 The initial conditions for sequence y are y ( 0 ) = y ( 1 ) = = y ( 23 ) = y ( 24 ) = 1 Once the registers have been initialized, the following recursions are used x n ( i + 25 ) = x n ( i + 3 ) + x n ( i ) mod 2, i = 0, , 2
25
[5.1.18] [5.1.17]
27
25
[5.1.19]
y ( i + 25 ) = y ( i + 3 ) + y ( i + 2 ) + y ( i + 1 ) mod 2, i = 0, , 2
27
[5.1.20]
By adding x n ( i ) and y ( i ) modulo 2, a Gold sequence z n is obtained z n ( i ) = x n ( i ) + y ( i ) modulo 2, i = 0, 1, , 2

25
[5.1.21]
z n takes he values { 0, 1 } . A real valued Gold sequence Z n ( i ) that takes values { 1, 1 } is defined +1 if z n ( i ) = 0 25 for i = 0, 1, 2 2 Zn ( i ) = 1 if z n ( i ) = 1 the sequences c long, 1, n and c long, 2, n can now be defined as c long, 1, n = Z n ( i ), i = 0, 1, , 2 c long, 2, n = Z n ( ( i + 16777232 ) modulo ( 2
25 25
[5.1.22]
2
25
[5.1.23]
1 ) ), i = 0, 1, , 2
[5.1.24]
The shift register structure used to generate c long, 1, n and c long, 2, n is shown in the block schematic section. The uplink complex valued long scrambling sequence C long, n ( i ) is finally generated as C long, n ( i ) = c long, 1, n ( i ) ( 1 + j ( 1 ) c long, 2, n ( 2 i 2 ) ) for i = 0, 1, , 2 integer.
25 i
[5.1.25]
2 , and where
denotes rounding to the nearest lower
26
The code period parameter in number of chips determines the repetition period of the generated code. Chip number 0 of the long scrambling codes are generated at the beginning of a frame; 10 msec or 38400 chips are used, on the next frame the code generation stops, the generator is reset and the code generation starts again at chip number 0 of the long scrambling code. The code period parameter specifies the number of chips after which the code generation is reset and started again. Block Schematic:
c long, 1, n
xn ( i )
x n ( i + 25 ) y ( i + 25 )

y(i)
modulo 2 addition 1 sample delay Figure 5.1.4: Uplink long scrambling code generator.
c long, 2, n
References:
27
3G TS 25.213: Spreading and Modulation (FDD)
28
5.1.4 Downlink Long Scrambling Code Generator

DL
Block Name: DownlinkLCGen Abbreviation: DLLCGen
LSCC
Synopsis: Generates the downlink complex scrambling sequence.
Parameter
Range
Default value
Definition Group of scrambling code, each consists of 8 primary codes and 120 secondary codes Primary code group Secondary code group No. of scrambling code Scrambling code period before repeating Enables the use of the compressed mode The left alternative code is used (only in compressed mode is enabled) The right alternative code is used (only in compressed mode is enabled) Input high/low threshold True output voltage False output voltage
Scrambling Code Group
1 - 64
Primary Code Secondary Code Code No. Code Period Compressed Mode
Cp0 - Cp7 Pri., Cs1 - Cs15 0-218-1 Positive Enable/Disable
Cp0 Pri. 0 38400 Disable
Left Alt. Code
Enable/Disable
Enable
Right Alt. Code Input Threshold True Output False Output
Enable/Disable All All All
Disable 0 -1 1
Block Inputs: Clock: Normally the chip rate clock. The code advances on the rising edge of the clock input. Block Outputs: Real: Real (I) phase of the code sequence, updated on the rising edges of the clock input.
29
Imaginary: Imaginary (Q) phase of the code sequence, updated on the rising edges of the clock input. Discussion: The structure used to generate the downlink scrambling code is shown in the Block Schematic section. It can be seen that a total of 2 18 1 = 262143 different codes can be generated, but not all of them are used. Only 8192 are used, which are divided into 64 groups of 128 codes. Each group has 8 primary code and 120 secondary codes. There is a one to one correspondence between each primary code and 15 secondary codes, therefore there are 15 8 = 120 secondary codes in each code group. Table 5.1.1 shows the correspondence between the code number generated and the code group, the primary and the secondary codes. It can be seen that the primary codes are codes number n = 16 i with i = 0, 1, , 511 . The secondary codes are codes number 16 i + k with k = 1, , 15 , therefore only codes n = 0, 1, , 8191 are used. In compressed mode each of the scrambling codes has two codes associated depending on whether left or right alternative codes are used. This can be specified in the parameter dialog box when the compressed mode is selected. The correspondence of compressed mode codes with the code group number, the primary code, the secondary code and the code number are shown in Table 5.1.2. Alternative codes may be used for compressed frames. Left alternative codes corresponding to code n are codes number n + 8192 , while right alternative codes are codes number n + 16384 . If the channelisation code used for non-compressed frames is c ch, SF, m , left codes are used if m < SF 2 and right codes if m SF 2 . The complex valued scrambling sequence is generated by combining two real valued Gold sequences, which are constructed from two m-sequences generated by means of two generator polynomials of degree 18. Let the two m-sequences be x and y . These sequences are generated with the following initial conditions x ( 0 ) = 1, x ( 1 ) = x ( 2 ) = = x ( 16 ) = x ( 17 ) = 0 y ( 0 ) = y ( 1 ) = = y ( 16 ) = y ( 17 ) = 1
[5.1.26] [5.1.27]
The recursive expressions which determine the value of subsequent symbols are x ( i + 18 ) = x ( i + 7 ) + x ( i ) modulo 2, i = 0, 1, , 2
18
20
[5.1.28] [5.1.29]
y ( i + 18 ) = y ( i + 10 ) + y ( i + 7 ) + y ( i + 5 ) + y ( i ) modulo 2
30
for i = 0, 1, , 2 defined as
18
20 . The n th Gold sequence z n with n = 0, 1, , 2

18 18
18
2 is
z n ( i ) = x( ( i + n ) modulo ( 2
1 ) ) + y ( i ) modulo 2, i = 0, 1, , 2 2
[5.1.30]
z n is a binary sequence converted into a real valued sequence Z n as follows +1 Zn ( i ) = -1 if z n ( i ) = 0 18 for i = 0, 1, , 2 2 if z n ( i ) = 1

[5.1.31]
The n th downlink complex valued scrambling code S dl, n ( i ) is finally generated as S dl, n ( i ) = Z n ( i ) + jZ n ( ( i + 131072 ) modulo ( 2 for i = 0, 1, , 38399 .
18
1))
[5.1.32]
31
Scr Code Group
Primary Code
Secondary Code Pri. Cs 1
Code No. code 0 code 1 ... code 15 code 16 code 17 ... code 31
Cp 0
... Cs 15 Pri. Cs 1
Cp 1 ...
... Cs 15
Pri. Scr Code Group 0 Cp 7 Cs 1 ... Cs 15 Pri. Cs 1 Cp 0 ... Cs 15 Pri. Cs 1 Cp 1 ... Cs 15
code 112 code 113 ... code 127 code 128 code 129 ... code 143 code 144 code 145 ... code 159
Pri. Scr Code Group 1 Cp 7 Cs 1 ... Cs 15
code 240 code 241 ... code 255
Table 5.1.1:Correspondence between Scrambling Code Group, Primary Code (Cp), Secondary Code (Cs) and Code number

Pri. Cs 1 Pri ... Cs 15 Pri. Cp 1 Cs 1 ... Cs 15 code 8064 code 8065 ... code 8079 code 8080 code 8081 ... code 8095
32
Pri. Scr Code Group 63 Cp 7 Cs 1 ... Cs 15
code 8176 code 8177 .. code 8191
Table 5.1.1:Correspondence between Scrambling Code Group, Primary Code (Cp), Secondary Code (Cs) and Code number
Scr Code Group
Primary Code
Secondary Code Pri. Cs 1
Code No., left alternative code 8192 code 8193 ... code 8207 code 8208 code 8209 ... code 8223 ...
Code No., right alternative code 16384 code 16385 ... code 16399 code 16400 code 16401 ... code 16415
Cp 0
... Cs 15 Pri. Cs 1
Cp 1
... Cs 15
Scr Code Group 0 Cp 7
Pri. Cs 1 ... Cs 15
code 8304 code 8305 ... code 8319
code 16496 code 16497 ... code 16511
Table 5.1.2:Correspondence between Scrambling Code Group, Primary Code (CP), Secondary Code (Cs) and Code number for left and right alternative codes

Pri. Cs 1 Cp 0 ... Cs 15 Pri. Cs 1 Cp 1 ... Cs 15 Scr Code Group 1 Cp 7 code 8320 code 8321 ... code 8335 code 8336 code 8337 ... code 8351 code 16512 code 16513 ... code 16527 code 16528 code 16529 ... code 16543
33
Pri. Cs 1 ... Cs 15
code 8432 code 8433 ... code 8447
code 16624 code 16625 ... code 16639
Pri. Cs 1 Pri ... Cs 15 Pri. Cp 1 Cs 1 ... Cs 15
code 16256 code 16257 ... code 16271 code 16272 code 16273 ... code 16287
code 24448 code 24449 ... code 24463 code 24464 code 24465 ... code 24479
Scr Code Group 63
Pri. Cp 7 Cs 1 ... Cs 15
code 16368 code 16369 .. code 16383
code 24560 code 24561 .. code 24575
Table 5.1.2:Correspondence between Scrambling Code Group, Primary Code (CP), Secondary Code (Cs) and Code number for left and right alternative codes
34
Block Schematic:
x(i)
I
x ( i + 18 ) y ( i + 18 )

y(i)
Figure 5.1.5: Downlink long scrambling code generator.
35
5.1.5 Spreader/Despreader Block Name: Spreader

SPDR
Abbreviation: Spreader
Synopsis: Performs spreading and/or scrambling upon a baseband QPSK/BPSK signal for either downlink or uplink. The block can also be used to perform descrambling/de-spreading. See Also: OVSF Spreading Code Generator, Uplink Long Scrambling Code Generator, Uplink Short Scrambling Code Generator, Downlink Long Scrambling Code Generator
Parameter on Downlink tab Enable Channelisation Enable Scrambling Channelisation code class/SF Channelisation Code Number Scrambling code Set DL Code Range Enable/Disable Enable/Disable C0/SF=1..C9/ SF=512 0..(SF-1) 0-2N-1, N=18 Default value Enable Enable C7, SF=128 16 0 Definition Enables Channelisation/ Dechannelisation Enables scrambling/ descrambling OVSF code class/spreading factor OVSF spreading code number Scrambling code number Sets the downlink scrambling codes as in the downlink scr code block scrambling code repetition period Sets the downlink scrambling code by selecting the code group and the primary and secondary code number (see Section 5.1.4)
Period
Positive
38400
Set DL code
36
Parameter on Uplink tab Enable Channelisation Enable Scrambling Gain (I) Gain (Q) Channelisation code class/SF (I) Channelisation code class/SF (Q) Channelisation Code Number (I) Channelisation Code Number (Q) Scrambling code Period
Range Enable/Disable Enable/Disable 0,1/15, 2/15, ..., 1 0,1/15, 2/15, ..., 1 C0/SF=1..C9/ SF=512 C0/SF=1..C9/ SF=512 0..(SF-1) 0..(SF-1) 0-2N-1, N=24 Positive
Default value Enable Enable 1 (0 dB) 1 (0 dB) C7, SF=128 C7, SF=128 16 0 0 38400
Definition Enables Channelisation/ Dechannelisation Enables scrambling/ descrambling I channel gain Q channel gain OVSF code class/spreading factor for I channel OVSF code class/spreading factor for Q channel OVSF spreading code number for I channel OVSF spreading code number for Q channel Scrambling code number scrambling code repetition period (only active for long UL scrambling codes) Enables the use of short UL scrambling codes
Short UL code
Enable/Disable
Disable
General Parameters
Range
Default value Spread 0 Disable
Definition Despread uses the complex conjugate of the scrambling code Input high/low threshold The input signal is used as clock, each input sample is considered a chip Enabling sampling and hold of output
Tx/Rx Input Threshold Clock on data
Spread/Despread All Enable/Disable
Sample and Hold
Enable/Disable
Enable

Default value
37
General Parameters
Range
Definition Introduces an offset in the generation of the scrambling/ channelisation codes with respect to the beginning of the radio frame Introduces a delay offset when starting the spreading/ despreading of the chipped signal See section on leading output
Timing Offset (chips)
0-(PERIOD-1)
Delay Offset (clocks)
All
No leading output
Enable/Disable
Disable
Block Inputs: Clock: Normally the chip rate clock. The code advances on the rising edge of the clock input. I: If in spreading mode, this is the in-phase (real) baseband signal, otherwise it is the real part of the spread signal. Q: If in spreading mode, this is the quadrature-phase (imaginary) baseband signal, otherwise it is the imaginary part of the spread signal. Block Outputs: Real: If in spreading mode, this is the real (I) spread output, otherwise it is the de-spread real (I) baseband output. Imaginary: If in spreading mode, this is the Imaginary (Q) spread output, otherwise it is the de-spread (Q) baseband output. Discussion: A real spreading and complex scrambling scheme is used in this block, as it is specified for the downlink and uplink spreading/scrambling. The internal channelisation and scrambling structures are shown in Figure 5.1.9 and Figure 5.1.10 respectively for the downlink and uplink spreaders. In both cases the channelisation process uses real valued codes and involves a real spreading operation. The scrambling, on the other hand, uses complex valued operations and involves a complex multiplier. For the downlink scenario, the same real valued channelisation code is used for the I and Q channels, whereas in the uplink, different channelisation codes are used for I and Q components. The case of the uplink is different. In this case, I and Q channels are spread using different channelisation codes, the particular case for the DPCH being shown in Figure 5.1.10. For other physical channels, the spreader structure used is similar, therefore, for spreading uplink physical channels, more than one spreader despreader block has to be used.
38
The despreader structure is similar to the spreaders shown in Figure 5.1.9 and Figure 5.1.10 but using complex conjugate scrambling sequences. Moreover the gain of the I and Q components used in the uplink are not applied. There are two ways of clocking this block: Using a clock signal (connected to clock input) working at the chip rate. When a rising edge over the threshold (specified in parameters) is detected, the next chip of the channelisation and scrambling codes is considered. Input signal is considered as the clock. This means that each input sample is considered as a chip, which means that the input signal is considered to be sampled at chip the rate. The sample and hold option controls the way the spread spectrum signal is sent to the output of the block. If the sample and hold option is enabled, the output of the block gives the value of the spread spectrum chip which is maintained until the next chip value is produced as shown in Figure 5.1.6. If this option is disabled, the value of the produced chip is given by one sample only, setting the remaining samples to zero as depicted in Figure 5.1.6. See spreader_sample_hold_output.svu. After spreading, it is common to use a pulse shaping filter to reduce the bandwidth of the spread spectrum signal prior to modulation and transmission. The pulse shaping filter (typically a root raised cosine) needs to be fed with impulses. In this case the sample and hold option should be disabled.
39
Sample and Hold Enabled
time
Tc Sample and Hold Disabled
Tc
time
T c: Chip period
Figure 5.1.6: Output of spreader block in spreading mode. Shown with sample and hold mode enabled and disabled
The function of the two offset parameters is explained next: Timing Offset (chips): Under normal conditions the generation of chip zero of the channelisation and scrambling codes start at the beginning of every 10 msec radio frame. If a timing offset different from zero is given, an offset is introduced in the generation of chip zero of the scrambling and channelisation codes with respect to the beginning of the radio frame. This operation is shown in Figure 5.1.7. Note that the timing offset does not introduce a delay offset in the generation of the scrambling and channelisation codes.
40
Timing Offset = 0 chips

10 msec radio frame 10 msec radio frame
scrambling and channelisation codes chip 0
scrambling code chip 38399
scrambling and channelisation codes chip 0
Timing Offset = 100 chips

scrambling code chip 38399 10 msec radio frame scrambling code chip 38399 10 msec radio frame
100 chips
100 chips
scrambling and scrambling and channelisation codes channelisation codes scrambling code chip 0 chip 0 chip 38299 scrambling code scrambling code chip 38300 chip 38300
Figure 5.1.7: Effect of the timing offset parameter in the operation of the spreader block
Delay Offset (clocks): The beginning of the spreading/despreading operation is delayed a number of clock cycles. This offset is useful when spreading/ despreading with a delayed signal as shown in Figure 5.1.8.
41
time = 0
bit sequence
chip sequence generated by spreader beginning of spreading operation (delay offset = 0) delay delayed bit sequence
chip sequence generated by spreader
delay
beginning of spreading operation (delay offset = n clock cylces) Figure 5.1.8: Effect of the delay offset parameter in the operation of the spreader block
42
Block Schematic:
I
any downlink physical channel except SCH
serial to parallel
C ch, SF, m
I+jQ
spread/scrambled signal
S dl, n
j
C ch, SF, m: mth channelisation code with spreading factor SF S dl, n : nth downlink scrambling code
Figure 5.1.9: Downlink spreading structure. Used for all downlink physical channels except SCH
DPDCH
cd cc
DPCCH
d c
S short, nor S long, n

I+jQ spread/scrambled signal
c d DPDCH channelisation code c c DPCCH channelisation code d DPDCH gain factor c DPCCH gain factor S long, nUL long scrambling code UL short scrambling code S short, n
Figure 5.1.10: DPCH uplink spreading structure
43
Parameter Dialog Boxes: Default parameters shown.
44
45
5.1.6 OVSF Fast Hadamard Transform Block Name: OVSFTransform

OVSF FHT
Abbreviation: OVSFTran
Synopsis: This block implements the Fast Hadamard Transform, equivalent to one entire level of the OVSF code tree.
Parameter Transform Direction Range Forward/Inverse Default value Forward Definition Direction of the transform The level of the tree (given by the spreading factor) that is to be used in the transform See section on Delay Offset
OVSF Tree
SF = {1, 2, 4, 8, 16 32, 64, 128, 256 } 0
128
Delay Offset
Block Inputs: Input to the OVSF Transform. Block Outputs: Output from the OVSF Transform. Discussion: This block takes one input and applies the Fast Hadamard Transform. This transform consists of taking a level of the OVSF code tree and for each codeword therein, computing the inner product of the codeword with an input sample.
C ch, 4, 0 = ( 1, 1, 1, 1 ) C ch, 2, 0 = ( 1, 1 ) C ch, 4, 1 = ( 1, 1, 1, 1 ) C ch, 1, 0 = ( 1 ) C ch, 2, 1 = ( 1, 1 ) C ch, 4, 3 = ( 1, 1, 1, 1 ) SF = 1 SF = 2 SF = 4 C ch, 4, 2 = ( 1, 1, 1, 1 ) C ch, 8, 0 C ch, 8, 1 C ch, 8, 2 C ch, 8, 3 C ch, 8, 4 C ch, 8, 5 C ch, 8, 6 C ch, 8, 7 SF = 8
Figure 5.1.11: Code tree for fast Hadamard transform.
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The above code tree shows the four codewords at level 3, i.e. where SF=4. In this block, the choice of level is made by the OVSF Tree parameter. For SF=4, input samples will be taken in groups of 4, and outputs will be computed in groups of 4 as follows:
x[n] y [ n + i ] = x [ n + 1 ] C ch, 4, i x[n + 2] x[n + 3]
where i = 0, 1, 2, 3 , and n = 0, 4, 8, 12, The direction of the transformation specified by the Transform Direction option is used solely for normalisation purposes, as the transform itself in symmetric. A forward transform has a gain of (1/SF) in order that the peak magnitude of the output will not exceed that of the input. Conversely the inverse transform has a gain of SF. For a given spreading factor SF, this block will generate groups of SF consecutive outputs which give a measure of the correlation of an input sequence of length SF with the SF different channelisation codewords at that level in the code tree. For example, with SF=128, 128 input samples will be read and 128 output samples will be created giving the correlation of the input sequence with channelisations codewords 0 through 127. Parameter Dialog Box: Default parameters shown.
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References:
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5.2
Code and Channel Generators
This section details code generation blocks which will produce various standard compliant codes (or signalling sequences) to be used for 3GPP. The code generating blocks are:
PILOT
Pilot Symbol Generator (PilotGen)
UL
RACH
Uplink Random Access Channel Preamble Generator (RACHPGen)
DL
SCH
Downlink Synchronisation Code Generator (SCHGen)
PHY CH
Physical Channel Generator / Multiplexer (PhyChGen)
The pilot symbol generator (PilotGen) generates standard compliant pilot symbol information which is later used for coherent detection in the receiver. All the patterns from the 3GPP standard for uplink and downlink, diversity and main antennas can be generated using this block.
UL
PILOT
The Uplink Random Access Channel Preamble Generator (RACHPGen) generates the random access channel preamble burst which consists of a signature scrambled with a random access channel preamble scrambling code. This preamble is pre-defined by the standard.
DL
RACH
The synchronisation code generator (SCHGen) produces the primary and/or secondary search codes transmitted in the 1st symbol position of the downlink Primary Common Control Physical Channel (PCCPCH).
SCH
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This block CH generates the Dedicated Physical Control Channel (DPCCH) for uplink and downlink Dedicated Physical Channels (DPCH), the uplink Physical Random Access Channel (PRACH) and the downlink Secondary Common Control Physical Channel (S-CCPCH). The DPCCH carries the power control (TPC), Transport Format Combination Indicator (TFCI) and pilot symbols.
PHY
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5.2.1 Pilot Symbol Generator Block Name: PilotGenBlock

PILOT
Abbreviation: PilotGen
Synopsis: Generates the pilot symbols that are used for coherent detection in the receiver. All the patterns for uplink and downlink, diversity and main antennas can be generated.
Parameter
Range UL DPCH, DL DPCH Ant. 1, DL DPCH Ant. 2, CPICH Ant1, CPICH Ant2, S-CCPCH Ant1, S-CCPCH Ant2 2, 4, 8, 16 bits (dependent upon mode)
Default value
Definition
Pilot Symbol Mode
D/L DPCH Ant. 1
Pilot symbol sequence selection according to the type of channel and diversity selection
Number of Bits Symbol Timing Offset
8 bits 0
Number of bits in the pilot symbol sequence. Symbol offset within the slot. In Enabled it produces the corresponding sequence of pilot bits (ignoring the other fields of the slot structure) Enables the use of even bits to I channel Input high/low threshold True output voltage False output voltage
Clock on data (pilot bits only)
Enable/Disable
Disable
Even bits to I Ch (DL only) Input Threshold True Output False Output
Enable/Disable All All All
Enable 0 1 -1
Block Inputs: Clock: Normally the symbol-rate clock. The code advances on the rising edge of the clock input.
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Slot Clock: Normally a 1500Hz clock the rising edge of which indicates symbol 0 of the slot. Block Outputs: Real: Real (I) part of the pilot symbol (even bits unless otherwise stated in the parameters). In Uplink mode only the Q output should normally be used. When the pilot symbols are not being transmitted, this output is 0. Imaginary: Imaginary (Q) part of the pilot symbol (odd or even bits depending on parameters). This is the output used in uplink scenarios. When the pilot symbols are not being transmitted, this output is 0. Mask: Low during the pilot symbol period, otherwise high. Slot #: Slot number 0-15 of the current slot being transmitted. It is incremented upon the rising edge of the slot clock input. Discussion: This block generates a sequence of pilot symbols known to the transmitter and receiver. These symbols are used by the receiver to establish the phase of the channel so that it can perform coherent detection. The pilot symbols are often used for making channel impulse response measurements by matched filtering the spread signal against the spreading code sequence that corresponds with the pilot symbol period. The pilot symbols generated and their position depend upon the type of physical channel. The position of the pilot symbols sequence relative to the start of the slot can be changed by setting the symbol timing offset parameter. The mask output is set to low when the pilot symbols are generated, therefore indicating the position of the pilot symbol sequence. The clock on data option enables the generation of the sequence of pilot bits for each slot ignoring the rest of the fields of the physical channel slot. Figure 5.2.1 illustrates the effect of enabling this option. For downlink Space/Time Transmit Diversity (STTD), a different pilot symbol sequence is transmitted on each antenna, named Ant.1 and Ant. 2 in the parameter dialog box. This enables the receiver to identify the two paths.

UL DPCH PILOT slot #2 clock on data: disabled pilot sequence #2 clock on data: enabled pilot sequence #2 pilot sequence #3 pilot sequence #4 the pilot sequence #3 TFCI FBI TPC PILOT slot #3
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TFCI FBI TPC
Figure 5.2.1: Effect of clock on data option.Shown for generation of a pilot sequence for UL DPCH.
The different pilot symbol sequences generated are the following: UL DPCH: DPCH is composed of DPDCH and DPCCH which are I/Q multiplexed. Only the DPCCH carries pilot symbols, whose slot structure is shown in Figure 5.2.2. The pilot sequence for the uplink PRACH, is the same as the one for the DPCCH when N pilot = 8 bits. Therefore this block can also be used to generate the pilot sequence for the PRACH.
Npilot bits DPCCH PILOT 2560 chips
Figure 5.2.2: DPCCH slot structure
NTFCI bits NFBI bits NTPC bits TFCI FBI TPC
DL DPCH (Ant. 1 & Ant. 2): Within one DL DPCH, data DPDCH and control DPCCH information are time multiplexed and transmitted as shown in Figure 5.2.3. The pilot symbol sequences depend on the considered antenna.
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Ndata1 bits
NTPC bits NTFCI bits
Ndata2 bits
Npilot bits
DATA1 DPDCH
TPC
TFCI
DATA2 DPDCH
PILOT DPCCH
DPCCH 2560 chips
Figure 5.2.3: DL DPCH slot format
CPICH (Ant. 1 & Ant. 2): The CPICH is used as the phase reference for the downlink physical channels. It is a fixed rate channel with a SF=256 that carries a determined symbol sequence. The slot structure is shown in Figure 5.2.4. The predeCPICH Predetermined symbol sequence
2560 chips
Figure 5.2.4: CPICH slot format
termined symbol sequence is different for antenna 1 and 2 in case of STTD operation. The pattern used is shown Figure 5.2.5, where A = 1 + j . A A A A A A A A AA A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
slot #14 frame #i slot #0 frame #i+1 slot #1 A = 1+j
Figure 5.2.5: Symbol sequence used in CPICH
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S-CCPCH (Ant. 1 & Ant. 2): this channel is used to carry the FACH and the PCH. The slot structure for the S-CCPCH is shown Figure 5.2.6.
NTFCI bits
Ndata bits Data
Npilot bits
S-CCPCH
TFCI
Pilot
2560 chips
Figure 5.2.6: S-CCPCH slot format
References: 3G TS 25.211: Physical channels and mapping of transport channels into physical channels (FDD)
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5.2.2 Uplink Random Access Channel Preamble Generator

UL
Block Name: RACHPreamble Abbreviation: RACHPGen
RACH
Synopsis: Generates the RACH preamble burst which consists of a signature scrambled with a RACH preamble scrambling code.
Parameter Signature number Preamble Scrambling Code Number Preamble Scrambling Code Group Input Threshold True Output False Output
Range 0-15 0-15 0-511 All All All
Default value 1 10 0 0 1 -1
Definition RACH Preamble signature Preamble scrambling code number Preamble scrambling code group Input high/low threshold True output voltage False output voltage
Block Inputs: Clock: Normally the chip-rate clock. The code advances on the rising edge of the clock input. Enable: A one-shot trigger pulse that causes a preamble burst to be sent upon the rising edge. Block Outputs: Real: Real (I) output. Imaginary: Imag (Q) output. Discussion: The Physical Random Access Channel (PRACH) is used to carry the RACH (transport channel). The random access transmission is structured into one or several preambles of 4096 chips and a message part of length 10 ms or 20 ms as shown in Figure 5.2.7.
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Preamble 4096 chips
Preamble 4096 chips
Preamble 4096 chips
Message part 10 ms Message part 20 ms
Preamble 4096 chips
Preamble 4096 chips
Preamble 4096 chips
Figure 5.2.7: Random access transmission structure
The UE can start transmission only at a specific number of time slots called access slots, and the random-access transmission is based on a slotted-ALOHA scheme. The preamble part of the random access transmission is generated in this block. The random access preamble code is a complex valued sequence C pre, n, s which consists of a signature sequence C sig, s and a scrambling code S r-pre, n combined as C pre, n, s ( k ) = C sig, s ( k ) S r-pre, n ( k ) e
- k j -- + -4 2
k = 0, 1, , 4095
[5.2.1]
This sequence is generated once a rising edge is detected in the Enable block input. The preamble scrambling sequence S r-pre, n is one of the long scrambling sequences c long, 1, n generated as indicated in 3G TS 25.213: Spreading and modulation (FDD). Only the first 4096 chips of c long, 1, n are taken S r-pre, n ( i ) = c long, 1, n ( i ), i = 0, 1, , 4095
[5.2.2]
There are 8192 PRACH preamble scrambling sequences ( n = 0, 1, , 8191 ) divided in 512 groups of 16 codes each such as n = 16 m + k
[5.2.3]
where k is the scrambling code number with k = 0, 1, 15 of the m th code group with m = 0, 1, , 511 . k is specified in the parameters as scrambling code number, whereas m is the scrambling code group. The preamble signature C sig, s is built from 256 repetitions of a length 16 signature P s ( n ) with n = 0, 1, , 15 . Therefore C sig, s can be defined as C sig, s ( i ) = P s ( i mod 16 ), i = 0, 1, , 4095
[5.2.4]
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There are 16 signature codes s = 0, 1, , 15 , where s is a block parameter. The different sequences P s ( m ) are taken from the set of 16 Hadamard sequences specified in 3G TS 25.213: Spreading and modulation (FDD). Block Schematic:
C pre, n, s ( k )
- k -- + -j 4 2
C sig, s ( k )
S r-pre, n ( k )
Figure 5.2.8: RACH generation.
References: 3G TS 25.211: Physical channels and mapping of transport channels into physical channels (FDD) 3G TS 25.213: Spreading and modulation (FDD)
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5.2.3 Synchronisation Code Generator

DL
Block Name: SyncCodeGen Abbreviation: SCHGen
SCH
Synopsis: Generates the primary and/or secondary search codes transmitted in the 1st symbol position of the downlink Primary Common Control Channel (PCCCH).
Parameter
Range
Default value Cp (primary code) Group 0 0 0 dB 0 dB
Definition Sync code number (if auto code select not enabled.) Scrambling code group Chip timing offset in slot Primary synch code gain Secondary synch code gain Enables automatic selection of the secondary synch code according to the slot number and scrambling code group. Input high/low threshold Peak output voltage (v)
Sync Code Number Scr. Code Group Chip Timing Offset Pri. code Gain, Gp Sec. code Gain, Gs Select code according to slot number and group Input Threshold Peak Output Level
Cp, C1-C16 Group 0-63 0-2559 All All
Enable/Disable
enabled
All All
0 1
Block Inputs: Chip Clock: Normally the chip-rate clock. The code advances on the rising edge of the clock input. Slot Clock: Normally a 1500Hz clock, the rising edge of which is taken as the first chip of the slot. Block Outputs: Real: Real (I) synchronisation code output. Imaginary: Imaginary (Q) synchronisation code output which is identical to the Real output at the current time. Mask: Low when the synchronisation code is being transmitted, otherwise high. Use this output to mask the BCH data on the pri-
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mary CCPCH, or to sample the output of a matched filter on its rising edge. Pri. Code: The primary search code. Sec. Code: The secondary search code. Slot #: Indicates the slot number 0-15 that is currently being generated. It is incremented on the rising edge of the slot clock input. Discussion: The primary SCH and secondary SCH consists of 256 chips at the beginning of the a slot which is filled with the P-CCPCH as shown in Figure 5.2.9
SCH 256 chips P-CCPCH Data (BCH)
18 bits
2560 chips
Figure 5.2.9: Position of primary SCH in slot
The SCH is used for cell search. It consists of two subchannels, the primary SCH and the Secondary SCH. The structure of a SCH frame is shown in Figure 5.2.10
Slot #0 Slot #1 Slot #14
Primary SCH Secondary SCH
cp ac s
i, 0
cp cs
i, 1
cp cs
i, 14
256 chips
256 chips
256 chips
2560 chips 10 ms, one SCH frame
Figure 5.2.10: Structure of SCH frame
The primary synchronization code c p is the same for all slots and is kept fixed for every cell in the system. It is generated as follows: let a be a = ( x 1, x 2, , x 16 ) = ( 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 )
[5.2.5]
the sequence a is repeated and modulated by a Golay sequence, a complex valued sequence with the same real and imaginary part is created, which is c p , defined as c p = ( 1 + j ) ( a , a , a , a , a , a, a, a , a , a , a , a , a , a , a , a )
[5.2.6]
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The secondary synchronization code (SSC) has been denoted in Figure 5.2.10 as i, k c s , where i = 0, 1, , 63 is the number of scrambling code group and k = 0, 1, , 14 is the slot number. k is known to the block through the slot clock input, which helps the block count the time slot. i is given to the block as a parameter (Scr Code Group), in this case, the code group and the time slot number determine which SSC to generate by using the SSC allocation table specified in 3G TS 25.213. There are 16 secondary synchronization codes C SSC, n with n = 1, 2, , 16 . The value of the SSSC code number n is determined by the scrambling code group (parameter) and the slot number (input) unless the select code according to slot number and group option is disabled, the code number n can then be chosen as a parameter (Sync Code Number). The secondary synchronization codes C ssc, n are generated by multiplying the elements of a Hadamard sequence and a sequence z defined as z = ( b, b, b, b, b, b, b, b, b, b, b, b, b, b, b, b ) where b = ( x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16 )
[5.2.8] [5.2.7]
If h m ( s ) and z ( s ) denote the s th symbol of the m th Hadamard sequence and z respectively where s = 0, 1, , 255 , the n th secondary code C ssc, n can be generated as C ssc, n = ( 1 + j ) ( h m ( 0 ) z ( 0 ), h m ( 1 ) z ( 1 ), , h m ( 255 ) z ( 255 ) ) where m = 16 ( n 1 ) . The m th Hadamard sequence with m = 0, 1, , 255 is the m th row of matrix H 8 constructed recursively as H0 = 1 Hp 1 Hp 1 p1 Hp 1 Hp 1
[5.2.10] [5.2.9]
Hp =
[5.2.11]
Even though the primary and secondary codes are complex, their real and imaginary part are identical at any time instant, therefore they can be accessed independently using the Primary and Secondary code outputs (showing the real or imaginary part of the sequence).
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References: 3G TS 25.211: Physical channels and mapping of transport channels into physical channels (FDD) 3G TS 25.213: Spreading and modulation (FDD)
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5.2.4 Physical Channel Generator / Multiplexer Block Name: DPCCHGen

PHY CH
Abbreviation: PhyChGen
Synopsis: Generates the Dedicated Physical Control Channel (DPCCH) for uplink and downlink, which carry physical layer control information, such as power control (TPC), Transport Format Combination Indicator (TFCI), Feedback Information (FBI) and pilot symbols. The channels generated are: uplink Dedicated Physical Control Channel (DPCCH), the uplink Physical Random Access Channel (PRACH), the downlink Dedicated Physical Channel (DPCH) and the downlink Secondary Common Control Physical Channel (S-CCPCH).
Parameter
Range UL DPCCH, PRACH, DL DPCH S-CCPCH TFCI Disabled, Default TFCI, Split TFCI
Default value
Definition
Physical Channel Type
DL DPCH
Physical channel selection
TFCI Mode
Default TFCI
Transport Format Combination Indication mode.

Default value
63
Parameter
Range For DL DPCH: 15kbps, Npilot = 4 30kbps, Npilot = 2, 4, 8 60kbps, Npilot = 4, 8 120kbps, Npilot = 8 240kbps, Npilot = 8 480kbps, Npilot = 16 960kbps, Npilot = 16 1920kbps, Npilot = 16 For S-CCPCH: 30kbps, Npilot = 0, 8 60kbps, Npilot = 0, 8 120kbps, Npilot = 0, 8 240kbps, Npilot = 0, 8 480kbps, Npilot = 0, 16 960kbps, Npilot = 0, 16 1920kbps, Npilot=0, 16
Definition
Channel Rate (DL DPCH and S-CCPCH only)
60 kbps, Npilot = 8 for DL DPCH 30 kbps, no pilot for S-CCPCH
In Downlink DPCH mode, channel rate specifies the DPCH output rate (including both DPDCH and DPCCH data) The required DPDCH input data rate is indicated in the dialog box. Not applicable to uplink DPCCH which is always 15kbps (SF=256). It also indicates the number of pilot bits to be used.
DPCCH Gain (DL DPCH and S-CCPCH only)
Off, N/15, N=1..15
Gain applied to the control part of the DL slots (DL DPCH and S-CCPCH). With this gain set to off the control part of the DL slots is disabled. Enables the use of a diversity antenna for STTD mode. It determines the pilot sequence to be used. Determines the no. of bits to be used in the FBI field Input high/low threshold True output voltage False output voltage
Diversity Antenna (DL DPCH and S-CCPCH only) No. FBI bits (UL DPCCH only) Input Threshold True Output False Output
Enable/Disable
Disabled
{0, 1, 2} All All All
0 0 1 -1
Block Inputs: DPDCH Data: Only used in downlink mode, where data is time multiplexed with the control information, in the uplink data and control are I/Q multiplexed. The Dedicated Physical Data Channel (DPDCH) bit stream input. The sample rate must be one sample per bit and the bit rate is calculated and given to the user
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in the parameter dialog box for the chosen parameters. This is normally the data from the channel coding and interleaving stages. TPC: An input level less than or equal to zero results in a stepdown power command being sent (00). Conversely an input level greater than zero causes a step-up power command to be sent (11). FBI: Feedback mode bits are currently not used but are included for future use. If enabled an input less than or equal to zero results in a 0 being transmitted, otherwise a 1 is transmitted. TFCI: Transport Format Combination Indicator (TFCI) word input. The default TFCI is a 6 bit word that indicates to the receiver how the transport channel(s) are multiplexed. In default TFCI mode, the value of the TFCI word is 0 to 63. In extended TFCI mode, the TFCI input is a 7-10 bit word (0-1023). Reset: Resets the slot counter to slot 0. Block Outputs: Data Out: Output bit stream. In Downlink DPCH mode the output data stream consists of the DPDCH input stream time-multiplexed with the DPCCH bits. In the uplink modes, the output data stream is the DPCCH only at a rate of 15kbps. This output is real and to convert it into a complex channel (for the DL) the IQ mixer block is required. DPCCH Mask: True when DPCCH bits are being output otherwise false. Slot #: Indicates the current slot number 0-14. Discussion: The Physical Channels form the link level radio channel resource that carries the channel coded transport channel(s). There are, broadly speaking three types of physical channel: Broadcast, Dedicated and Random Access. The Broadcast physical channels (e.g. Primary/Secondary Common Control Physical Channels, Forward Access Channel) appear on the downlink only and are broadcast cell-wide. They are specialised channels that only carry control information rather than traffic. The Random Access channels (e.g. Physical Random Access Channel) is an uplink channel which can be transmitted from anywhere in the entire cell and is characterized by a collision risk. The Dedicated Physical Channel (DPCH) is available on both the downlink and uplink. It is made up of two sub-channels: the Dedicated Physical Control Channel (DPCCH) and the Dedicated Physical Data Channel (DPDCH) as shown in Figure .
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Logical Channels eg DTCH
Transport Channels (eg DCH)
Dedicated Physical Data Channel DPDCH Physical Channel (eg DPDCH) output to spreading and modulation
Power Control (TPC) Transport Format (TFCI) Dedicated Physical Control Channel DPCCH
Pilot Symbols Figure 5.2.11: Dedicated Physical Channel Mapping. Logical, transport and physical control channels are mapped onto the dedicated physical channel (DPCH).
The way in which control and traffic data are combined depends upon whether the channel is on the uplink or the downlink. The uplink transmits independent BPSK on the I and Q modulation phases. The (traffic) data (DPDCH) is transmitted on the I phase. The control data (DPCCH) is transmitted on the Q phase and is always transmitted at 15 kbps, as shown in Figure 5.2.12.
I Channel
Uplink DPDCH Data

Q Channel
PILOT
TFCI FBI TPC
Figure 5.2.12: DPDCH and DPCCH on the uplink DPCH.
The downlink DPCH combines the DPDCH and DPCCH into one stream as shown in Figure 5.2.13. Data and control traffic are time multiplexed into the DPCH, the resulting stream is then QPSK modulated:
DATA1 TPC TFCI DPDCH DPCCH DATA2 DPDCH PILOT DPCCH
Figure 5.2.13: DPDCH and DPCCH on the downlink DPCH.
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The uplink physical random access channel (PRACH) does not transmit FBI or TPC and has an extended pilot word as depicted in Figure 5.2.14:
Q channel PILOT TFCI
Figure 5.2.14: Uplink PRACH control channel.
The Secondary Common Control Physical Channel (S-CCPCH) is composed of a TFCI field, a data stream and is terminated with pilot symbols as shown in Figure 5.2.15:
TFCI DATA PILOT
Figure 5.2.15: Downlink S-CCPCH.
The Transport Format Combination Indicator word (TFCI) is a 6 or 10 bit word that is channel coded into 32 bits per 10 ms radio frame (therefore there are two bits per frame) using a (32,6) or (16,10) bi-orthogonal coding scheme. The (16,10) biorthogonal code is used only when TFCI is operated in split mode. The FBI field is used to support services that require the feedback of information between the UE and the base station, such as closed loop mode transmit diversity and site selection diversity (SSDT). The FBI field is divided into S and D fields, where the S field is used for SSDT transmission and the D field for Closed Loop Mode Transmit Diversity Signalling. For more information on the use of the S and D field.
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References: 3G TS 25.211: Physical channels and mapping of transport channels into physical channels (FDD)
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5.2.5 Downlink Dedicated Channel Generator Block Name: DownlinkDedicatedLayerOneChannelModel Abbreviation: DLDCHMDL
Synopsis: This block produces Downlink Dedicated Coded Composite Transport and Physical Channels with Compressed Mode support. The block incorporates: General CCTrCH (fixed or flexible DTX) supporting any number of TrCH and complete Transport Format Sets; Automatic Rate Matching calculations including Compressed Mode by Puncturing support; Internal MAC data source model including Transport Format Combination selection; Downlink Dedicated PhyCH (DPCH); Multiple simultaneous Compressed Mode patterns with Puncturing, SF/2 and Higher Layer Scheduling. Parameters:
Parameter CCTrCH / PhyCH Configuration File Compressed Mode Schedule Configuration File Range Any accessible XML file containing a valid configuration Any accessible XML file containing a valid configuration Default value Definition The filename of the XML file containing the configuration to use.
BearerService12_2.xml
CompressedModePatterns.xml
The filename of the XML file containing the configuration to use
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CCTrCH / PhyCH XML Configuration File Format:
Element: Channels
Element PhyCH CCTrCH Range must occur only once must occur only once Definition Specifies the configuration of the physical channel. Specifies the configuration of the coded composite channel.
Element: PhyCH
Attribute Range Definition Specifies which slot format to use for the physical channel; specifically this sets the spreading factor and the arrangement of fields from the DPDCH and DPCCH physical channels. See the DPCH slot format table below. The channelisation code used for spreading the data at the output of the physical channel. SF is the spreading factor, given by the slot format. The scrambling code number for the complex scrambling applied to the output of the physical channel.
SlotFormat
0...16
ChannelCodeNumber
0...SF-1
ScramblingCodeNumber
0...38399
Element: CCTrCH
Element/Attribute Range Definition Specifies whether the position of any DTX periods in the CCTrCH are fixed or flexible. Flexible position DTX allows for Compressed Mode by Higher Layer Scheduling. Specifies the configuration of an individual transport channel in this coded composite.
DTXPosition
{fixed,flexible}
TrCH
must occur at least once, may occur more than once
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Element: TrCH
Element/Attribute TrID TTI CRC Coding Range integer >=0 {10,20,40,80} {0,8,12,16,24} {conv2,conv3,turbo} Definition A numeric identifier for this transport channel. Specifies the Transmit Time Interval (TTI) in milliseconds. Specifies the CRC length in bits. Specifies the type of channel coding: 1/2 rate convolutional, 1/3 rate convolutional or turbo. Rate matching attribute, involved in rate matching calculation and determines rate matcher output block sizes.
RMAttribute
1...256
SourceType, SourceValue DynamicPartList
See section on Source Configuration. must occur once Defines the aspects of the transport channel configuration which can change from TTI to TTI.
Element: DynamicPartList
Element TBS Range must occur at least once, may occur more than once Definition Specifies the configuration of transport blocks for a TTI.
Element: TBS
Attribute BlockSize Range 1...163840 1...163840 and an integer multiple of BlockSize Definition Size of an individual transport block at the input to the channel coding. Total size of the set of transport blocks for channel coding.
BlockSetSize
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Compressed Mode schedule XML Configuration File Format:
Element: Patterns
Element Pattern Range must occur at least once, may occur more than once Definition Specifies the configuration of the a compressed mode pattern.
Element: Pattern
Attribute Active TGCFN TGSN TGL1 TGD TGL2 TGPL1 TGPL2 TGPRC Range {0,1} 0...255 0...14 0...14 integer 0...14 integer integer integer Definition Specifies whether or not this pattern is active; if not it is ignored. Connection Frame Number. Starting Slot Number, the start of Gap 1. Gap 1 Length. Gap Distance, the distance between the start of Gap 1 and Gap 2. Gap 2 Length. Period of Pattern 1. Period of Pattern 2.a Pattern Repetition Count. Specifies the manner in which Compression is achieved: Spreading Factor Reduction, Higher Layer Signalling or Puncturing. Specifies the frame type A or B; results in a modified slot format. See the table of DPCH slot formats below.
CompressionType
{SFR,HLS,PUNC}
FrameType
{A,B}
a. TGPL1 and TGPL2 cannot both be zero.
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DPCH Slot Formats: This table shows the slot formats resulting from the choice of SlotFormat attribute in the PhyCH XML configuration element and the FrameType attribute in the Compressed Mode Pattern XML configuration element:
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Source Configuration: The table below shows the valid combinations of SourceType and SourceValue elements to generate source data. All sources produce a sequence of values 0 and 1 i.e. representing bits. In the case of finite-length definition of sources such as bitfield and file, the bit sequence generated will repeat when more bits are requested from this source than are defined by it.
SourceTypea SourceValue interpretation SourceValue Range Definition Generates the bit sequence from PN generator with pn9 integer seed for PN initialisationb 0...511 polynomial x 9 + x 4 + 1 with starting state given by SourceValue. Generates the bit sequence from PN generator with pn15 integer seed for PN initialisation 0...32767 polynomial x 15 + x + 1 with starting state given by SourceValue.
file
string specifying filename string specifying bitfield ---
a valid filename specifying a file containing whitespace separated characters 0 and 1 representing bits. See Source Configuration Examples. --A source producing zeros. A source producing ones. Generates the bit sequence from PN generator with
bitfield zeros ones
pn9_itu
integer seed for PN initialisation
0...511
polynomial x 9 + x 5 + 1 with starting state given by SourceValue. Generates the bit sequence from PN generator with
pn23
0...8388607
polynomial x 23 + x 18 + 1 with starting state given by SourceValue.
a. The strings describing SourceType are case-insensitive. b. If a seed value of 0 is given for any of the PN sequence sources, a randomly chosen seed will be internally generated.
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Source Configuration Examples:

SourceType SourceValue Source bit sequence generated 1,0,0,1,1,0,0... Interpretation SourceValue interpreted as a binary vector of bits SourceValue interpreted as a hexidecimal number, converted into a sequence of bits.a
bitfield
1001
bitfield
0xA5
1,0,1,0,0,1,0,1,1,0,1...
a. Bit sequence generated will always be a multiple of 4 bits in length i.e. leading zero bits of most significant nibble will be generated.
Example CCTrCH / PhyCH XML configuration:
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Example Compressed Mode schedule XML configuration:
Block Inputs: None Block Outputs: PhyCH Chip Real: Real part of the chip output from the physical DPCH channel. PhyCH Chip Imag: Imaginary part of the chip output from the physical DPCH channel. CCTrCH Frame: Current frame of data in the coded composite transport channel. DCH0 TBS: The transport block set bits input to the coding for the first transport channel in the coded composite. DCH1 TBS: The transport block set bits input to the coding for the second transport channel in the coded composite.
76
Parameter Dialog Box:
77
5.3
Channel Coding
Prior to transmission information bits are coded to allow for error detection and correction at the receiver. The library provides a number of channel coding blocks which can be configured with 3GPP standard values. Each coding mechanism (i.e. convolutional coding, turbo coding, CRC coding, interleaving etc.) is implemented by an individual block. Alternatively the Transport Channel Coder allows all of the transport channel coding functions to be performed in one block. The following channel coding blocks are included in the library:
CRC
Cyclic Redundancy Coding (CRC) - Encoder/Decoder (CRCGEN)
Convolutional Encoder (ConvEnc)
Convolutional Decoder (Viterbi Algorithm) (ConvDec)
Turbo Encoder (TurboEnc)
Turbo Decoder (TurboDec)
RM
Rate Matcher (RateMtch)
Interleaver (IntLeave)
De-Interleaver (DeIntLev)
CODEC
CH
Transport Channel Coder (TrChCdr)
Transport Channel Multiplexer (TrChMux)
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5.3.1 Cyclic Redundancy Coding (CRC) - Encoder/Decoder Block Name: CRCGen

CRC
Abbreviation: CRCGen
Synopsis: In encode mode this block reads in data bits segmenting them into transport channel blocks. A CRC checksum is computed and appended to the block. In decode mode, the block removes the CRC and indicates if any errors occurred in the block.
Parameter Mode
Range Encode/Decode GRCR8, GCRC12, GCRC16, GCC24
Default value Decode
Definition Selects Encode or Decode mode Selects the polynomial to be used for CRC checksum calculation Block length over which the CRC is computed. In this description the block length is denoted as N Delay offset in bits or seconds Indicates that offset delay is specified in bits when checked. Input high/low threshold TRUE output voltage FALSE output voltage See section on leading output.
Polynomial
GCRC16
Block Length (bits)
>0
20
Offset Delay
Offset in Bits Input Threshold TRUE Output FALSE Output No leading output
Enable/disable All All All Enable/disable
Disable 0 1 -1 Disable
Block Inputs: Data Input: The serial input data. The input sample rate must be equal to the bit rate. Block Outputs: Data Out: In encode mode this signal consists of N input data (systematic) bits followed by M CRC parity bits per block
79
period. In this mode the sampling rate (of the output) is ( N + M ) N times the input sampling rate. In decode mode this signal consists of M systematic bits which were read from the Data Input signal per block period. No error correction is performed. The sampling rate is N ( N + M ) times the input sample rate in decode mode. Error: This output signal is only required in decode mode (it is set to FALSE in encode mode), and is used to indicate that an error has been detected (i.e. a discrepancy exists between the data bits and the parity bits). This signal is TRUE when an error has been detected, and FALSE when no error has been detected in the current data block. The sampling rate is the sample as that of the Data Out signal. Discussion: The CRC block can operate in either Encode or Decode mode. In encode mode the block reads in N bits at a time and generates M parity bits which are appended to the original block to create an output block size of ( M + N ) bits. This is shown in Figure , where { b i } are the input data bits, and { P j } are the calculated parity bits.
block pos: 1 2 N N+1 N+2 M+N
b1
b2
bN
pM pM 1
p1
Figure 5.3.1: Output block structure of CRC encoder.
To produce the M parity bits the N input bits are mapped to the coefficients of a polynomial where TRUE logic levels are represented by the value 1 and FALSE logic levels are represented by the value 0. The first bit is the coefficient of the highest power term, the second bit the coefficient of the second highest power term, and so on as shown below.
N
I( D) =
i=1
bi D
Ni
= b1 D
N1
+ b2 D
N2
+ + bN 1 D + bN
[5.3.1]
80
The resulting polynomial I ( D ) is then multiplied by D M and divided by the generator polynomial specified by the polynomial parameter, using modulo-2 division. The parity bits are the coefficients of the remainder polynomial, R ( D ) .
M
R(D) =
i=1
pi D M i = p1 D
M1
+ p2 D
M2
+ + pM 1 D + pM
[5.3.2]
The number of parity bits is determined by the label of the polynomial which is being used. For example if G CRC 16 ( D ) is used then there are 16 parity bits. Eq. 5.3.3 describes the relationship between the input polynomial, the generator polynomial and the remainder polynomial where Q ( D ) is the quotient of the modulo-2 division operation. The polynomial in Eq. 5.3.4 describes the output of the block in encode mode. R(D) D M I ( D ) - = Q ( D ) + ----------------------------------------------------G CRCM ( D ) G CRCM ( D ) Y( D ) = DMI( D ) + R( D )
[5.3.3]
[5.3.4]
The generator polynomials used in this block are specified in 3G TS 25.212, and are shown below. G CRC 24 ( D ) = D 24 + D 23 + D 6 + D 5 + D + 1 G CRC 16 ( D ) = D 16 + D 12 + D 5 + 1 G CRC 12 ( D ) = D 12 + D 11 + D 3 + D 2 + D + 1 G CRC 8 ( D ) = D 8 + D 7 + D 4 + D 3 + D + 1
[5.3.5] [5.3.6] [5.3.7] [5.3.8]
In decode mode, the CRC block receives ( M + N ) input bits and creates the a polynomial in a similar manner to encode mode but with ( M + N ) coefficients. This polynomial is then divided by the specified CRC polynomial G CRCM using modulo-2 division. If the remainder is zero, no CRC errors have occurred. The error output reflects the state of the CRC check. The output stream consists of the N systematic bits of the received block. No error correction is performed by this block. The block period T b is defined as the time for a N samples to be read at the input in encode mode, or ( M + N ) samples to be read at the input in decode mode. The delay between input and output is equal to the block period irrespective of what mode the block is operating in.
81
Equivalent circuits for encoding and decoding the data are shown below. In both of these the set of coefficients { g i } are derived from the CRC polynomials in Eq. 5.3.5 to 5.3.8. In encode mode the bits are input to the encoder circuit with switch 1 in the closed. After all the bits are fed in switch 1 is open and the parity bits appear sequentially at the output of the circuit.
Initial Values: The shift registers of both the encoder and decoder are initialised to all zeros. The implementation of the CRC encoder/decoder block can be represented by shift registers.
switch 1
g1

g2
gL 1
I(D)
Figure 5.3.2: CRC parity generator.
Y(D)
In decode mode the received bit vector is fed into the error circuit with switch 1 closed and switch 2 open. Once all ( M + N ) bits are fed into the circuit switch 1 is opened and switch 2 closed. If a any TRUE values appear at the output of the circuit then an error has occured. CRC error checker
switch 1
Y(D)
g1

g2
gL 1
error switch 2
Figure 5.3.3: CRC syndrome generator.
In encode mode N input bits are fed into the parity generator with the switch in the closed position. After this the register contains the parity bits which can be shifted out one at a time with the switch in the open position.
82
References: 3G TS 25.212: Multiplexing and channel coding (FDD).
83
5.3.2 Convolutional Encoder Block Name: ConvEnc Abbreviation: ConvEnc
Synopsis: The convolutional encoder block performs segmentation, tail bit insertion and convolutional encoding at rate 1/2 or rate 1/3.
Parameter
Range
Default value
Definition Denoted 1 R . R is the number of function generators. Number of input bits grouped together for encoding. Denoted as M s Input high/low threshold True output voltage False output voltage See section on delay offset. Sets delay offset measurement units. See section on no leading output Defines which version of the 3GPP standard the convolutional encoder should comply with.
Encoding Rate
12
or
13
13
Precoded Block Length (bits) Input Threshold True Output False Output Delay offset Delay in Samples No Leading Output
>1
All All All
260 0 1 -1 0 disabled disabled
0
enable/disable enable/disable {v3.0.0, v3.1.0, v3.2.0, v3.3.0, v3.4.0}
Release Version
v3.4.0
Block Inputs: Data Input: Input stream of systematic data (data to be encoded). The sampling rate of the input is denoted as f s and is interpreted as one sample per bit. Block Outputs: Data Output: Output stream of coded data. The sampling rate of the output is f c with one bit per sample.
84
Discussion: This block implements a constraint length K = 9 , rate 1 2 ( R = 2 )or rate 1 3 ( R = 3 ) convolutional coder. Blocks of M s (systematic) bits are received and processed to generate M c output bits where M c = R ( M s + 8 ) . The steps performed on each block are denoted in Figure 5.3.4: eight tail bits are appended to the block; the block is applied to one of the function generator circuits in Figure 5.3.5; the outputs of the R function generators are multiplexed to form the output of the block. Each encoder produces R functions of the incoming bits and multiplexes them at the output of the block. The following diagram shows the processing steps that a block goes through for rate 1/2 coding, and how the encoded bits are positioned within the output block. y ir is the i th output bit of the r th function generator.
first input bit
b1 b2 b3
first output bit
bM
tail bit insertion
b1 b2 b3
bM 0 0 0 0 0 0 0 0
0 yM +K1 1 yM +K1
convolutional encoding (1/2)

0 y1 y0 y1 y0 y1 y1 1 2 2 3 3
Figure 5.3.4: The steps performed by the convolutional encoders block.
As can be seen the bits of the output block alternate between the output bits of the function generators, starting from the lowest index. This is also the case for the 1 3 convolutional coder, where the output bits appear in the order 0, y 1, y 2, y 0, y 1, y 2, } . The input and output block sizes are therefore related { y1 1 1 2 2 2 by M c = R ( M s + 8 ) . Note that due to internal buffering the encoded data block will start to appear at the output of the coder M s input samples after the first bit of the input data is read. When one data block is being read in, the previous block is being coded and streamed to the output. Initial Values: The shift registers of the convolutional encoders are initialised to all zeros.
85
Block Schematic:
: modulo-2 addition
1/2 convolutional coder

G0 = 561Oct G1 = 753Oct 0 1
1/3 convolutional coder

G0 = 557Oct G1 = 663Oct G2 = 711Oct 0 1 2
Figure 5.3.5: The structure of the convolutional coder function generators.
References: TS 25.212: Multiplexing and channel coding (FDD)
86
5.3.3 Convolutional Decoder (Viterbi Algorithm) Block Name: ConvDec Abbreviation: ConvDec
Synopsis: This block implements a constraint length K = 9 , rate 1 2 ( R = 2 ) or rate 1 3 ( R = 3 ) convolutional coder. Blocks of M s (systematic) bits are received and processed to generate M c output bits where M c = R ( M s + K 1 ) . This block performs decoding of rate 1 2 or rate 1 3 , constraint length K = 9 convolutionally encoded data using the Viterbi Algorithm (VA). Both hard and soft decision modes are implemented. The block also removes the K 1 tail bits inserted by the coder for correct trellis termination. .
Parameter Range Default value Definition Denoted 1 R as R is the number of function generators in the encoder. Block length before coding (i.e. output block size of decoder). Denoted as M s . Determines whether the soft or hard decision Viterbi algorithm is used. Magnitude of signalling levels. Voltage step between adjacent quantisation levels. Number of bits used to represent the soft decisions. Denoted as n Input high/low threshold. True output voltage. False output voltage. See section on delay offset.
Encoding Rate
1 2 or 1 3
13
Precoded Block Length (bits)
>0
260
Decision Type. Signalling Amplitude (v) (soft decision mode only) Quantisation Step (v) (soft decision mode only) Quantisation Bits (soft decision mode only) Input Threshold True Output False Output Delay Offset
Hard/Soft
Hard
>0 >0 18
All All All
0.2
3 0 1 -1 0

Default value disabled disabled
87
Parameter Delay in Samples No Leading Output
Range enable/disable enable/disable {v3.0.0, v3.1.0, v3.2.0, v3.3.0, v3.4.0}
Definition Sets delay offset measurement units. See section on no leading output. Defines which version of the 3GPP standard the convolutional decoder should comply with.
Release Version
v3.4.0
Block Inputs: Data Input: Input stream of coded data. The sampling rate of the input is f c with one sample per bit. Block Outputs: Data Output: Output stream of decoded data. The sampling rate of the output is f s with one sample for each bit. Discussion: This block implements a constraint length K = 9 rate 1/3 convolutional decoder using the standard Viterbi Algorithm (VA). The path depth is the same as the precoded block length, M s . The block reads in blocks of M c received samples, decodes them and then strips the K 1 tail bits. The output block size is given by M s = ( M c R ) K + 1 . The Viterbi algorithm is a computationally efficient method of performing maximal likelihood decoding specifically for convolutional codes. The algorithm works by retracing the all possible sequences of states (paths) that the encoder could have progressed through when it generated the coded block. A metric known as a path matrix is accumulated for each of these. When two paths arrive at the same state then their path matrices are compared and one of them can be disregarded. Once the paths have been traced through the whole block of data, the path matrices are compared and one path is selected is the most likely one which actually occurred at the encoder. In order to generate a path matrix for a particular path, a metric is required to evaluate each branch of the path. The path matrix is defined as the sum of all of the branch metrics for that path. Decoding can be performed in either soft or hard decision mode.
88
In hard decision mode the input to the block is a voltage, which is converted to a bit stream by applying a threshold. Let c jr { 0, 1 } represent the r th bit of the j th symbol (branch) of a possible path. Let y jr { 0, 1 } similarly represent the input bits to the viterbi decoder in hard decision mode, after thresholding. A metric for how close c jr is to y jr is the hamming distance, defined as: j =
cjr yjr
r
[5.3.9]
When this metric is used the path whose path matrix is smallest in value, is most likely to be the correct path. In soft decision mode the input to the viterbi decoder ( y jr ) is quantised to L n different levels where L = 2 and y jr ( 0, 1, 2, L 1 ) . The metric for a particular branch c jr is defined as: j =
yjr ( 2 cjr 1 )
r
[5.3.10]
In soft decoding mode the path with the greatest value of path matrix is most likely to be the correct path.
Initial Values: The decoder is initialised to the zero state before decoding (all paths start from the zero state).
89
References: TS 25.212: Multiplexing and channel coding (FDD)
90
5.3.4 Turbo Encoder Block Name: TurboEnc Abbreviation: TurboEnc
Synopsis: The turbo encoder block performs segmentation, tail bit insertion and rate R 3 convolutional encoding.
Parameter
Range
Default value
Definition Ratio of bits in / bits out for the encoder. Denoted as 1 R Input block length Input high/low threshold True output voltage False output voltage See section on delay offset. Sets delay offset measurement units. See section on no leading output. Defines which version of the 3GPP standard the turbo coder should comply with.
Encoding Rate
13 >0
All All All
13
1296 0 1 -1 0 disabled disabled
Precoded Block Length (bits) Input Threshold True Output False Output Delay Offset Delay in Samples No Leading Output
0
Release Version
v3.4.0
Block Inputs: Data Input: Input stream of coded data. The sampling rate of the input is f s with one sample per bit. Block Outputs: Data Output: Output stream of coded data. The sampling rate of the output is f c with one sample per bit.
91
Discussion: This block implements turbo coding using a Parallel Concatenated Convolutional Coding (PCCC) scheme. The block reads in blocks of M s bits, and produces output blocks of M c coded bits.The input and output block sizes are related by M c = RM s + 12 since 12 tail bits are appended to the output of the encoder to terminate the decoder correctly. Since a block of M c bits is streamed to the output in the same time as M s bits are read at the input, the output sampling rate is f c = ( M f M s ) f s . The encoded data block only begins to appear at the output after the last bit of the corresponding input block has been read. Therefore there is a latency of M s input bits between input and output. The encoding scheme consists of two recursive systematic convolutional encoders (RSC1 and RSC2) and an interleaver. RSC1 encodes the systematic data, and RSC2 encodes an interleaved version of the systematic data. After a block of M s bits have been read into the coder, both the systematic and interleaved data streams begin to be encoded. For every bit which enters the encoder, three bits are output. The output sequence is X ( 0 ), X ( 0 ), Y ( 0 ), X ( 1 ), X ( 1 ), Y ( 1 ) etc. The interleaver generates a matrix whose size depends on the input block size M s . The input data block is read into the matrix row by row, and then both intra-row and inter-row permutation is performed. Intra-row permutation is performed on the j th row according to a number sequence c j ( i ) where the bit in position c j ( i ) of the row is moved to position i . Inter-row permutation is performed (after intra-row permutation) according to the sequence p ( j ) where row p ( j ) is moved to position j . For a precise description of how the interleaver selects the matrix size, and the sequences c j ( i ) and p ( j ) , refer to 3G TS 25.212. After permutation the matrix is read out column by column. The output of the interleaver consists of M s + l bits, where the l extra bits arise because the input block does not fit exactly into the matrix. The l bits which did not exist in the original block are pruned bringing the number of bits back down to M s . The combined delay of the interleaving and the pruning operations is M s bits. Once an entire block has passed through the encoder trellis termination must be performed: the two RSCs must be forced to the all 0 state. For both of the RSCs this is done by applying the feedback from the shift register to the RSC input: putting the input switches in the lower position. The first three tail bits are used to terminate RSC1 (RSC1 input switch in lower position) while RSC2 is disabled. The last three tail bits are used to terminate RSC2 (RSC2 input switch in lower position) while RSC1 is disabled. For trellis termination the bits are then transmitted in the following sequence:
Y ( t ), X ( t + 1 ), Y ( t + 1 ), X ( t + 2 ), Y ( t + 2 ), X ( t ), Y ( t ), X ( t + 1 ), Y ( t + 1 ), X ( t + 2 ), Y
92
Initial Values: The shift registers of the recursive convolutional encoders are initialised to all zeros. Block Schematic:
input block
X(t) RSC1
interleaver

X(t)
output block
RSC2

Y(t) Y(t)
Figure 5.3.6: Turbo Coder.
93
5.3.5 Turbo Decoder Block Name: TurboDec Abbreviation: TurboDec
Synopsis: The Turbo decoder block performs decoding of rate 1 3 PCCC turbocodes using the sub-log MAP (Maximum A Posterior) algorithm.
Parameter Encoding Rate Range Default value Definition Encoder rate Size of block in bits before encoding was performed. Denoted M s . Input high/low threshold True output voltage False output voltage Magnitude of signalling levels. Estimate of the noise variance. Number of decoding iterations performed. Input high/low threshold. True output voltage. False output voltage. See section on delay offset. Sets delay offset measurement units. See section on no leading output. Defines which version of the 3GPP standard the turbo decoder should comply with.
13 >0
All All All 1
13
1296
Precoded Block Length
Input Threshold True Output False Output Signalling Amplitude (v) Noise Variance v2 Decoding Iterations Input Threshold True Output False Output Delay Offset Delay in Samples No Leading Output
0 1 -1
>0
0.001 10 0 1 -1 0 disabled disabled
>0 >0
All All All
0
Release Version
v3.4.0
94
Block Inputs: Data Input: Input stream of data to be decoded at one sample per bit. Sampling frequency is denoted f c Block Outputs: Data Output: Output stream of decoded data. Output sampling frequency is denoted f s input sample rate /[R * ((M+8)/M)] where R is the rate parameter (2 or 3) and M is the input block size (excluding tail bits). Discussion: This block makes use of the sub-log MAP (Maximum A Posterior) algorithm to decode rate 1 3 Block Schematic:
de-interleaver MAP decoder 1 interleaver interleaver
MAP decoder 2
Figure 5.3.7: Turbo Decoder.
95
96
5.3.6 Rate Matcher Block Name: RateMatch

RM
Abbreviation: RateMtch
Synopsis: Implements a rate matching algorithm that punctures or repeats bits to provide an output bit stream at a different rate to the input bit stream.
Parameter
Range Rate Matching/ Rate Recovery
Default value Rate Matching
Definition Selects whether the block performs rate matching (Tx) or rate recovery (Rx). Number of bits in a frame/TTI before rate matching/after rate recovery.
Tx/Rx Frame Before Matching (bits) (uplink mode) TTI Before Matching (bits) (downlink mode) Frame After Matching (bits) (uplink mode) TTI After Matching (bits) (downlink mode) Link Direction
>0
402
>0
490
Number of bits in a frame/TTI after rate matching/before rate recovery. Determines whether uplink or downlink transmission/ reception is being performed. Determines the frame length and therefore the number of frames per TTI. Selects type of channel coding or decoding which will be or has been performed on the data. Selects the type of data which is supplied by the demodulator. Input high/low threshold. True output voltage. False output voltage.
Uplink/Downlink
Uplink
Span (ms) (Uplink mode only)
10,20,40,80
10
Data Coding Type
Conv./Turbo
Conv.
Information Type Input Threshold True Output False Output
Hard/Soft All All All
Hard 0 1 -1

Default value 0 disabled disabled
97
Parameter Delay Offset Delay in Samples No Leading Output
Range
Definition See section on delay offset. Sets delay offset measurement units. See section on no leading output. Defines which version of the 3GPP standard the rate matcher should comply with.
0
Release Version
v3.4.0
Block Inputs: Input Data: Input data stream at rate R1 bits/s with R1*Span bits per Transmission Time Interval (TTI). Block Outputs: Output Data: Output data stream at a rate of R2 bits/s with R2*Span bits per Transmission Time Interval (TTI). Discussion: The rate matcher may be placed before the first stage of interleaving or after it depending on whether the transmission is uplink or downlink. The link parameter therefore selects which algorithm is to be used depending on the stage at which the rate matching is performed. The algorithm applies puncturing and repetition to the input bit stream on a blockby-block basis to match the number of input bits per block to the specified number of output bits per block. This may be either a rate increase or a rate decrease. The rate matching is required because frequently the number of bits per TTI that are output from the channel coder/interleaver does not match that required to fill a radio frame. (The physical channel resource offers a fixed bit rate according to the channel rate onto which the transport channels are mapped.) Furthermore, several transport channels with differing Quality of Service (QoS) requirements may share a physical channel in which case the number of bits allocated to each transport channel in the physical channel mapping must be selected according to the QoS required. The algorithm used to perform rate matching is complex and depends on a number of parameters. For example if turbo coding is performed then the rate matcher must not puncture systematic bits of data. Please refer to the FDD channel coding specification document 25.212 Section 4.2.7 Rate Matching for details of the rate matching algorithm.
98
The Rate Matcher block has a latency of one TTI.
Block Schematic: Parameter Dialog Box: Default parameters shown.
99
5.3.7 Interleaver Block Name: IntLeave Abbreviation: IntLeave
Synopsis: 1st stage or 2nd stage permuting interleaver.
Parameter
Range
Default value Uplink
Definition Determines whether uplink or downlink transmission is being performed. Indicates the position of the interleaver in relation to the transport channel multiplexer. Determines the TTI and therefore the number of frames per TTI. Number of bits per TTI. For 1st Interleaver this is the number of bits per column. For second interleaver this is the entire block size to be interleaved. Denoted M . Selects the type of data which is supplied by the demodulator. Input high/low threshold. True output voltage. False output voltage. See section on delay offset. Sets delay offset measurement units. See section on no leading output.
Link Direction
Uplink/Downlink
Position
First/Second
First
Span (ms) (First position only)
10, 20, 40, 80
20
TTI Block Length (bits) (in Uplink this is before radio frame equalisation)
>0
804
Information Type. Input Threshold True Output False Output Delay Offset Delay in Samples No Leading Output
Hard 0 1 -1 0 disabled disabled
0
enable/disable enable/disable
100
Block Inputs: Data Input: Input data stream. Block Outputs: Data Output: Output (interleaved) data stream. Discussion: The interleaver block performs 1st and 2nd interleaving for both the uplink and the downlink. The operation of each is highlighted below. 1st Interleaver The 1st Interleaver is a block interleaver with inter-column permutations. Data is read input data into a rectangular matrix row by row (see Eq. 5.3.11) The columns of the matrix are then re-arranged depending on the number of frames per TTI and then read out column by column. Each column represents one TTI worth of data. Therefore the number of columns C is set to the number of frames per TTI (1,2,4 or 8). The columns are re-arranged according to one of the permutation patterns P 1 C ( j ) shown in Table 5.3.1. P 1 C ( j ) is the original position of the j th permuted column. Note that the entire block size of the 1st Interleaver is M C and not just M .
TTI (ms) 10 20 40 80 Number of Columns 1 2 4 8 Inter-column permutation patterns
{ P 1C ( 0 ) , , P 1C ( C 1 ) }
{0} {0,1} {0,2,1,3} {0,4,2,6,1,5,3,7}
Table 5.3.1:Permutation patterns for first interleaver.
x1 xC + 1
x2 xC + 2
x3 xC + 3
xC x2 C x RC
[5.3.11]
x( R 1 ) C + 1 x( R 1 )C + 2 x( R 1 ) C + 3
2nd Interleaver The second interleaver operates on the output of the transport channel multiplexer and has a fixed span of 10 ms or 1 frame. The incoming data is read into a rectangular array as shown by Eq. 5.3.11 but with the number of columns C fixed to 30. The number of rows R is chosen as the minimum integer such that M RC . Since the size of the input block is not necessarily a multiple of 30, the matrix may contain a number of bits ( K ) which were not in the original block. If M is the block size then RC = M + K .
101
For the second interleaver there is only one inter-column permutation pattern as shown in Table 5.3.2.
Number of Columns 30 Inter-column permutation patterns
{ P 2C ( 0 ) , , P 2C ( C 1 ) }
{0,20,10,5,15,25,3,13,23,8,18,28,1,11,21,6, 16,26,4,14,24,19,9,29,12,2,7,22,27,17}
Table 5.3.2:Permutation pattern for second interleaver
After the inter-column permutations have been performed the block is read out of the matrix column by column. The K bits which did not exist in the original block are pruned so that the input and output block sizes are the same. Block Schematic: Parameter Dialog Box: Default parameters shown.
102
5.3.8 De-Interleaver (DeIntLeave) Block Name: DeIntLeave Abbreviation: DeIntLev
Synopsis: 1st stage or 2nd stage permuting de-interleaver. Performs the inverse of the interleaver block (see Section 5.3.7).
Parameter Range Default value Uplink Definition Determines whether uplink or downlink reception is being performed. Indicates whether deinterleaving of the CCTrCh or individual transport channels is being performed. Determines the TTI and therefore the number of frames per TTI. Number of bits in the block to be interleaved. Each block is one TTI of data. Selects the type of data which is supplied by the demodulator. Input high/low threshold. True output voltage. False output voltage. See section on delay offset. Sets delay offset measurement units. See section on no leading output.
Link Direction
Uplink/Downlink
Position
First/Second
First
Span (ms) (First position only) TTI Block Length (bits) (in Uplink this is before radio frame de-equalisation) Information Type. Input Threshold True Output False Output Delay Offset Delay in Samples No Leading Output
10,20,40,80
20
>0
804
Hard 0 1 -1 0 disabled disabled
0
Block Inputs: Data Input: Input data stream.
103
Block Outputs: Data Output: Output data stream. Discussion: The De-Interleaver block performs the inverse of the Interleaver function which is described in Section 5.3.7. The following steps are taken to achieve this: construct a matrix in the same way as the Interleaver block; read the data block into the matrix column by column; invert the permutation operation performed by the interleaver; read the data from the matrix row by row; perform any running which may be required (bits added to fill the matrix). The output block size of de-interleaver is the same as the input block size. There is a latency of one block. Parameter Dialog Box: Default parameters shown.
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5.3.9 Transport Channel Coder Block Name: TrChCoder

CODEC
CH
Abbreviation: TrChCdr
Synopsis: This block performs all of the transport channel coding/decoding in one block.
Parameter
Range
Default value Encode
Definition Determines whether block performs encoding or decoding. Determines whether the soft or hard decision Viterbi algorithm is used. Number of bits used to represent the soft decisions.
Tx/Rx
Encoder/Decode
Decision Type (conv. decode mode only) Quantisation Bits (soft decision conv. decode mode only) Quantisation Step (v) (soft decision conv. decode mode only) Decoding Iterations (turbo decode mode only) Noise Variance v2 (turbo decode mode only) Signalling Amplitude (v) (soft decision conv. decode and turbo decode modes only)
Hard/Soft
Hard
18
>0 >0 >0
0.2
Voltage step between adjacent quantisation levels. Number of decoding iterations performed. Estimate of the noise variance.
10
0.001
>0
Magnitude of signalling levels.
Bearer Service (kbps)
User Defined, 12.2, 64, 144, 384, 2048, BCH coding
User Defined
When set to user defined, user selects channel coding parameters. If a specific bit rate is selected then the channel coding parameters are set automatically. Selects uplink or downlink channel coding.
Link direction.
Uplink/Downlink
Uplink

Default value 20
105
Parameter TTI (Transmission Time Interval) (ms) Info Block Length/TTI
Range
Definition Determines the TTI and therefore the number of frames per TTI. Number of raw information bits per TTI.
10,20,40,80
>0
No Channel Coding, Rate 1 2 Conv. Rate 1 3 Conv. Rate 1 3 Turbo No CRC 8 bit, 12 bit, 16 bit, 24 bit
244
Channel Coding
Rate 1 3 Conv.
Determines the type of channel coding / decoding used.
CRC Coding
16 bit
Number of CRC bits appended to the transport channel block. Number of bits per frame before rate matching /after rate recovery. Number of bits per frame after rate matching / before rate recovery. Number of bits per TTI before rate matching / after rate recovery. Number of bits per TTI after rate matching / before rate recovery. Enables disregarding of frames to enable synchronisation when one TTI is not equal to one frame. Input high/low threshold. True output voltage. False output voltage. See section on delay offset. Sets delay offset measurement units. See section on no leading output.
TrCh bits/Frame (uplink mode only) PhyCh bits/Frame (uplink mode only) TrCh bits/TTI (downlink mode only) PhyCh bits/Frame (downlink mode only)
>0
402
>0
490
>0
402
>0
490
Re-sync frames on CRC error
enable/disable
disable
Input Threshold True Output False Output Delay Offset Delay in Samples No Leading Output
All All All
0 1 -1 0 disabled disabled
0

Default value v3.4.0
106
Parameter
Range {v3.0.0, v3.1.0, v3.2.0, v3.3.0, v3.4.0}
Definition Defines which version of the 3GPP standard the channel coder should comply with.
Release Version
Block Inputs: Input Data: Uncoded transport channel data. Block Outputs: Output Data: Coded transport channel. Discussion: This block performs all of the channel encoding/decoding required for a single transport channel in both the uplink and the downlink. Table 5.3.3 lists all of the functions performed by this block and which sections of this manual should be referred to for more detailed information about each.
Function Cyclic Redundancy Check Encoding Cyclic Redundancy Check Decoding Turbo Encoding Turbo Decoding Convolutional Encoding Convolutional Decoding Rate Matching Rate Recovery 1st Interleaving 1st De-Interleaving Reference Section 5.3.1 Section 5.3.1 Section 5.3.4 Section 5.3.5 Section 5.3.2 Section 5.3.3 Section 5.3.6 Section 5.3.6 Section 5.3.7 Section 5.3.8
Table 5.3.3:Functions performed by the Transport Channel Coder
The block schematic shows how the block operates in downlink mode. For uplink the positions of the rate matcher and interleaver are swapped. When the coder has been configured in encode mode, the decoder can be generated by simply duplicating the block and setting the it to decode mode. A number of bearer services are provided which when enabled, perform automatic configuration of the channel coding parameters. Broadcast Channel (BCH) coding provides the BCH specific coding parameters.
107
The block supports DTX on the Downlink. In the transmitt direction, the rate matching is performed from Before value to After-DTX Portion value. In the Downlink receive direction, the DTX Portion value is ignored and the ratematching is performed from the Before value to the After value. In the Uplink, the DTX Portion parameter is disabled. Initial Values: Initial values of the various functions can be found in the relevant sections.
108
Block Schematic:
Transmitter - encode mode Data In CRC attachment Convolutional Coding Turbo Coding Receiver - decode mode Data In 1st De-Interleaving
Rate Recovery Convolutional decoding (Viterbi) Turbo Coding
Rate Matching 1st Interleaving CRC decoder
Data Out
Data Out
CRC Error
Figure 5.3.8: Transport Channel Coder Functions (Downlink)
109
References: 3G TS 25.212: Multiplexing and channel coding (FDD)
110
5.3.10 Transport Channel Multiplexer Block Name: TrChMux Abbreviation: TrChMux
Synopsis: Multiplexes up to twenty transport or logical channel bit streams into one radio frame or Transmission Time Interval (TTI) respectively.
Parameter
Range For transport channel multiplexing: 10ms For logical channel multiplexing: 10ms, 20ms, 40ms, 80ms enable/disable
Default value
Definition
Multiplexing Frame Length (ms)
10ms
Transmission Time Interval (TTI)
Transport Channel Multiplex
enable
Enables the multiplexing of transport channels into a 10ms radio frame Enables the multiplexing of logical channels into a transport channel Input high/low threshold True output voltage False output voltage See section on leading output
Logical Channel Multiplex Input Threshold True Output False Output No Leading Output
enable/disable All All All Enable/Disable
disable 0 1 -1 Disabled
Block Inputs: Up to 20 inputs, assigned in order of connection. Each must be sampled at one sample per bit. Block Outputs: Output: Multiplexer output. The sample rate depends upon how many input channels are used and what their individual
111
sample rates are. Discussion: This block implements a multiplexer which can be used primarily in two situations in the FDD context. First, it can be used to multiplex various logical channels (e.g. DTCH, DCCH etc.) into a transport channel (e.g. a dedicated transport channel DCH) before channel coding and interleaving as shown in Figure 5.3.9. In this case, it is possible to choose the transmission time interval (TTI) between the values 10 ms, 20 ms, 40 ms and 80 ms. The second use of this block is to multiplex up to 20 transport channels into a radio frame after channel coding. The TTI must not be confused with the radio frame length of 10 ms. The TTI dictates the size of block over which channel coding takes place and the depth of the interleaving. The mapping from transport channels to physical channels splits the transport channel up into radio frames.
Logical Ch 1 Logical Ch 2
Logical Ch 1
Logical Ch 1 Logical Ch 2 Logical Ch 1 Logical Ch 2 Logical Ch n
Logical Ch 2
Logical Ch n TTI size
Logical Ch n TTI size TTI size TTI size
Figure 5.3.9: Multiplexing of logical channels into a transport channel.
Logical Ch n
112
Tr Ch 3 Tr Ch 2 Tr Ch 1 0ms
Tr Ch 3 Tr Ch 2 Tr Ch 1 10ms
Tr Ch 3 Tr Ch 2 Tr Ch 1 20ms 30ms
Tr Ch 1
Tr Ch 2
Tr Ch 3
Tr Ch 1
Tr Ch 2
Tr Ch 3
Tr Ch 1
Tr Ch 2
Tr Ch 3
to channel coding/interleaving
0ms
10ms
20ms
30ms
Figure 5.3.10: Multiplexing of 3 transport channels into a radio frame.
The transport channel multiplexer block time-multiplexes up to 20 bit streams with differing sample rates into one 10ms radio frame. This process is illustrated in Figure 5.3.10. If the input sampling rates are R 1 Hz, R 2 Hz, ..., R 20 Hz, the output sampling rate will be R out = R 1 + R 2 + + R 20 .
113
114
5.4
Channel Generators
The library provides two integrated blocks which provide a complete uplink/ downlink including all logical channels, transport channels, channel coding, rate matching, pulse shaping and modulation stages. The blocks also provides test points in order that the designer can view the output of some internal stages of the block. The blocks are:
UL
DPCH GEN
Uplink Generator (ULGen)
DL
DPCH GEN
Downlink Generator (DLGen)
An integrated block for High Speed Downlink Packet Access channel generation is also provided. This block produces a coded HS-DSCH channel output (on an appropriate set of HS-PDSCH and HS-SCCH physical channels) according to a subframe schedule specified via an XML configuration file.
HSDPA
HSDPA Transmission Generator (HSDPA)
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5.4.1 Uplink Generator

UL
Block Name: UplinkGen Abbreviation: ULGen
DPCH GEN
Synopsis: This block generates a complete uplink including all channel coding, spreading/channelisation, rate matching and data framing, RRC filtering and final I/Q modulation onto a carrier.
Parameter
Range
Default value
Definition Enables or disables channel coding on the DTCH source. If disabled, the source is transmitted as transport data uncoded. Specifies the source for the data in the DTCH channel. Selects a particular DTCH service rate. Once selected, every other relevant parameter initialises automatically. Selects the basic channel coding method to use for the DTCH channel coding. The length of a TTI in msec for use in interleaving when channel coding. The number of bits per TTI before channel coding. The number of transport blocks per TTI to be coded. The number of CRC bits to add when channel coding. The number of bits per TTI at the input to the rate matcher
DTCH Source: Enable channel coding
Enable/Disable
Enabled
DTCH Source: Information Source
{PN9, PN15, File...}
PN15
DTCH Source: Bearer Service
{12.2 kbps, 64 kbps, 144 kbps, 384 kbps, 2048 kbps} {Uncoded, Rate 1/2 conv, Rate 1/3 conv, Rate 1/2 turbo, Rate 1/3 turbo} {10ms, 20ms, 40ms, 80ms}
12.2 kbps
DTCH Source: Channel Coding
Rate 1/3 conv.
DTCH Source: TTI DTCH Source: Tr Block Size DTCH Source: num. Tr Blocks DTCH Source: CRC DTCH Source: Rate Matcher Nc
20ms
1 1
{0, 8, 12, 16, 24}
244 bits 1 16 bits
402

Default value 490
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Parameter DTCH Source: Rate Matcher Ni DCCH Source: Enable
Range
Definition The number of bits per TTI at the output of the rate matcher If enabled, the DPCH will include a DCCH. Has the same options as each of the sections outlined for the DTCH Source. The channel bit-rate used for the Dedicated Physical Data Channel (DPDCH). The channelisation code use for the physical data channel The channel bit-rate used for the Dedicated Physical Control Channel (DPCCH). The channelisation code use for the physical control channel. The number of DPCH channels transmitted. When a 2048kbps reference service is selected, multicode transmission with 6 DPCH channels is used. The relative DPDCH gain The relative DPCCH gain The particular DPCCH slot format to use. Specifies the arrangement of pilot bits, TFCI, FBI and TPC fields. Enable/Disable the HSDPCCH Specifies the configuration settings for HS-DPCCH
Enable/Disable
Enabled
DCCH Source
-{15 kbps, 30 kbps, 60 kbps, 120 kbps, 240 kbps, 480 kbps, 960 kbps} {0.. (spreading factor1)}
--
Physical Channel: DPDCH rate
60 kbps
Physical Channel: DPDCH Ch. Physical Channel: DPCCH rate Physical Channel: DPCCH Ch.
16
fixed: 15 kbps
15 kbps
{0..511}
Physical Channel: No. DPCH
Fixed: 6 for 2048 kbps service, 1 elsewhere
Physical Channel: DPDCH gain Physical Channel: DPCCH gain Physical Channel: DPCCH slot format
{0,1/15,2/15,...15/15} {0,1/15,2/15,...15/15}
15/15 11/15
{0,1,2,3,4,5}
HS-DPCCH: Enable HS-DPCCH: Configuration
Enable/Disable --
Disabled --

Default value Internal PN9 sequenc e 0
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Parameter HS-DPCCH Configuration: HARQ-ACK: Indicator Source HS-DPCCH Configuration: HARQ-ACK: ACK Gain HS-DPCCH Configuration: HARQ-ACK: NACK Gain HS-DPCCH Configuration: CQI: Indicator Source
Range
Definition
Internal - PN9, PN15, External file
Specifies the source for the HARQ-ACK Indicator data.
--
Specifies the linear gain of the HS-DPCCH ACK. Specifies the linear gain of the HS-DPCCH NACK Specifies the source for the Channel Quality Indicator data.
--
0 Internal PN9 Sequenc e Internal PN9 Sequenc e
Internal - PN9, PN15, External file
HS-DPCCH Configuration: CQI: CQI Gain
--
Specifies the linear gain of the HS-DPCCH CQI
HS-DPCCH Configuration Frame Timing
--
Specify the Frame delay in terms of integer multiples of 256 chips as the HSDPCCH sub-frame starts m*256 chips after the start of an uplink DPCH frame that corresponds to the DL DPCH or F-DPCH frame from the HS-DSCH serving cell containing the beginning of the related HS-PDSCH subframe. Which scrambling code to use for this particular uplink generator. If enabled, the scrambler will use short scrambling codes rather than long scrambling codes. If enabled, an oversampled output will be pulse-shaped. If disabled, square pulses will be used.
Scrambling: Scr. Code
{0..38400} or {0..255} for short code
10
Scrambling: Short Code
Enable/Disable
Disabled
Oversampling and Filtering: Enable Filter
Enable/Disable
Enabled

Default value
118
Parameter
Range
Definition If enabled, the default internal pulse-shaping filter will be used. If disabled, the pulse-shaping filter given by the coefficient file parameter will be used. When a filename is specified, this coefficient file is used as the pulse shaping filter. Specifies the number of samples per chip at the output. Shows the number of taps of the user-defined pulse shaping filter. Carrier frequency for carrier modulation of the uplink output. Gives the absolute output level of the combination of all enabled channels.
Oversampling and Filtering: Default Filter
Enable/Disable
Enabled
Oversampling and Filtering:: Coefficient file Oversampling and Filtering: Oversampling Ratio Oversampling and Filtering: No. of Taps Modulator: Carrier Frequency
a valid coefficient filename
blank
--
blank
0
Units: {dBm 50R, dBm 1R, dBW 50R, dBu, Vpk, Vrms} {DPCH, Spread DPCH, Scrambled DPCH, DTCH CRC insertion, DTCH channel coder, DTCH 1st interleaver, DTCH rate matcher, DCH 2nd interleaver, DCCH CRC insertion, DCCH channel coder, DCCH 1st interleaver, DCCH rate matcher} {v3.0.0, v3.1.0, v3.2.0, v3.3.0, v3.4.0}
0.0
Modulator: Output Level
1.0 Vpk
Test Point 1
DPCH
Specifies what data will be available on the TP (Real) and TP (Imag) output ports.
Release Version
v3.4.0
Defines which version of the 3GPP standard the uplink should comply with.
Block Inputs: TPC: Data on this input is multiplexed into the TPC field in the DPCCH. TFCI: Data on this input is multiplexed into the TFCI field in the DPCCH. Reset:
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Block Outputs: Real: Real part of output value. Imag: Imaginary part of output value. TP (Real): Real part of the value of the signal specified in the Test Point 1 parameter. TP (Imag): Imaginary part of the value of the signal specified in the Test Point 1 parameter. Slot Number: Output indicating the current slot that is being transmitted. DTCH Info: The Dedicated Transport Channel data that is being transmitted. DCCH Info: The Dedicated Control Channel data that is being transmitted. Discussion: This block performs a complete standard compliant 3GPP uplink. A Dedicated Data Channel (DDCH) and a Dedicated Control Channel (DCCH) are either generated internally or read from external files. These two transport channels are then subject to transport channel coding followed by transport channel multiplexing and second interleaving. The result is referred to a Dedicated Physical Data Channel (DPDCH). A Dedicated Physical Control Channel (DPCCH) is also generated internally. The TPC and TFCI fields can be supplied as block inputs. The coded DPDCH and DPCCH are both channelised and weighted according to the relevant dialogue parameters. Note that the spreading factors may be different due to the difference in data rates. A complex signal is then generated with DPDCH as the real part and DPCCH as the imaginary part and scrambled using either long or short uplink codes. The block also contains optional pulse shaping and modulation. A default root raised cosine filter is available or alternatively the coefficients can be read from a file. In order to DTX an HS-DPCCH, we need to set the Channel Quality Indicator and the HARQ ACK/NACK values to -1.
120
Parameter Dialog Box:
121
References:
122
5.4.2 Downlink Generator

DL
Block Name: DownlinkGen Abbreviation: DLGen
DPCH GEN
Synopsis: This block generates a complete downlink including all channel coding, spreading/channelisation, rate matching and data framing, RRC filtering and final I/Q modulation onto a carrier.
Parameter on Dedicated ch tab
Range
Default value
Definition If enabled, Transport channel coding (CRC, turbo, rate match etc.) will be performed on the DTCH and DCCH channels. If enabled, the Coded Composite Transport Channel (CCTrCH) will include the DCCH. Selects a particular DTCH service rate. Once selected, every other parameter on this tab initialises automatically. Selects the source data to be coded into the DTCH. Can be one of two pseudorandom number generators, or an external file. The number of bits per TTI before channel coding. The number of CRC bits to add when channel coding. The basic channel coding method to use when channel coding. The length of a TTI in ms for use in interleaving when channel coding.
Enable DTCH & DCCH Transport coding
True/False
True
CCTrCH Multiplexing (enable DCCH)
True/False
True
DTCH Reference Services
{12.2 kbps, 64 kbps, 144 kbps, 384 kbps}
12.2 kbps
DTCH Full Transport Format: Source
{PN 9, PN 15, file...}
PN 15
DTCH Full Transport Format: Block Set DTCH Full Transport Format: CRC DTCH Full Transport Format: Coding DTCH Full Transport Format: TTI
1
{0, 8, 12, 16, 24} {Uncoded, Turbo Rate 1/ 3, Conv Rate 1/2, Conv Rate 1/3} {10ms, 20ms, 40ms, 80ms}
1 x 244 bits 16 bits Conv Rate 1/3
20ms

Parameter on Dedicated ch tab DTCH Full Transport Format: Rate Matching: Rate Default value 85.6%
123
Range A percentage between 50% and 150% defined by the slider
Definition The rate matching factor used when channel coding. The rate matching parameters specified in terms of the block length after rate matching, before rate matching and DTX Portion. Has the same options as each of the sections outlined for the DTCH Full Transport Format. The data rate used in the physical channel. This is the twice the channel symbol rate. The channelisation code used for the physical channel The scrambling code used for the physical channel Timing offset for the start of the frame. The frame edge will be delayed by this offset. Specifies how many channels to use in multi-code transmission. Channels are assigned consecutively from the code given in the Ch Code parameter. Specifies the power offset of the DPCCH within the physical channel. The number of pilot bits to add into the physical channel.
DTCH Full Transport Format : Rate Matching : TTI Length
TTI block lengths before and after matching
Before: 804 After:686 DTX Portion: 0
DCCH Full Transport Format
--
--
Physical Ch Slot Format: Ch Rate Physical Ch Slot Format: Ch Code Physical Ch Slot Format: Scramble Code Physical Ch Slot Format: Frame Offset
{15 kbps, 30 kbps, 60 kbps, 120 kbps, 240 kbps, 480 kbps, 960 kbps, 1920 kbps} {0.. (spreading factor-1)}
60 kbps
16
{0..15}
0 offset < 38400
Physical Ch Slot Format: Multicode Ch#
{1..6}
Physical Ch Slot Format: DPCCH Offset Physical Ch Slot Format: Pilot Bits
All
0dB
{4,8}

Parameter on Dedicated ch tab Default value
124
Range
Definition If enabled, the TFCI (Transport Format Combination Indicator) specified on the TFCI input will be multiplexed into the physical channel slot format.
Physical Ch Slot Format: Enable TFCI
True/False
True
Parameter on Common ch tab STTD check boxes
Range
Default value Disabled
Definition Enables Space Time Transmit Diversity for each of the individual channels. The channel bit rate used for the P-CCPCH and P-SCH channels. The channelisation code used for the P-CCPCH and P-SCH channels. The scrambling code used for the P-CCPCH and PSCH channels. Timing offset for the start of the frame. The frame edge will be delayed by this offset. Specifies the source of the data in the P-CCPCH and PSCH channels. If enabled, the Broadcast Channel (BCH) within the PCCPCH will be transport coded. Otherwise the BCH contains zeros If enabled, the Time Switched Transmit Diversity (TSTD) scheme for the synchronisation channels is used.
Enable/Disable
P-CCPCH / SCH Ch Rate
fixed: 30 kbps
30 kbps
P-CCPCH / SCH Ch Code
fixed: 1
P-CCPCH / SCH Scramble Code P-CCPCH / SCH Frame Offset
fixed: 0
fixed: 0
P-CCPCH / SCH Source
PN9
P-CCPCH / SCH Ref BCH Coding
Enable/Disable
Disable
P-CCPCH / SCH TSTD SCH Diversity
Enable/Disable
Disable

Parameter on Common ch tab Default value
125
Range {30 kbps, 60 kbps, 120 kbps, 240 kbps, 480 kbps, 960 kbps, 1920 kbps} {0..255}
Definition
S-CCPCH Ch Rate
30 kbps
The channel bit rate used for the S-CCPCH channel.
S-CCPCH Ch Code
120
The channelisation code used for the S-CCPCH channel. The scrambling code used for the S-CCPCH channel. Timing offset for the start of the frame. The frame edge will be delayed by this offset. Specifies the source of the data in the S-CCPCH. Enables or disables the presence of Transport Format Combination indicators in the S-CCPCH. Enables or disables the presence of Pilot bits in the S-CCPCH. Specifies the power offset of the PCCH within this channel. The channel bit rate used for the P-CPICH channel. The channelisation code used for the P-CPICH channel. The scrambling code used for the P-CPICH channel. Timing offset for the start of the frame. The frame edge will be delayed by this offset. The channel bit rate used for the S-CPICH channel. The channelisation code used for the S-CPICH channel.
S-CCPCH Scramble Code
{0..15}
S-CCPCH Frame Offset
0 offset < 38400
512
S-CCPCH Source
PN9
S-CCPCH Enable TFCI
Enable/Disable
Disable
S-CCPCH Enable Pilot
Enable/Disable
Disable
S-CCPCH PCCH Offset
All
0dB
P-CPICH Ch Rate
fixed: 30 kbps
30 kbps
P-CPICH Ch Code
fixed: 0
P-CPICH Scramble Code
fixed: 0
P-CPICH Frame Offset
fixed: 0
S-CPICH Ch Rate
fixed: 30 kbps
30 kbps
S-CPICH Ch Code
{0..255}
10

Parameter on Common ch tab S-CPICH Scramble Code Default value 0
126
Range {0..15}
Definition The scrambling code used for the S-CPICH channel. Timing offset for the start of the frame. The frame edge will be delayed by this offset. The channel bit rate used for the PICH channel. The channelisation code used for the PICH channel. The scrambling code used for the PICH channel. Timing offset for the start of the frame. The frame edge will be delayed by this offset. Specifies the source of the paging indication sequence. The number of paging indications which should be generated per frame.
S-CPICH Frame Offset
fixed: 0
PICH Ch Rate PICH Ch Code PICH Scramble Code
fixed: 30 kbps {0..255} {0..15}
30 kbps 0 0
PICH Frame Offset
0 offset < 38400

fixed sequence of length 18 {18, 36, 72, 144}
PICH Source
--
PICH PI per frame
18
Parameter on General Settings tab Primary Code Group
Range
Default value 0
Definition Specifies the Scrambling Code Group for this downlink generator Specifies the Primary Scrambling Code for this downlink generator Equal to (128 x (Primary Code Group)) + (16 x (Primary Code Number)) Carrier frequency for carrier modulation of the downlink output.
{0..63}
Primary Code Number
{0..7}
Absolute Code Number
{0..8176}
Carrier Frequency
0.0

Parameter on General Settings tab Default value
127
Range Units: {dBm 50R, dBm 1R, dBW 50R, dBu, Vpk, Vrms}
Definition Gives the absolute output level of the combination of all enabled channels. Only valid when Normalise Output is enabled. If enabled, a pulse shaping filter will be used, otherwise square pulses are generated by oversampling. Specifies the number of samples per chip at the output. If enabled, the pulse shaping filter will use its internal default coefficients. When a filename is specified, this coefficient file is used as the pulse shaping filter. When Enabled, will generate an output with peak level given by the Output Level parameter. Allows the enabling and disabling of the Primary Synchronisation Channel, and specification of its power level. Allows the enabling and disabling of the Secondary Synchronisation Channel, and specification of its power level. Allows the enabling and disabling of the Page Indication Channel, and specification of its power level. Allows the enabling and disabling of the Primary Common Pilot Channel, and specification of its power level.
Output Level
1.0 Vpk (inactive)
Oversampling & Filtering (enable filter)
Enable/Disable
Enabled
Oversampling Ratio
Default Coefficients
Enable/Disable
Enabled
File...
a valid coefficient filename
inactive
Normalise Output
Enable/Disable
Disabled
P-SCH
Enable/Disable, and power in dBm
Disabled, (0dBm)
S-SCH
Disabled, (0dBm)
PICH
Disabled, (0dBm)
P-CPICH
Disabled, (0dBm)

Parameter on General Settings tab Default value
128
Range
Definition Allows the enabling and disabling of the Secondary Common Pilot Channel, and specification of its power level. Allows the enabling and disabling of the Dedicated Physical Channel, and specification of its power level. Allows the enabling and disabling of the Primary Common Control Physical Channel, and specification of its power level. Allows the enabling and disabling of the Secondary Common Control Physical Channel, and specification of its power level. Allows the enabling and disabling of the Multiple User Model, and specification of its power level. Defines which version of the 3GPP standard the downlink should comply with. Activates the STTD check boxes on the Common ch tab.
S-CPICH
Disabled, (0dBm)
DPCH
Enabled, 0dBm
P-CCPCH
Disabled, (0dBm)
S-CCPCH
Disabled, (0dBm)
MUM
Enable/Disable, and power in dBm {v3.0.0, v3.1.0, v3.2.0, v3.3.0, v3.4.0} Enable/Disable
Disabled, (0dBm)
Release Version
v3.4.0
Downlink Diversity Enabled
Enabled
Multiple User parameter tab: The Multiple User Model (MUM) feature allows the creation of a set of users which will act as interference to the desired users configured in the Dedicated Ch parameter tab. By default, no multiple user model is defined. To enable a multiple user model, right-click in the MUM system area, and select either New System to define a new MUM system, or choose Load system... to load a previously defined and saved MUM. Once New System is selected, a row representing a single user appears in the upper list. To modify the parameters for this user, use the lower edit box area. Some parameters (Enabled, Ch. Rate, Diversity, DPCH #) are modified by right-clicking on their value and choosing from the list of valid values which appears. The other
129
parameters are modified by editing the value directly. To add further users, highlight a user in the MUM system area, right-click and select Copy User. Then right-click again and select Paste After User. To delete a particular user, select the user, then right-click and select Delete User(s). Multiple users can be simultaneously deleted by holding the control key and left-clicking on each user to delete, then deleting by right-clicking and selecting Delete User(s). Once the system is completed (by adding all the users needed and suitably parameterising them), the Save system as right-click option can be used. The user will be prompted for the name and location of the file in which to save the multiple user model definition.
Block Inputs: TPC: Data on this input is multiplexed into the TPC field in the DPCCH. TFCI: Data on this input is multiplexed into the TFCI field in the DPCCH. S-CCPCH: This input enables and disables the S-CCPCH channel. If the input is greater than or equal to zero, the S-CCPCH is enabled. Block Outputs: ANT1 Real: Real part of output value for Antenna 1. ANT1 Imag: Imaginary part of output value for Antenna 1. ANT2 Real: Real part of output value for Antenna 2. ANT2 Imag: Imaginary part of output value for Antenna 2. DTCH Data: The Dedicated Transport Channel data that is being transmitted. DCCH Data: The Dedicated Control Channel data that is being transmitted. BCH Data: The Broadcast Channel data that is being transmitted. Discussion: This block performs a complete standard compliant 3GPP downlink. The block can generate Primary and Secondary Synchronisation Channels (P-SCH and S-SCH), Primary and Secondary Common Pilot Channels (P-CPICH and SCPICH), the Paging Indication Channel (PICH), and the Primary and Secondary Common Control Physical Channels (P-CCPCH and S-CCPCH). Multiple user interference can also be created using the Multiple User Model (MUM) feature. For these channels, all the important parameters can be varied. These parameters are described in the tables for the Common Ch and General Settings parameter tabs. The main focus of the block is the generation of the Dedicated Physical Channel (DPCH). The parameterisation for this channel is extensive, allowing full specification of the transport channel coding to be applied. The parameters for this channel are described in table for the Dedicated Ch parameter tab. Once all the desired channels are configured, the General Settings tab uses simple on/off
130
enable switches to specify which channels are to be generated, and the absolute levels of the channels can be specified in dBm. The option exists to enable antenna diversity, which will generate appropriate outputs for a pair of antennas. The selected combination of channels can also be modulated onto a carrier of specified frequency, and of a specified amplitude if desired, with suitable pulse shape filtering. The block supports DTX on the Downlink. In the transmitt direction, the rate matching is performed from Before value to After-DTX Portion value. Parameter Dialog Box: Default parameters shown.
131
132
133
References:
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5.4.3 HSDPA Transmission Generator Block Name: HighSpeedDownlinkPacketAccessTransmission

HSDPA
Abbreviation: HSDPA
Synopsis: This block produces a coded HS-DSCH channel output (on an appropriate set of HS-PDSCH and HS-SCCH physical channels) according to a subframe schedule specified via an XML configuration file. Parameters:
Parameter Range Any accessible XML file containing a valid configuration Default value Definition The filename of the XML file containing the subframe configuration to use.
Subframe Sequence Configuration File
HSDPAFrames.xml
XML Configuration File Format:

Element: HSDPAConfiguration
Element/Attribute ScramblingCodeNumber Range 0...38399 Definition The physical scrambling code with which to scramble HS-PDSCH and HS-SCCH channels. Value in chips specifiying the start time offset of the HS-PDSCH channel. Value in chips specifiying the start time offset of the HS-SCCH channel. The channelisation code for the HS-SCCH channel.
HSDSCHFrameOffset
0...38399
HSSCCHFrameOffset
0...38399
HSSCCHChannelNumber SourceType, SourceValue SubframeSequence
0...127
See section on Source Configuration. must occur only once Specifies a sequence of SubFrame elements to be used in turn for transmission configuration.
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Element: SubframeSequence
Element SubFrame Range must appear once, can appear many times Definition Specifies the modulation and coding parameters for this particular subframe.
Element: SubFramea
Attribute CodeGroup Range 1...16 Definition Number of channelisation codes used simultaneously for HSPDSCHs. Offset to the first channelisation code to use for HS-PDSCHs. Type of modulation used in transmission of this subframe. Size of transport block at input to channel coding. A transport block size of -1 will result in DTX of the current subframe Transport Block Size information
CodeOffset ModulationType
0...(15-CodeGroup+1) {QPSK,16QAM}
TransportBlockSize
0...163840 or -1
TransportBlockSizeID HARQProcessID SystematicPriority RedundancyVersion
0...63 0...7 {0,1} {0,1}
( x tbs )
Hybrid-ARQ process information
( x hap ) s r
Parameter Parameter
for RV coding. for RV coding.
ConstellationVersion
0...3
Parameter b for RV coding. Specifies constellation rearrangement for 16QAM constellation. Size of the virtual IR buffer. New Data Indicator UE identitfier
VirtualBufferCapacity NewData UeID
1...304000 {0,1} 0...65535
( x nd )
( x ue )
a. For further details on the meaning of the fields present in this subframe configuration, please see TS25.212 Sections 4.5 and 4.6.
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Source Configuration: The table below shows the valid combinations of SourceType and SourceValue elements to generate source data. All sources produce a sequence of values 0 and 1 i.e. representing bits. In the case of finite-length definition of sources such as bitfield and file, the bit sequence generated will repeat when more bits are requested from this source than are defined by it.
SourceTypea SourceValue interpretation SourceValue Range Definition Generates the bit sequence from PN generator with pn9 integer seed for PN initialisationb 0...511 polynomial x 9 + x 4 + 1 with starting state given by SourceValue. Generates the bit sequence from PN generator with pn15 integer seed for PN initialisation 0...32767 polynomial x 15 + x + 1 with starting state given by SourceValue.
file
string specifying filename string specifying bitfield ---
a valid filename specifying a file containing whitespace separated characters 0 and 1 representing bits. See Source Configuration Examples. --A source producing zeros. A source producing ones. Generates the bit sequence from PN generator with
bitfield zeros ones
pn9_itu
0...511
polynomial x 9 + x 5 + 1 with starting state given by SourceValue. Generates the bit sequence from PN generator with
pn23
0...8388607
polynomial x 23 + x 18 + 1 with starting state given by SourceValue.
a. The strings describing SourceType are case-insensitive. b. If a seed value of 0 is given for any of the PN sequence sources, a randomly chosen seed will be internally generated.
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Source Configuration Examples:

SourceType SourceValue Source bit sequence generated 1,0,0,1,1,0,0... Interpretation SourceValue interpreted as a binary vector of bits SourceValue interpreted as a hexidecimal number, converted into a sequence of bits.a
bitfield
1001
bitfield
0xA5
1,0,1,0,0,1,0,1,1,0,1...
a. Bit sequence generated will always be a multiple of 4 bits in length i.e. leading zero bits of most significant nibble will be generated.
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Example XML configuration:
Block Inputs: None Block Outputs: HS-PDSCH Ant1 Real: Real part of Antenna 1 output value for Physical Downlink Shared Channel. HS-PDSCH Ant1 Imag: Imaginary part of Antenna 1 output value for Physical Downlink Shared Channel. HS-DSCH CCTrCH: The current data in the DSCH coded composite transport channel. DCH TBS: The current Transport Block Set at the input to the DSCH coding. HS-SCCH Ant1 Real: Real part of Antenna 1 output value for Shared Control Channel. HS-SCCH Ant1 Imag: Imaginary part of Antenna 1output value for Shared Control Channel.
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HS-SCCH Subframe: The content of the HS-SCCH channel prior to spreading. HS-PDSCH Ant2 Real: Real part of Antenna 2 output value for Physical Downlink Shared Channel. HS-PDSCH Ant2 Imag: Imaginary part of Antenna 2 output value for Physical Downlink Shared Channel. HS-SCCH Ant2 Real: Real part of Antenna 2 output value for Shared Control Channel. HS-SCCH Ant2 Imag: Imaginary part of Antenna 2 output value for Shared Control Channel. Parameter Dialog Box:
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5.5
Channel Models
For complex baseband simulation, there is a choice of four different channel models. The library provides a simple static channel model consisting of a complex gain, and three channel models derived from the 3GPP standards. The channel models are as follows:
MPTH
Complex Gain (CPLXGain) Rayleigh Fading Channel(FadingCh) Moving Channel (MovingCh) Birth-Death Channel (BthDthCh)
MOV
BD
Where a simple complex (baseband) simulation is required, the complex gain can be used. The Rayleigh fading channel provides various parameters such as mobile user velocity and produces a fading channel with complex output for a complex input signal. The moving channel sets up a two path channel, with the first path fixed and the second path moving in a sinusoidal fashion. The birth-death channel provides a two path channel where a channel path dies and reappears immediately with a new delay.
BD
MOV MPTH
141
5.5.1 Complex Gain Block Name: CPLXGain Abbreviation: CPLXGain
Synopsis: This block amplifies the complex valued input signal.
Parameter
Range
Default value 0 dB
Definition Magnitude of the complex gain factor. It can be specified in dB or linear Phase in degrees of the complex gain factor Disables the block output
Gain (dB, Linear)
All
Phase (degrees) Disable Output
All True/False
0 False
Block Inputs: Real: Real part of the complex valued input. Imag: Imaginary part of the complex valued input. Block Outputs: Real: Real part of output value. Imag: Imaginary part of output value. Discussion: This block amplifies a complex valued input data sequence. The gain factor is specified in polar form AG e
j G
[5.5.1]
where A G and G are the gain and phase of the factor amplitude respectively. Let x R + jx I be the complex valued input with a polar representation Ax e
j x
[5.5.2]
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where A x and x are the gain and phase of the input respectively. The output of the block will be Ay e
j j y
= Ax AG e
j ( x + G )
[5.5.3]
A y e y is represented in rectangular form y R + jy I and sent to the output. The gain factor phase G is specified in degrees, while the amplitude A G can be specified in linear or in dB according to A G (dB) = 20 log A G
[5.5.4]
References:
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5.5.2 Rayleigh Fading Channel Block Name: FadingCh

MPTH
Abbreviation: FadingCh
Synopsis: This block simulates a multipath fading channel.
Parameter Velocity (km/h) Carrier frequency (Hz)
Range
Default Value
Definition Speed of the mobile station The carrier frequency Phase for the component weight generation. If random is selected, this parameter is ignored and a random phase is chosen. Initial time for the component weight generation No. of terms used to calculate Rayleigh fading waveforms Filename specifying no. of paths, average delay and power of each multipath
vm > 0 fc > 0 0 < < 2
3km/h 2.14 10 Hz
9
Phase (rad)
Initial Time (sec)
t0 > 0 N 0 = { 4, 8, 16, 32, 64 }

must be a pathname to a valid parameter file
No. of terms
16
Channel Parameter Filename
..\general\ case1.txt
Block Inputs: Real: Real component of input to channel x I ( t ) Imag: Imaginary component of input to channel x Q ( t ) Block Outputs: Real: Real component of channel output y I ( t ) Imag: Imaginary component of channel output y Q ( t ) Discussion: This block simulates a multipath Rayleigh fading channel with the structure shown in Figure 5.5.1.
144
x ( t ) = x I ( t ) + jx Q ( t ) G 0 ( w I ( t ) + jw Q ( t ) )
0 0
1
G 1 ( w I ( t ) + jw Q ( t ) )
1 1
2
GN 1 ( w I
N1
N 1
( t ) + jw Q
N1
(t) )
y I ( t ) + jy ( t )
Figure 5.5.1: Multipath fading channel structure.
The envelope of the filter weights w i ( t ) = w I i ( t ) + jw Q i ( t ) , i = 0, 1, N 1 has a Rayleigh distribution and is generated using the modified Jakes fading model described later. The output of the filter is:
N1
y ( t ) = y I ( t ) + jy Q ( t ) =
i=0
Gi wi ( t ) x ( t i )
[5.5.5]
The values of G i and i for i = 0, 1, , N 1 (where 0 is assumed to be zero) are obtained from the channel text file, whose format is explained next. The first line of the text file should indicate the number of filter weights. The time average delay relative to the first tap is specified in nsec and appears in the first column, while the average power of each tap relative to the strongest tap is specified in dB on the second column as shown below.
paths = 6 delay(nsec) power(dB) 0 0 200 -0.9 800 -4.9 1200 -8.0 2300 -7.8 3700 -23.9
Filter taps generation, modified Jakes model:
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A modified version of the Jakes model has been used to generate the time correlated Rayleigh fading waveforms used in the filter taps. Each tap of the filter w k ( t ) has been generated using the expression
N0
wk ( t ) =
2 ----N0
n=1
A k ( n ) [ cos ( n ) + j sin ( n ) ] cos ( n ( t + t 0 ) + ) k = 0, 1, , N 0 1

[5.5.6]
N 0 is the number of terms used to calculate the Rayleigh fading waveforms, A k ( n ) is the k th Walsh-Hadamard sequence in n of length N 0 , therefore N 0 has to be a power of two, since only Walsh-Hadamard sequences of power of two length exist. The number of weights in the system N is limited to N 0 , as a maximum number of N 0 codewords of length N 0 exist. n is n n = ----N0 and 2 ( n 0.5 ) - n = 2 f m cos -------------------------- 4N
0
[5.5.8] [5.5.7]
where f m is the maximum Doppler frequency f m = f c v m c , with c being the speed of light. is a uniformly distributed random phase in the interval [ 0, 2 ] , or the fixed phase chosen by the user. t 0 is the initial time parameter. It is suggested that N 0 = 8 provides an acceptably accurate approximation to the ideal case of Rayleigh fading. With the traditional Jakes model, the different waveforms generated present significant cross-correlation, and therefore different taps are not completely independent. With the modified version and due to the use of orthogonal functions (Walsh-Hadamard codewords), cross-correlation between the different waveforms generated is reduced.
146
References:
147
5.5.3 Moving Channel Block Name: MovingChannelModel

MOV
Abbreviation: MovingCh
Synopsis: This block simulates a two path moving channel.
Parameter
Range
Default Value 1.4142
Definition Magnitude of the complex gain factor. It can be specified in dB or linear. Phase in radians of the complex gain factor. If random is selected, this parameter is ignored and a random phase is chosen.
Gain (v,dB)
All
Phase (rad)
0 < < 2
-4
B (s) A (s) delta Omega (1/s)
B>0 A>0 > 0
1 10 s 5 10 s
0.04 rad/s
6 6
Minimum distance between the two paths Extent of the variation of the delay between the paths. Frequency of the moving path variation in rad/s. Magnitude of the complex gain factor. It can be specified in dB or linear.
Gain (v,dB)
All
1.4142
Block Inputs: Real: Real component of input to channel x I ( t ) Imag: Imaginary component of input to channel x Q ( t ) Block Outputs: Real: Real component of channel output y I ( t ) Imag: Imaginary component of channel output y Q ( t ) Discussion: This block simulates a two path moving channel as described in 3G TS 25.104. The two paths are as follows:
148
P1
P2
delay
Figure 5.5.2: Moving channel path positions.
Path P1 is static, with no delay, and has a complex weight A G e G where A G is the gain block parameter and G is the phase block parameter. If random was selected for the phase, G is a uniformly distributed random phase in the interval [ 0, 2 ] . Path P2 is of variable delay, with the delay relative to path P1 governed by the Eq. 5.5.9: A - ( 1 + sin ( t ) ) = B + -2 The weight of path P2 is identical to the weight of path P1. The output of the block will therefore be: y ( t ) = y I ( t ) + jy Q ( t ) = A G e where x ( t ) = x I ( t ) + jx Q ( t ) .
j G
[5.5.9]
( x ( t ) + x ( t ) )
149
References: 3G TS 25.104: FDD; Radio transmission and reception.
150
5.5.4 Birth-Death Channel Block Name: BirthDeathChannelModel

BD
Abbreviation: BthDthCh
Synopsis: This block simulates a two path birth-death channel.
Parameter
Range
Default Value 1.4142
Definition Magnitude of the complex gain factor. It can be specified in dB or linear Phase in radians of the complex gain factor. If random is selected, this parameter is ignored and a random phase is chosen.
Gain (v,dB)
All
Phase (rad)
0 < < 2
-4
Path position spacing (sec)
ts > 0 N>2
1 10
Spacing between the possible channel path positions The number of positions which the path positions may take The time between the updates of actual path positions
No. of possible path positions
11
Set update period (sec)
tu > 0
0.191
Block Inputs: Real: Real component of input to channel x I ( t ) Imag: Imaginary component of input to channel x Q ( t ) Block Outputs: Real: Real component of channel output y I ( t ) Imag: Imaginary component of channel output y Q ( t ) Discussion: This block simulates a two path birth-death channel as described in 3G TS 25.104.
151
P1
P2
0 ts 2 ts
...
( N 1 ) ts
P1
P1
P2
0 ts 2 ts
...
( N 1 ) ts
P2 P1
P2
0 ts 2 ts
...
( N 1 ) ts
Figure 5.5.3: Path birth and death in birth-death channel.
The path position spacing ( t s ) and number of possible path positions ( N ) are used to create a discrete set of possible path positions as follows: = { 0 , ts , 2 ts , 3 ts , , ( N 2 ) ts , ( N 1 ) ts } The following algorithm is then used to select the two possible path positions P1 and P2 from the set : 1) Initially, P1 and P2 are chosen at random from . Paths P1 and P2 cannot take the same position. 2) After time t u has elapsed, path P1 vanishes and reappears immediately at a random location selected from , excluding the position that path P2 currently takes. 3) After a further time t u has elapsed, path P2 vanished and reappears immediately at a random location selected from , excluding the position that path P1 currently takes. 4) Repeat steps 2 and 3.

j
152
Paths P1 and P2 both have a complex weight A G e G where A G is the gain block parameter and G is the phase block parameter. If random was selected for the phase, G is a uniformly distributed random phase in the interval [ 0, 2 ] . The output of the block will therefore be: y ( t ) = y I ( t ) + jy Q ( t ) = A G e
j G
( x ( t P1 ) + x ( t P2 ) )
[5.5.10]
References: 3G TS 25.104: FDD; Radio transmission and reception.
153
5.6
Synchronisation
Two blocks are provided for synchronisation:
DL Sync
Synchronisation Acquisition(SyncAcqs)
Clock Generator (ClockGen)
The block is for synchronisation acquisition from the primary and secondary synchronisation channels (P-SCH and S-SCH), and the common pilot channel (CPICH).
DL Sync
The block generates a series of clock signals used to synchronize the different elements of a 3GPP communications system. Clock signals with a period equal to a chip, a symbol, slot, a frame, and a superframe are produced. The block will also provide a count of the number of clock periods, chips, symbols, slots and frames.
154
5.6.1 Synchronisation Acquisition

DL Sync
Block Name: SynchronisationAcquisition Abbreviation: SyncAcqs
Synopsis: This block provides slot synchronisation, frame synchronisation, primary scrambling code detection and scrambling code group detection, by decoding of the primary and secondary synchronisation channels (P-SCH and SSCH) and the common pilot channel (CPICH).
Parameter
Range
Default Value
Definition The level of PSC detection filter output above which an event will be considered detected. The level of SSC detection filter output above which an event will be considered detected. If enabled, SSC and PSC filtering will continue even after detection is made. If enabled, slot events after the first detection will be made simply by counting the appropriate number of chips. If enabled, the filter outputs will be zero for any value below the specified threshold. Determines which SSC filter will be available on outputs 2 and 3. See section on delay offset
PSC Decision Threshold (v)
SSC Decision Threshold (v)
Continue filtering after Code Group acquisition
Enable/ Disable
Disabled
Use chip counting after filters detect first slot event
Enable/ Disable
Disabled
Output (extract) threshold filter events only
Enable/ Disable
Disabled
SSC Codeword Delay Offset(samples)
{1,2, .. 16}
1 0
Block Inputs: Real: Real component of output from the channel x I ( t ) Imag: Imaginary component of output from the channel x Q ( t )
155
Block Outputs: P-SCH Filter (Real): Real component of the filter used to detect the primary synchronisation code. P-SCH Filter (Imag): Imaginary component of the filter used to detect the primary synchronisation code. S-SCH Filter (Real): Real component of the filter used to detect a particular slot code for the secondary synchronisation channel. The particular code is chosen in the SSC codeword parameter. S-SCH Filter (Imag): Imaginary component of the filter used to detect a particular slot code for the secondary synchronisation channel. The particular code is chosen in the SSC codeword parameter. Slot Codes (Detect): The series of secondary synchronisation codes (SSCs) detected by the S-SCH filters. Code Group (Detect): The scrambling code group which has been detected by decoding the S-SCH channel. Pri Code (Detect): The primary scrambling code which has been detected by decoding the CPICH channel. Slot # (Detect): Gives the slot number in the current frame once the scrambling code group has been established. Slot Boundary (True): Gives a series of impulses representing the slot boundaries. 1st Frame (True): Indicates the position of the first frame. Discussion: This block provides basic synchronisation acquisition by the reception of three downlink common control physical channels as follows: P-SCH (Primary Synchronisation Channel) S-SCH (Secondary Synchronisation Channel) CPICH (Common Pilot Channel) The P-SCH is detected by the P-SCH filter, the output of which is available on the outputs P-SCH Filter (Real) and P-SCH Filter (Imag). When the filter output goes above the threshold defined by the PSC Decision Threshold parameter, this corresponds to a slot edge. The Slot Boundary (True) event output will contain an impulse at this point. Further slot events will be recorded on this output when they are detected by the P-SCH filter, or if the Use chip counting after filters detect first slot event option is selected, these slot events will occur by simply counting the appropriate number of chips at the input (the number of chips/slot). The S-SCH is detected by a bank of S-SCH filters. There are 16 S-SCH filters, each matched to one of the 16 Secondary Synchronisation Codes (SSCs). The SSC Codeword parameter chooses which filter output will be available on the S-SCH Filter (Real) and S-SCH Filter (Imag) outputs. The S-SCH contains a string of
156
15 codes, chosen from the 16 SSCs. These 15 codes each last for one slot duration, and therefore together span a whole frame. As a particular SSC is received, the SSCH filter matched to this SSC will go above the threshold defined in the SSC Decision Threshold parameter, and this particular SSC is recorded on the Slot Codes (Detect) output. Once a full frame of 15 SSCs has been received, the scrambling code group can be established by checking the string of SSCs received against a table in 3G TS 25.213. This scrambling code group is available on the Code Group (Detect) output as soon as it is detected. At this stage the P-SCH and S-SCH filters are no longer required, but can be kept in use by selecting the Continue filtering after Code Group acquisition block option. If after receiving 15 SSCs no scrambling code group can be established (i.e. bad data has been received), the scrambling code group detection is reset, and the detector waits for another 15 SSCs. Now that the scrambling code group has been detected, the position of frame edge can be established. Immediately the current slot number is available on the Slot # (Detect) output. When the next frame edge is detected, this is the first frame that is properly synchronised, and this event will be recorded by the 1st Frame (True) output going high. Given that primary synchronisation has been achieved, and the scrambling code group is now known, the received CPICH can be decoded in order to establish which primary scrambling code is being used. This is achieved by cross-correlating a received CPICH symbol with locally generated versions of the eight possible primary scrambling codes. Once the primary scrambling code has been detected, it is available on the Pri Code (Detect) output.
157
References: 3G TS 25.213: Spreading and modulation (FDD)
158
5.6.2 Clock Generator Block Name: Clock Gen Abbreviation: ClockGen
Synopsis: This block generates a series of clock signals used to synchronize the different elements of a communications systems.
Parameter Clocks per chip Chips per Symbol Chips per Slot Internal Clock Frequency Slots per Frame Frames per Superframe
Range All > 0 All > 0 All > 0 All > 0 All > 0 All > 0
Default value 1 256 2560
Definition Number of input/internal clock periods per chip Number of chips per symbol (Spreading Factor) Number of chips per slot
6
3.84 10
15 72
Frequency of the internal clock (only if internal clock is enabled) Number of slots in a frame Number of frames in a superframe Enables or disables the internal clock, the clock input is not used if the internal clock is enabled Input high/low threshold True output voltage False output voltage
Internal clock
Enable/Disable
Enabled
Input Threshold True Output False Output
All All All
0 1 -1
Block Inputs: Clock: Normally the chip rate clock, however it is possible to have more than one input clock cycles per chip by setting the clock per chip parameter. The block internal counter is triggered on the rising edge of the input clock. This input is not used if the internal clock is enabled.
159
Advance: If this input is greater than the threshold, the next chip clock is advanced one internal/input clock cycle (only if there is more than one internal/input clock cycle per chip). Retard: If this input is greater than the threshold, the next chip clock is retarded one internal/input clock cycle (only if there is more than one internal/input clock cycle per chip). Reset: Resets the block counters, active if greater than the threshold. Enable: Enables operation of the clocks, active if greater than the threshold. Block Outputs: Chip Clock: Clock signal with its period equal to the chip period. Symbol Clock: Clock signal with its period equal to the symbol period. Slot Clock: Clock signal with its period equal to the duration of a slot. Frame Clock: Clock signal with its period equal to the duration of a frame. Superframe Clock: Clock signal with its period equal to the duration of a superframe. Sub-chip Count: Counts the number of clock periods. Chip Count: Counts the number of chips. Symbol Count: Counts the number of symbols. Slot Count: Counts the number of slots. Frame Count: Counts the number of frames. Discussion: This block produces clock signals used to synchronize the communications system. The clock signals produced can be used to run other blocks such as scrambling and channelisation codes generator, spreader/ despreader, physical channels generators (e.g. blocks generating synchronization codes, RACH preamble, pilot symbols, etc.) and any block that requires to synchronize to the rest of the system. An example of the some of the clock signals is shown in Figure 5.6.1.

1 chip
160
chip clock
256 chips = 1 symbol symbol clock
256 chips = 1 symbol
2560 chips = 1 slot
slot clock
Figure 5.6.1: Chip, symbol and slot clock signals. Example shows 256 chips per symbol and 2560 chips per slot
The input clock signal or the internal clock signal, are used as reference to generate the chip clock waveform. The chip clock can have the same period as the input/ internal clock waveform or it can also have a different one. This is controlled by the clocks per chip parameter. Figure 5.6.2 illustrates the case in which there are n internal/input clock cycles per chip clock period. This situation is specially useful when we want to make use of the advance/retard capability of this block. The advance/retard option is especially indicated for synchronization and tracking of variations in a received signal, such as the delay locked loop. The operation of the advance retard option is the following: with the number of internal/input clock cycles per chip n set to a value other than one, and the advance/ retard inputs having a value below the threshold level, the block will generate a raising edge every n internal/input clock cycles as indicated in Figure 5.6.2. If the advance input has a value above the threshold level, the chip clock will advance the production of a raising edge by one internal/input clock cycle as shown in Figure 5.6.3. The retarding operation is similar, but retarding the production of a raising
1 clock cycle input/external clock
n clock cycles = 1 chip
n clock cycles = 1 chip
chip clock Figure 5.6.2: Relation between input/internal clock and chip clock

1 internal/input clock cycle
161
input/external clock advance input chip clock
6 internal/input clock cycles = 1 chip
chip period reduced 1 internal/input clock cycle
threshold
Figure 5.6.3: Use of advance input and its effect on the chip clock. Shown in relation with the input/external clock
edge by one internal/input clock cycle as shown in Figure 5.6.4. This process continues as long as the advance/retard state is maintained. Asserting both advance/ retard together causes no advance or retard to take place as they cancel each other out.
input/external clock chip clock 1 internal/input clock cycle
chip period increased 1 internal/input clock cycle
retard input
threshold
Figure 5.6.4: Use of retard input and its effect on the chip clock. Shown relation with the input/external clock
in
162
References:
163
5.7
Physical Measurements
Two blocks are included in the library to perform physical layer measurements. These blocks are:
ACLR
Adjacent Channel Leakage Measurement
BER
Bit Error Rate Measurement

ACLR
The adjacent chennel leakage block measures the Adjacent Channel Leakage Ratio (ACLR) for a given channel at the input of the block. This ratio indicates the amount of power which is leaked into contiguous frequency bands by a certain channel.
The bit error rate block
BER
provides Bit Error Rate (BER) measurements.
164
5.7.1 Adjacent Channel Leakage Block Name: ACLRMeasurements

ACLR
Abbreviation: ACLR
Synopsis: This block measures the Adjacent Channel Leakage Ratio (ACLR) for the channel presented at the block input.
Parameter
Range
Default value 10
Definition The base-2 logarithm of the FFT length used to generate the spectrum of the channel. The number of spectra over which to average the measurement outputs.
6
Frame Length (2^n)
n1
Averaging Length (frms)
La > 0 f BW > 0 f sep > 0
10
Bandwidth (Hz)
3.84 10 5 10
6
The bandwidth of the data in the channel. The separation in Hz between the centres of two adjacent channels.
Channel Sep (Hz)
Block Inputs: Real (I): Real part of the channel to measure. Imag (Q): Imaginary part of the channel to measure. Block Outputs: +1st Adj. Carrier: ACLR in carrier below. -1st Adj. Carrier: ACLR in carrier above. -2nd Adj. Carrier: ACLR in 2nd carrier below. +2nd Adj. Carrier: ACLR in 2nd carrier above. In-band: In-band power. Spectrum: The spectrum generated by the internal FFT which is examined to calculate the other outputs. Discussion: This block measures the ratio of the power that is leaked into the first two channels above and below the centre channel to the power of that centre channel. The centre channel is taken from the block input, and therefore this block should be connected to an appropriately filtered channel which is ready for carrier
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modulation. The block input nis transformed by an FFT of length given by the Frame Length parameter ( 2 ). A number of consecutive FFTs (with the number being given by the Averaging Length parameter) are averaged together. The first five outputs give the power in the five bands marked f BW at the positions shown in Figure 5.7.1 (centres spaced at intervals of f sep ). The default values of f BW and f sep are taken from the 3G TS 25.104. These bands are shaped by a Root Raised Cosine filter with a roll-off of 0.22 (see 3G TS 25.101). The sixth output (marked Spectrum) gives the actual FFT output which is used to calculate the power in the bands. The output generates a set of FFTs back-toback with each FFT containing the number of samples given by the Frame Length parameter. The ACLR required for compliance with the 3GPP standards can be found in 3G TS 25.104. 2nd carrier below carrier below carrier above 2nd carrier above
in-band
f BW f sep
f BW f sep
f BW f sep
f BW f sep
f BW f sep
Figure 5.7.1: Positioning of adjacent channels.
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References: 3G TS 25.101: UE radio transmission and reception (FDD). 3G TS 25.104: UTRA (BS) FDD; Radio transmission and reception.
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5.7.2 Bit Error Rate Block Name: BitErrorRateCounter

BER
Abbreviation: BER
Synopsis: This block provides Bit Error Rate measurements for the physical layer.
Parameter Trial Length (samples) Input Threshold (v) Delay Offset Range Default value 1 0 0 Definition The number of bits to average across. Threshold for quantising inputs into binary values.
N>0
All 0
Block Inputs: Two inputs (nameless) which are to be compared. These inputs must be at the same sampling rate. Block Outputs: Block BER: Bit Error Rate across the block size defined by the Trial Length parameter Total BER: Bit Error Rate across entire system run. Total Errors: The total number of errors across the entire system run. Discussion: This block provides the ability to measure the Bit Error Rate (BER) performance of physical layer simulations. The two inputs should be connected to two data streams (of the same rate) which would be identical under perfect operation e.g. the input to a spreader and the output from a despreader. The inputs are quantised using the Input Threshold parameter. Input values above or equal to the threshold are considered high, and conversely values lower than the threshold are considered low. The presence of a bit error is simply detected by the logical XOR of the two input values after thresholding. The resulting sequence of bit errors from the logical XOR is then processed for the three outputs. The Total Errors output is simply a running total of the number of bit errors since the beginning of the system run. The Total BER output is the total number of bit errors divided by the number of bits tested, and is consequently a measure of the probability of a bit error averaged across the system run. The Block BER is the number of bit errors in the current block divided by the length
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of the block, as specified by the Trial Length parameter. Consequently, it provides a measure of the bit error probability across a limited time period. This output produces one value per block, at the end of the block. It should be noted that when Trial Length=1, the Block BER output gives the sequence of bit errors, as the BER in a block of length 1 can only be 1.0 or 0.0 (if the input bits were different or the same, respectively). For any Trial Length N where N > 1 each of the outputs is decimated by a factor of N. Parameter Dialog Box: Default parameters shown.
References:
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5.8
Multiplexers, Demultiplexers and Integrators
The library includes the following blocks: In_phase / Quadrature phase Splitter (IQSplit)
In_phase / Quadrature phase Combiner (IQComb)
1 to 2 Demultiplexer (Demux12)
Physical Channel Slot Field Demultiplexer (SlotDemx)
The I/Q splitter takes an input data stream and produces two channels suitable for passing on to an in-phase and quadrature phase (QAM) modulation.
The I/Q combiner
performs the inverse operation.
This demultiplexer block receives a bit stream that consists of two fields of multiplexed bits. The two fields are of specified length and are streamed to the outputs of the block at different sample rates.
The Physical Channel Slot Demultiplexer demultiplexes the different fields of a physical channel slot and sends the result to different outputs.
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5.8.1 I/Q Splitter Block Name: IQSplitter Abbreviation: IQSplit
Synopsis: This block splits a bit stream into I and Q channels. Even bits are directed to either the I or Q outputs as specified in the parameters. The output sample rate on either I or Q is half the input sample rate.
Parameter Input/Output Mapping
Range Even samples output to I channel Odd samples output to Q channel Enable/Disable
Default value Even samples output to I channel Disabled
Definition Determines the input/output mapping used to assign even and odd samples to the I and Q outputs See section on leading output
No leading output
Block Inputs: Data Input: The input data stream. The block expects a sampling rate of one sample per bit. Block Outputs: I: The I channel output stream. Even and odd numbered bits can be output on this channel (parameter dependent). The sample rate is half the input sample rate. Q: The Q channel output stream. Even and odd numbered bits can be output on this channel (parameter dependent). The sample rate is half the input sample rate. Discussion: The FDD specification uses QPSK for downlink channels. The serial bit stream after channel coding and multiplexing is split into I and Q bit streams to drive the I and Q channels of the spreading and modulation functions. It is specified in the documentation that even bits (e.g. b 0 , b 2 , b 4 etc.) must be mapped to the I channel while the odd bits ( b 1 , b 3 , b 5 etc.) must go to the I channel.
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Block Schematic:
I { b 0, b 1, b 2, b 3, b 4, b 5 }
R in 2 R in
Q
{ b 0, b 2, b 4 }
R in 2
{ b 1, b 3, b 4 }
R in: input sampling rate

Figure 5.8.1: Operation of IQ splitting.
References: 3G TS 25.213:Spreading and modulation (FDD)
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5.8.2 I/Q Combiner Block Name: IQCombiner Abbreviation: IQComb
Synopsis: This block combines the data sequence of the I and Q channel into a single data stream at double the rate of the inputs.
Parameter Input/Output Mapping
Range I channel output to even samples Q channel output odd samples Enable/Disable
Default value I channel output to even samples
Definition Determines the input/output mapping used to assign I and Q channels to even and odd samples See section on leading output
No leading output
Enabled
Block Inputs: I Input: I data channel Q Input: Q data channel Block Outputs: Data Output: I and Q combined channels Discussion: The I and Q input channels are combined into a single data sequence at twice the rate of the inputs. The input output mapping is determined by the parameters. Parameter Dialog Box: Default parameters shown.
References:
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5.8.3 1 to 2 Demultiplexer Block Name: Demux12 Abbreviation: Demux12
Synopsis: This block receives a bit stream that consists of two fields of multiplexed bits. The two fields are of specified length and are streamed to the outputs of the block at different sample rates.
Parameter Output 0 Length Output 1 Length Delay Offset
Range
Default value 1 1 0
Definition Number of bits in field 0 Number of bits in field 1 Delay offset in seconds (unless otherwise stated) before processing starts When enabled the delay offset is interpreted in samples See section on leading output
0 0 0
Delay in Samples
Enable/Disable
Disabled
No leading output
Enable/Disable
Disabled
Block Inputs: Data Input: The input data stream. The block expects a sample rate of one sample per bit. Block Outputs: Output 0: Bits of field 0 in the input radio frame. The sampling rate is reduced according to the reduction in number of bits between the input sequence and field 0. Output 1: Bits of field 1 in the input radio frame. The sampling rate is reduced according to the reduction in number of bits between the input sequence and field 1. Discussion: UMTS FDD time-multiplexes fields of bits together in a radio frame e.g., different transport channels and control bits (such as pilot symbols.) The Demux12 block enables two or more bit fields to be demultiplexed into separate
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streams with a corresponding reduction in sample rate relative to the multiplexed rate. Figure 5.8.2 shows an example, however, this operation can be implemented more easily using the slot demultiplexer block, introduced in the next section.
Stream C 35kbps Stream A 45kbps Stream E 15kbps Demux12 Stream D 20kbps Stream B 10kbps Stream A Ch 1 45kbps 100 bits
Ch 2 200 bits Ch 3 150 bits Ch 1 100 bits Ch 2 200 bits Ch 3 150 bits
Demux12
Stream B 10kbps
Ch 1 100 bits
Ch 1 100 bits
Stream C 35kbps Stream D 20kbps Stream E 15kbps 0ms
Ch 2 200 bits
Ch 3 150 bits
Ch 2 200 bits
Ch 3 150 bits
Ch 2 200 bits
Ch 2 200 bits
Ch 3 150 bits
Ch 3 150 bits
10ms
20ms
Figure 5.8.2: Demultiplexing three bit fields using two Demux12 block
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Block Schematic:
m R in ----------- n + m
m bits
10ms n bits
R in
m bits radio frame: 10 ms n bits radio frame: 10 ms
radio frame: 10 ms
n R in ----------- n + m
R in: input sampling rate

Figure 5.8.3: Demultiplexing of a DTCH using the Demux12 block
References:
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5.8.4 Slot Field Demultiplexer Block Name: SlotFieldDemultiplexer Abbreviation: SlotDemx
Synopsis: This block demultiplexes the different fields of the slots in the various physical channels. The demultiplexed data is sent to the different outputs of this block.
Parameter
Range DL DPCH UL DPCH S-CCPCH PRACH PCPCH User Defined
Default value
Definition Chooses the physical channel whose fields are to be demultiplexed into the different outputs of the blocks. The format of the selected channel might be variable and can also be selected in the slot format table Indicates the number of bits in each field of the selected slot. Except for the User Defined channel, the values given are fixed and determined by the selected physical channel and the specific format specified in the slot format table
Physical channel
DL DPCH
Slot Structure
Block output assignments
Output 0 Output 1 Output 2 Output 3 Output 4
field A field B field C field D field E
Assigns the different fields of the slot to different block outputs. This can be edited
Delay Offset
0
Enable/ Disable Enable/ Disable
Delay offset in seconds (unless otherwise stated) before processing starts When enabled the delay offset is interpreted in samples See section on leading output
Delay in Samples No leading output
Disabled Disabled
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Block Inputs: Slot data I: I data component of the slot to demultiplex. The block expects a sample rate of one sample per bit. Slot data Q: I data component of the slot to demultiplex. The block expects a sample rate of one sample per bit. Block Outputs: Field Set 0: Bits of slot field assigned in the parameters. Field Set 1: Bits of slot field assigned in the parameters. Field Set 2: Bits of slot field assigned in the parameters. Field Set 3: Bits of slot field assigned in the parameters. Field Set 4: Bits of slot field assigned in the parameters. Discussion: This block implements a quick and simple way of demultiplexing the different fields contained in the slots of the various physical channels. As an example we can mention the DLDPCH with a rate of 30 kbps whose slot has the structure shown in Figure 5.8.4.
DATA1 TPC TFCI 2 bits 2 bits 0 bits
DATA2 14 bits
PILOT 2 bits
Figure 5.8.4: Structure of downlink DPCH slot at 30 kbps
This is chosen by selecting the appropriate row on the slot format table in the parameter dialog box. The next step is to assign the different fields to the various outputs of the block. Assume the following correspondence is required:
Field Data 1 TPC TFCI Data 2 Pilot Output A B C D E
This means the block demultiplexes the different fields in the slot in the way shown in Figure 5.8.5. The parameter settings to perform this operation are shown in Figure 5.8.6.
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Block Output Rate R out = 3 kbps A A B C D E

DATA1 TPC TFCI 2 bits 2 bits 0 bits DATA2 14 bits PILOT 2 bits R out = 3 kbps
B C
R out = 0 kbps R out = 21 kbps

D E
R out = 3 kbps
20 bits at R in = 30 kbps
Figure 5.8.5: Demultiplexing the DPCH slot into the different blocks outputs
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Figure 5.8.6: Parameters used to demultiplex DLDPCH slots at 30 kbps
However, it might be desirable to get the two data fields in the same output of the block for further processing. This can be achieved as it is possible to assign the contents of more than one slot field to the same output. To do this double click on the output row of the block output assignment, which will change into assign mode as shown in Figure 5.8.7.
Figure 5.8.7: Assigning fields to outputs
To assign fields A and D (Data 1 and Data 2 for the DLDPCH example), the user has to click on fields A and D of the slot structure as shown in Figure 5.8.8 when in assigning mode. This setting will send the data bits in fields A and D to output 0.
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Figure 5.8.8: Assigning slot fields to outputs
References: 3G TS 25.211:Physical channels and mapping of transport channels onto physical channels (FDD)
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5.9
Averaging Blocks
The following blocks are included in this group: Integrate and dump (IntDump)
Frame Averaging (FrameAvg)
The integrate and dump block is normally used at the output of the despreader to integrate and dump the despread chips over a bit/symbol period in order to recover the transmitted data.
The frame averaging block performs an averaging operation over a window of a certain amount of samples specified a a parameter.
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5.9.1 Integrate and Dump Block Name: IntegrateDump Extract Abbreviation: IntDump
Synopsis: This block integrates and dumps (performs a decimation operation) the complex input signal over the specified period.
Parameter Integration interval I channel
Range
Default value
Definition Length of the integration operation in number of samples on the in-phase component Length of the integration operation in number of samples on the quadrature component Delays the beginning of the processing by a certain amount of time/samples When enabled the delay offset is interpreted in samples See section on leading output
>0
Integration interval Q channel
>0
Delay Offset
Delay in Samples
Enable/Disable
Disabled
No leading output
Enable/Disable
Disabled
Block Inputs: I Input: I data channel Q Input: Q data channel Block Outputs: I Output: I channel data output. The output rate is decimated by the value specified in the integration length parameter. Q Output: Q channel data output. The output rate is decimated by the value specified in the integration length parameter. Discussion: A complex integrate and dump operation is performed on the complex input. This block is equivalent to having two real integrate and dump blocks in parallel. For a given integration length of N samples blocks of N input samples are added together and the result is sent to the output. The sampling rate at the output is N times smaller than at the input. The process is described in Figure 5.9.1 for a sequence of real values.
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input signal at rate R in

N samples A N samples N samples N samples
integrate
NA N ( A ) NA NA
dump
NA
N ( A )
extract output signal at R out = R in N

Figure 5.9.1: Integrate and dump operation over six samples (N = 6)
Note that the output of the integrate and dump requires scaling in order to obtain the desired amplitude value. The complex gain block can be used to perform this operation. The provision of different integration intervals for the in-phase (I) and quadrature (Q) components is for performing convenient integrate and dump operations in an uplink scenario. In an uplink DPCH channel, the DPDCH is transmitted on the I component and the DPCCH is transmitted on the Q component. These two channels may have different spreading factors, and consequently need to have a different integrate and dump length.
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Block Schematic: I input

x I ( n ), x I ( n + 1 ), , x I ( n + N 1 ) R in R in
N1
k=0 N1
xI ( n + k )
I output
R in R out = -----N
x Q ( n ), x Q ( n + 1 ), , x Q ( n + N 1 )
k=0
xQ ( n + k )
Q output
R in R out = -----N
Q input
R in : Input sampling rate

Figure 5.9.2: General form for integrate and dump.
References:
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5.9.2 Frame Averaging Block Name: Frame Averaging Abbreviation: FrameAvg
Synopsis: This block an averaging operation over vectors.
Parameter Frame length (samples) Averaging length (frames)
Range
Default value 256
Definition Length of averaging frame (vector) in number of samples Number of frames (vectors) over which the averaging operation is performed
>0
>0
Block Inputs: Input: Input data Block Outputs: Output: Output averaged data. Discussion: This block combines a multiplexer and an averager in order to average samples of different blocks (frames) as shown in Figure 5.9.3. This is equivalent to average vectors. Assume a frame length of N samples and an averaging length of K frames. Under these conditions the frame averaging block reads K frames (vectors) from the input and averages them sample by sample, i.e. the first sample of the K frames are averaged to produce the first sample of the output, the second sample of the K frames are then averaged to produce the second sample of the output. This process goes on with all the N samples of the K frames as shown in Figure 5.9.3. This kind of structure can be useful to perform channel estimation, where subsequent cross-correlations of the received pilot bits with the local copy of the same pilot bits generated at the receiver has to be averaged in order to minimise the effect of the noise. In this case, the frame length is the length of the cross-correlation blocks, and the number of frames is the number of cross-correlation blocks to be averaged. A typical sliding window averager can also be implemented using this block by setting the averaging length to 1 and specifying the size of the averaging windows in the frame length parameter.
5 The 3GPP:fdd Library Blocks N samples #i
186
#(i+1) #i N samples #(i+1) N samples #(i+2) N samples #(i+K) N samples multiplex
#(i+2)
K input frames #(i+K)
sample by sample averaging
output N samples
Figure 5.9.3: Operation of the Frame Averaging block
6 Block-driven 3GPP:fdd Library Blocks
187
Block-driven 3GPP:fdd Library Blocks
This section of the manual documents the block-driven library blocks available only for the Mathworks Simulink platform. These blocks can be driven by an input data block of any size in Simulink. If data block sizes of 1 are used then these Simulink blocks can be conveniently used in conjunction with the scalar-driven blocks described earlier in this document. This section now continues with a description of each block, the following blocks are provided: Frame Scrambler Frame Spreader E-AGCH Coder E-HICH Coder E-RGCH Coder E-DPCCH Coder E-DCH Coder
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6.1
Frame Scrambler Block Name: Frame Scrambler
Synopsis: Perfoms the uplink/downlink scrambling.

Parameter Uplink/Downlink Scrambling Code Number Offset Range {Uplink,Downlink} 0...38399 0...38399 Default value Downlink 0 0 Definition Selects either Uplink or Downlink Scrambling. Selects the scrambling code. Selects the offset to the scrambling sequence.
Block Inputs: Data In: This is the input data block to the scrambler. This block supports real/complex and scalar/vector inputs. Block Outputs: out: Complex scrambled data. Input and output data blocks are of the same size. Parameter Dialog Box: Default parameters shown
Description: Scrambles a baseband QPSK/BPSK signal (or sum of such signals) for either downlink or uplink. The length of the scrambled output sequence is equal to the input block size.
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6.2
Frame Spreader Block Name: Frame Spreader
Synopsis: OVSF Spreading.

Parameter Spreading Factor Code Number Range 1,2,4,8,16,32,64, 128, 256 or 512 0...Spreading Factor - 1 Default value 128 12 Definition The factor by which the input symbols are spread. Represents the particular spreading code.
Block Inputs: Channel Coded Data: The input to the spreader block, a set of complex symbols. Block Outputs: out: Spread chips resulting from spreading the input block of data. Parameter Dialog Box: Default parameters shown.
Description: The Frame Spreader performs the spreading of the coded data, depending on the spreading factor and the code number. The spreading process involves the generation of the Orthogonal Variable Spreading Factor code generation process and the calculation of the Kronecker product to spread the input data symbols.
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6.3
E-AGCH Coder Block Name: E-AGCH Coder
Synopsis: This block performs channel coding for the E-DCH Absolute Grant Channel.
Parameter E-RNTI Range 0...65535 Default value 1200 Definition Enhanced Radio Network Identifier.
Block Inputs: Absolute Grant Value(s): The Absolute Grant value(s) for the E-AGCH Coding. The allowed range of values and the corresponding indices are given in the drop down table for reference. Absolute Grant Scope(s): This scalar or vector input indicates the Absolute Grant Scope(s). 1 = Per HARQ process, 0 = All HARQ processes Block Outputs: out: Complex values representing mapped data, 30 complex values per subframe i.e. 30 complex values per each element of the vectors at inputs 1 and 2. Parameter Dialog Box: Default parameters shown.
191
Description: The E-AGCH Coding Token generates the complex values representing mapped data, 30 complex values per subframe i.e. 30 complex values per each element of the vectors at inputs 1 and 2. The Absolute Grant Vector indicates the required indices and the Absolute Grant Scope vector indicates the corresponding scope. The length of the AGValue vector and the AGScope vector should be the same; else the block returns an error.
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6.4
E-HICH Coder Block Name: E-HICH Coder
Synopsis: This block performs channel coding for the E-DCH HARQ Indicator Channel.
Parameter Sequence index Slots Range 0...39 {3,12} Default value 5 12 Definition The sequence index number. This is the range of the number of slots which also indicates the output length.
Block Inputs: HARQ Acknowledgment: The HARQ acknowledgement indicator input. +1 = ACK, 0 = NACK (RLSs not containing the serving E-DCH cell, -1 = NACK (RLS containing the serving EDCH cell. Block Outputs: out: Complex values representing mapped data, 20 values for each slot so either 60 or 240 complex values depending on the number of slots parameter. Parameter Dialog Box: Default parameters shown.
Description: The E-HICH Coding Token generates the complex values representing mapped data, outputs the complex values representing mapped data, 20 values per slot so either 60 or 240 complex values depending on the 'Slots' parameter.
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6.5
E-RGCH Coder Block Name: E-RGCH Coder
Synopsis: This block performs channel coding for the E-DCH Relative Grant Channel.
Parameter Sequence index Slots Range 0...39 {3,12,15} Default value 39 15 Definition The sequence index number. This is the range of the number of slots which also indicates the output length.
Block Inputs: Relative Grant Command: The Relative Grant command is mapped to the relative grant value as shown:
Command Up Hold Down RGValue (serving EDCH RLS) +1 0 -1 RGValue (all other) not allowed 0 -1
Block Outputs: out: Complex values representing mapped data, 20 values for each slot so either 60, 240 or 300 complex values depending on number of slots parameter. Parameter Dialog Box: Default parameters shown.
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Description: The E-RGCH Coding Token generates the complex values representing mapped data, 20 values for each slot so either 60, 240 or 300 complex values depending on number of slots parameter.
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6.6
E-DPCCH Coder Block Name: E-DPCCH Coder
Synopsis: This block performs channel coding for the E-DPCCH Channel. Block Inputs: happy: The E-DCH happy bit value, or a vector of such values. Valid values are 0 and 1. rsn: The Retransmission Sequence Number, or a vector of such numbers. Valid values are 0, 1, 2 and 3. etfci: The E-TFCI (Transport Format Combination Indicator), or a vector of such indicators. Valid values are in the range 0 to 127. Block Outputs: out: 30 coded bits per subframe available at the input. Parameters: This block has no parameters. Parameter Dialog Box:
Description: The E-DPCCH Coder generates coded data subframes of 30 bits. Each input value set across the 3 inputs corresponds to one subframe, therefore the output will contain a multiple of 30 coded bits, one set of 30 for each subframe available at the input.
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6.7
E-DCH Coder Block Name: E-DCH Coder
Synopsis: This block performs channel coding for the data part of the E-DCH Channel.
Parameter Range Default value Definition Specifies the Redundancy Version to encode when performing the Hybrid-ARQ rate matching. This parameter governs the output block size and should be set to the capacity per frame of the physical channel set (E-DPDCH) that will convey the coded data.
Redundancy
{0,1,2,3}
Physical Frame Capacity
1...38400
9600
Block Inputs: Data: The input data block to be encoded Block Outputs: out: The coded data block, matching the specified physical frame capacity. Parameter Dialog Box: Default parameters shown.
Description: The E-DCH Coder takes the input block of data provided and encodes it by performing CRC attachment, code block segmentation, turbo coding and Hybrid-ARQ rate matching.
7 Matlab Toolbox Functions
197

This section of the manual documents the toolbox functions available for the MATLAB platform. All the toolbox functions returns the same type (cell array or matrix) as the input and preserves the orientation, wherever possible. Also if the input is empty, the toolbox functions returns an empty output. This section now continues with a description of each toolbox function, the following functions are provided: FddCRC FddHSBitScrambling FddTrCHCoding FddTurboDecoding FddConvolutionalDecoding FddHSHarq FddHSHarqRecovery FddEHarq FddEHarqRecovery FddPhyChSegmentation FddPhyChInterleaving FddPhyChDeinterleaving FddConstellationRearranging FddConstellationDearranging FddDLModulation FddDLDemodulation FddULModulation FddULDemodulation FddSpreading FddDespreading FddScrambling FddDescrambling FddHSSCCHCoding FddHSSCCHCodingType3 FddHSSCCH FddHSHARQACKEncoder FddHSCQIEncoder FddEDCHCoding FddEDPCCHCoding FddERGCHCoding
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FddEHICHCoding FddEAGCHCoding FddHSDSCH FddHSDSCHDecode FddHSPDSCH FddHSPDSCHDecode FddFadingChan
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7.1
FddCRC
The FddCRC is the general CRC coding toolbox function which performs the CRC encoding/decoding of the transport block. Syntax: Encode: [crcOut] = FddCRC(transportBlockData,direction,polyId,mask), where direction must be 1 Decode: where [crcOut,status] = FddCRC(transportBlockData,direction,polyId,mask), direction must be 0
Input transportBlockData
Range --
Description The input transport data block for the CRC encoding/decoding. Specifies the encoding/decoding operation. 0 = Decode 1 = Encode. Specifies the 8, 12, 16 or 24 bit CRC. The mask value used in CRC attachment method 2 for HSSCCH_less_mode operation Description The CRC encoded/decoded transport data block. Only for Decoding CRC error status: 0 = Pass 1 = Fail
direction
0 or 1
polyId
0, 1, 2 or 3
mask
--
Output crcOut
Range --
status (Only for Decoding)
0 or 1
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Description: The FddCRC toolbox function performs the CRC encoding/decoding of the input transport data block. The transport block can be a row or a column vector. The parameters direction and polyId specifies the encoding/decoding and the CRC polynomial for 8, 12, 16 or 24 bit CRC respectively. For encoding, the function returns the data block and the appended CRC in a single vector.The function supports CRC attachment method 2 for HS-SCCH_less_mode operation. This is provided by the optional parameter 'mask'. For decoding, the CRC is removed and the data block is returned. The optional output 'status' provides an indication of the CRC error.
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7.2
FddHSBitScrambling
The FddHSBitScrambling performs the bit scambling operation specified for the High Speed Downlink Shared Channel (HS-DSCH). Syntax: [bitsOut]=FddHSBitScrambling(bitsIn)
Input bitsIn Range -Description The CRC encoded transport data block.
Output bitsOut
Range --
Description The bitscrambled CRC encoded transport data block.
Description: This toolbox function performs the bit scrambling operation for the HS-DSCH channel. The input data block can be either a row or a column vector.
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7.3
FddTrCHCoding
The FddTrCHCoding toolbox function performs the channel coding on the uplink/ downlink. Syntax: [trChCodedData]= FddTrCHCoding(dataIn,code,codeRate)
Input dataIn
Range --
Description The data bits after the CRC coding and bit scrambling, if any.. Specifies the Turbo/ Convolutional coding. 0 = Convolutional 1 = Turbo Specifies the coderate of the convolutional coding.
code
0 or 1
codeRate
2 or 3
Output trChCodedData
Range --
Description The output data block after the Turbo/Convolutional coding.
Description: This function performs the channel coding operation on the uplink/ downlink transport channel. It supports the Turbo coding (with a fixed coderate of 1/3) and the Convolutional coding (coderates of 1/2 or 1/3). For the turbo coding, there is no need to specify the coderate. If the input block length is greater than the maximum block size (504 for convolutional coding, and 5114 for turbo coding) then code block segmentation will be performed before coding, with zero padding if necessary.The code blocks after segmentation are of the same size. If the number of bits input to the segmentation stage is not a multiple of the number of code blocks, filler bits are added to the beginning of the first block. If turbo coding is selected and the block size < 40, filler bits are added to the beginning of the code block. The filler bits are transmitted and they are always set to 0.
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7.4
FddTurboDecoding
The FddTurboDecoding toolbox function performs the turbo decoding on the uplink/downlink transport channel. Syntax: [bitsOut] = FddTurboDecoding(bitsIn,iterations,threshold,amplitude,noise) [bitsOut]= FddTurboDecoding(bitsIn,iterations,threshold,amplitude,noise,outLength)
Input bitsIn iterations threshold (optional) amplitude (optional) noise (optional) outLength (optional)
Range -integer > 0 ---integer > 0
Description The turbo coded data bits. Specifies the number of decoding iterations to run. Specifies the input signal threshold. The input signal amplitude. The noise variance. Specifies the output data length, excluding the filler bits.
Output bitsOut
Range --
Description The turbo decoded output data block.
Description: This toolbox function performs the turbo decoding operation on the uplink/downlink transport channel. It supports the turbo coding with a fixed coderate of 1/3. The decoder can calculate the signal paramaters (input threshold, signal amplitude and noise variance) automatically or these can be specified by the user as the optional parameters. Note that during turbo coding if the number of bits input to the segmentation is not a multiple of the number of code blocks filler bits are added to the beginning of the first block before segmentation and coding. Also if the number of bits input < 40, filler bits are added to the beginning of the code block before coding. Hence the
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output of the turbo decoding function, by default, will also have the padded zeros at the begining of the output. This has to be taken into account while analysing the result of the turbo decoding. The extra padded zeros can be removed by specifying the optional "outLength" parameter which must be the input block size to the turbo coder on the Tx side. If the 'outLength' is specified, the decoder outputs the decoded block after removing the initial padded filler bits, if any, obtained after the turbo decoding operation. See 25.212 Section 4.2.2.2 Code block segmentation for more details.
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7.5
FddConvolutionalDecoding
The FddConvolutionalDecoding toolbox function performs the convolutional decoding on the uplink/downlink transport channel. Syntax: [bitsOut]= FddConvolutionalDecoding(bitsIn,rate,quantBits,threshold,amplitude,quantStep)
Input bitsIn
Range --
Description The convolutional coded data block. Specifies the coderate: 2 = coderate of 1/2 3 = coderate of 1/3. Specifies the number of quantisation bits used. Specifies the input signal threshold. The input signal amplitude. Specifies the quantisation step.
rate
2 or 3
quantBits threshold (optional) amplitude (optional) quantStep (optional)
integer>1 ----
Output bitsOut
Range --
Description The convolutional decoded output data block.
Description: This function performs the convolutional decoding for rates = 1/3 & 1/2 on the uplink/downlink. The decoder can calculate the signal paramaters (input threshold, signal amplitude and quantisation step) automatically or these can be specified by the user as the optional parameters. Note that during convolutional coding if the number of bits input to the segmentation, Xi, is not a multiple of the number of code blocks, Ci, filler bits are added to the beginning of the first block before segmentation. Hence the output of the convolutional decoding function will also have the padded zeros at the begining of the output. This has to be taken into account while analysing the result of the convolutional decoding.
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7.6
FddHSHarq
The FddHSHarq toolbox function performs the Hybrid ARQ encoding on the HSDSCH channel. Syntax: [harqCodedData]=HarqEncoding(dataIn,phyChCapacity,sysPriority, rvParameter,modulation,virtBufCapacity).
Input dataIn phyChCapacity sysPriority
Range --0 or 1 0 or 1 for 16QAM and 64QAM 0,1,2 or 3 for QPSK 0,1 or 2
Description The output data block after the Turbo/Convolutional coding. The physical channel capacity of the high speed channel. Specifies the systematic priority.
rvParameter
Specifies the redundancy version.
modulation
Specifies the modulation scheme. 0 = QPSK, 1 = 16QAM, 2 = 64QAM Specifies the virtual buffer capacity.
virtBuffCapacity
--
Output harqCodedData
Range --
Description The output data block after the harq encoding.
Description: This function offers the hybrid ARQ functionality, which matches the number of bits at the output of the channel coder to the total number of bits of the HS-PDSCH set to which the HS-DSCH is mapped. The hybrid ARQ functionality is controlled by the redundancy version parameters. The exact set of bits at the output of the hybrid ARQ functionality depends on the number of input bits, the number of output bits, and the RV parameters. The phyChCapacity parameter specifies the output data length. Note that the phyChCapacity must be an integer multiple of the bits/symbol. The input block length must be an integer multiple of 3.
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7.7
FddHSHarqRecovery
The FddHSHarqRecovery toolbox function performs the Hybrid ARQ recovery on the HS-DSCH channel. Syntax: [bitsOut]=FddHSHarqRecovery(bitsIn,codedBlockLength,sysPriority, rvParameter,modulation,virtBufCapacity).
Input bitsIn codedBlockLength sysPriority
Range -+ve integer 0 or 1 0 or 1 for 16QAM/ 64QAM 0,1,2 or 3 for QPSK 0 ,1 or 2
Description The Hybrid ARQ encoded data. The channel coded data block length (Output length). Specifies the systematic priority.
rvParameter
Specifies the redundancy version.
modulation
Specifies the modulation scheme. 0 = QPSK, 1 = 16QAM, 2 = 64QAM. Specifies the virtual buffer capacity.
virtBuffCapacity
--
Output bitsOut
Range --
Description The recovered transport channel coded block.
Description: This function offers the hybrid ARQ recovery functionality, which matches the total number of bits of the HS-PDSCH set to which the HS-DSCH is mapped to the number of bits at the output of the channel coder. The hybrid ARQ recovery functionality is controlled by the redundancy version parameters. The exact set of bits at the output of the hybrid ARQ recovery functionality depends on the number of input bits, the number of output bits, and the RV parameters. The codedBlockLength parameter specifies the output data length. The codedBlockLength must be an integer multiple of 3.
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7.8
FddEHarq
The FddEHarq toolbox function performs the Hybrid ARQ encoding on the Enhanced Data Channel. Syntax: [harqCodedData]= FddEHarq(dataIn,phyFrameCapacity,rvParameter)
Input dataIn phyFrameCapacity rvParameter
Range --0,1,2 or 3
Description The output data block after the channel coding. Secifies the physical channel capacity of the E-DCH Specifies the E-DCH RV Index.
Output harqCodedData
Range --
Description The output data block after the harq encoding.
Description: This function provides the hybrid ARQ functionality, which matches the number of bits at the output of the channel coder to the total number of bits of the E-DPDCH set to which the E-DCH transport channel is mapped. The hybrid ARQ functionality is controlled by the redundancy version parameters. The phyFrameCapacity parameter specifies the output data length.
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7.9
FddEHarqRecovery
The FddEHarqRecovery toolbox function performs the Hybrid ARQ recovery on the Enhanced Data Channel. Syntax: [bitsOut] = FddEHarqRecovery(softBitsIn,outputBlockLength,rvParameter)
Input softBitsIn outputBlockLenght rvParameter
Range --0,1,2 or 3
Description The Harq coded soft bits. Secifies the physical channel capacity of the E-DCH Specifies the E-DCH RV Index.
Output bitsOut
Range --
Description The recovered transport coded data block.
Description: This function provides the HSUPA hybrid ARQ recovery functionality, It recovers the bits (channel code block) that would have been input to the forward rate matching stage. The hybrid ARQ functionality is controlled by the redundancy version parameters. The outputBlockLength parameter specifies the output data length.
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7.10 FddPhyChSegmentation The FddPhyChSegmentation toolbox function performs the physical channel segmentation of the transport channel. Syntax: [dataOut] = FddPhyChSegmentation(bitsIn,phyChannels)
Input bitsIn
Range --
Description The output data block after the channel coding operations. If a scalar which is less than the length of bitsIn then, phyChannels: The number of physical channels to equally segment the data across
phyChannels
Integer value > 0 or The vector of individual channel capacities
otherwise, phyChannels: A vector representing the frame capacities of the set of physical channels. If the length of the input is less than the total channel capacity then the input is zero padded prior to segmentation.
Output dataOut
Range --
Description The cell array whose columns represent the individual channels.
Description: This toolbox function divides the channel coded bits into the different physical channels. For HSDPA, all the physical channels have the same capacity, hence the parameter of the function while using for HSDPA transport channels is the number of channels. The function outputs a cell array with each row element representing an individual channel. For HSUPA, the channel capacities of the channels can be different, hence for HSUPA transport channels the parameter to the function is the channel capacities of the channels as a vector. If the length of the input is less than the total channel capacity then the input is zero padded prior to segmentation. An error is returned if the total channel capacity is less than the input length.
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7.11 FddPhyChInterleaving The FddPhyChInterleaving toolbox function performs the physical channel interleaving operation in the Uplink/Downlink. Syntax: [interleavedData] = FddPhyChInterleaving(dataIn,modulation)
Input dataIn
Range --
Description The input data cell array or matrix. 0 = BPSK/QPSK 1 = 16QAM 2 = 64QAM 3 = 4PAM The default value is 0.
modulation (optional)
0, 1, 2 or 3 (Default = 0)
Output interleavedData
Range --
Description The cell array or matrix whose columns represent the individual channels.
Description: This toolbox function performs the channel interleaving in the uplink/ downlink transport channel. The function input can be either a cell array or matrix, whose columns represent the individual channels. The output format will be the same as the input i.e. if the input is a cell array, the output will also be a cell array. The colums of the matrix or cell array represent the individual channels. Allowed modulation types are QPSK/16QAM/64QAM for HSDPA and BPSK/ 4PAM for HSUPA. For 16QAM, the input channel lengths must be 1920, and for 64QAM the input channel lengths must be 2880.
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7.12 FddPhyChDeinterleaving The FddPhyChDeinterleaving toolbox function performs the physical channel deinterleaving operation in the Uplink/Downlink. Syntax: [dataOut] = FddPhyChDeinterleaving(dataIn,modulation)
Input dataIn
Range --
Description The input data cell array or matrix. 0 = BPSK/QPSK 1 = 16QAM 2 = 64QAM 3 = 4PAM The default value is 0.
modulation (optional)
0, 1, 2 or 3
Output dataOut
Range --
Description: This toolbox function performs the channel deinterleaving in the uplink/downlink transport channel. The function input can be either a cell array or matrix, whose columns represent the individual channels. The output format will be the same as the input i.e. if the input is a cell array, the output will also be a cell array. The colums of the matrix or cell array represent the individual channels.
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7.13 FddConstellationRearranging The FddConstellationRearranging toolbox function performs the constellation rearranging specified for the High Speed Downlink Shared Channel (HS-DSCH). Syntax: [out]=FddConstellationRearranging(symbolsIn,modulation,constVersion,logical)
Input symbolsIn modulation
Range --
Description The input data cell array or matrix. 0 = QPSK 1 = 16QAM 2 = 64QAM The vector of constellation version values for all the channels. Specifies the input data type: 0 = Logical 1 = Signed Default is 0.
0, 1 or 2
constVersion
0,1,2, or 3
logical (optional)
0 or 1
Output out
Range --
Description: This toolbox function performs the constellation rearrangement operation specified for the 16-QAM and 64-QAM modulation schemes for the High Speed Downlink Shared Channel. The input data can be either a matrix or a cell array with the columns representing the individual channels.The function can take in either logical values or the signed values. The constellation rearrangement is only applicable to the 16-QAM and 64-QAMmodulation schemes. The default value for logical is 0.
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7.14 FddConstellationDearranging The FddConstellationDearranging toolbox function performs the constellation dearranging for the High Speed Downlink Shared Channel (HS-DSCH) in the receive direction. Syntax: [out]=FddConstellationDearranging(symbolsIn,modulation,constVersion, logical)
Range --
Description The input data cell array or matrix. 0 = QPSK 1 = 16QAM 2 = 64QAM The vector of constellation version values for all the channels. Specifies the input data type: 0 = Logical 1 = Signed Default is 0.
0, 1 or 2
constVersion
0,1,2, or 3
logical (optional)
0 or 1
Output out
Range --
Description: This toolbox function performs the constellation dearrangement operation for the 16-QAM/64QAM modulation scheme for the High Speed Downlink Shared Channel. The input data can be either a matrix or a cell array with the columns representing the individual channels. The constellation dearrangement functionality is transparent for the QPSK modulation scheme. The default value for logical is 0.
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7.15 FddDLModulation The FddDLModulation toolbox function performs the downlink symbol modulation and mapping. Syntax: [symbolsOut]= FddDLModulation(bitsIn,modulation)
Input bitsIn modulation
Range --
Description The input data cell array or matrix. 0 = QPSK 1 = 16QAM 2 = 64QAM
0, 1 or 2
Output symbolsOut
Range --
Description: This toolbox function performs the symbol modulation in the downlink physical channel. The input can be either a cell array or a matrix.% This toolbox function maps the input bits to the symbols according to the modulation scheme (QPSK , 16QAM or 64QAM). The input can be either a cell array (1xN) or a matrix (MxN), where N is the number of channels i.e. columns have data corresponding to the individual channels.
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7.16 FddDLDemodulation The FddDLDemodulation toolbox function performs the downlink symbol demodulation and demapping. Syntax: [bitsOut]= FddDLDemodulation(symbolsIn,modulation)
Range --
Description The input data cell array or matrix. 0 = QPSK 1 = 16QAM 2 = 64QAM
0, 1 or 2
Output bitsOut
Range --
Description: This toolbox function performs the symbol demodulation in the downlink physical channel. The input can be either a cell array or a matrix.
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7.17 FddULModulation The FddULModulation toolbox function performs the uplink symbol modulation and the optional IQ mapping. Syntax: [symbolsOut]= FddULModulation(bitsIn,modulation,iqed)
Input bitsIn modulation
Range -0 or 1
Description The input data cell array or matrix. 0 = BPSK 1 = 4PAM 1=I channel j = Q channel
iqed (optional)
1 ,,j
Output symbolsOut
Range --
Description: This toolbox function performs the symbol modulation in the uplink physical channel. The input can be either a cell array or a matrix. This function performs the BPSK/4PAM modulation and the optional IQ mapping in the uplink. If the iqed parameter is not specified, only BPSK/4PAM modulation is done.
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7.18 FddULDemodulation The FddULDemodulation toolbox function performs the uplink symbol demodulation and the optional IQ demapping. Syntax: [bitsOut]= FddULModulation(symbolsIn,modulation,iqed)
Range -0 or 1
Description The input data cell array or matrix. 0 = BPSK 1 = 4PAM 1=I channel j = Q channel
iqed (optional)
1 ,,j
Output bitsOut
Range --
Description: This function performs the BPSK/4PAM demodulation and the optional IQ demapping in the uplink physical channel. If the iqed parameter is not specified, only BPSK/4PAM demodulation is done. The input can be either a cell array or a matrix.
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7.19 FddSpreading The toolbox function FddSpreading spreads the coded symbols depending on the spreading factor and the spreading code number. The function input can be a single channel or multiple channels in either matrix or cell array format. In both cases, the columns represent the individual channels. The function returns a cell array by default. matrixOut is an optional parameter which when set to 1 will cause the function to output a matrix instead of the cell array, by padding with zeros if necessary. Syntax: [out] = FddSpreading(data,spreadFactor,spreadCode,matrixOut)
Input data spreadFactor spreadCode matrixOut
Range -1,2,4,8,16,32,64,128 ,256 or 512 0 ... (spreadFactor-1) 0 or 1
Description The input coded symbols. The spreading factor. Selects the particular spreading code. When set to 1, the function outputs a matrix, else outputs a cell array.
Output out
Range --
Description Spread chips resulting from spreading the input block of data.
Description: This function spreads the coded symbols depending on the spreading factor and the spreading code number input vectors, which must be of length equal to the number of channels. The function input can be a single channel or multiple channels in either matrix or cell array format. For a matrix, each column represents a single channel. For a cell array, each row element represents a single channel. A vector input will be treated as a single channel. The function will return the same type of output (cell array or matrix) as the input if the parameter matrixOut is not set to 1. When matrixOut is set to 1, the output will always be a matrix, even if the input is a cell array of different lengths or the spread channels are of different lengths (due to different spreading factors or different input channel lengths). In this case, zero padding will be added to the end of each channel to even out the channel lengths.
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7.20 FddDespreading The FddDespreading toolbox function performs the despreading of the descrambled data. Syntax: [symbolsOut]= FddDespreading(chipsIn,spreadFactor,spreadCode,matrixOut)
Input chipsIn spreadFactor
Range -2^x where x is 0 to 9
Description The input data vector. Specifies the spreading factor used. Specifies the spreading code used. Specifies whether the output should be a matrix instead of the default cell array.
spreadCode matrixOut (optional)
0 to spreadFactor - 1
0 or 1
Output symbolsOut
Range --
Description: This function despreads the descrambled chips depending on the spreading factor and the spreading code input vectors, which must be of length equal to the number of channels. The function returns a cell array by default, however matrixOut is an optional parameter which when set to 1 will cause the function to output a matrix instead of the cell array, padding with zeros if necessary. The output symbols are normalised by the spreading factor.
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7.21 FddScrambing The toolbox function FddScrambling performs scrambling in the Uplink/Downlink. Syntax: [out] = FddScrambling(data,direction,code,scramOffset)
Input data direction code scramOffset
Range -0,1 0...38399 0...38399
Description The spread and summed baseband signal. 0(Uplink), 1(Downlink). The valid scrambling code. The offset to the scrambling sequence.
Output out
Range --
Description The output is a complex data block having the length of the input
Description: Performs scrambling in the Uplink/Downlink. The scramOffset is an optional parameter to offset the scrambling sequence, with a default value of 0.
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7.22 FddDescrambling The FddDescrambling toolbox function performs the descrambling of the chips. Syntax: [descrambledOut]=FddDescrambling(dataIn,direction,scrambCode,scramOffset)
Input dataIn direction
Range --
Description The input complex, baseband data. Specifies the direction. 0(Uplink),1(Downlink) Specifies the scrambling code. Specifies the offset to the scrambling sequence.
0 or 1 0 to 38399 0 to 38399
scrambCode scramOffset
Output descrambledOut
Range --
Description The row or column vector having the descrambled data.
Description: This function performs descrambling in the Uplink/Downlink. The scramOffset is an optional parameter to offset the scrambling sequence, with a default value of 0.
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7.23 FddHSSCCHCoding The toolbox function FddHSSCCHCoding performs the channel coding operation on the High Speed Shared Control Channel. Syntax: [hsscchCodedBits,codingValues] = FddHSSCCHCoding(config)
Input config
Range --
Description Specifies the channel configuration values in the form of a structure.
Output hsscchCodedBits
Range --
Description A HS-SCCH coded block of size one sub frame, containing the coded data bits. This is the structure with the output from the intermediate channel coding stages.
codingvalues
--
Description: The function performs the channel coding of the High Speed Shared Control Channel. The channel configuration input must be a structure with the following fields as shown in the example below. config.codeGroup=10; config.codeOffset=1; config.constellationVersion=0; config.harqProcessID=0; config.modulationScheme=1; config.newData=1; config.redundancyVersion=3; config.systematicPriority=1; config.transportBlockSize=3202; config.transportBlockSizeID=0; config.ueID=0; config.virtualBufferCapacity=7200;
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7.24 FddHSSCCHCodingType3 The toolbox function FddHSSCCHCodingType3 performs the channel coding operation on the High Speed Shared Control Channel. Syntax: [hsscchCodedBits,codingValues] = FddHSSCCHCodingType3(config)
Input config
Range --
Description Specifies the channel configuration values in the form of a structure.
Output hsscchCodedBits
Range --
Description A HS-SCCH coded block of size one sub frame, containing the coded data bits. This is the structure with the output from the intermediate channel coding stages.
codingvalues
--
Description: The function performs the channel coding of the High Speed Shared Control Channel Type 3. The channel configuration input must be a structure with the following fields as shown in the example below. config.codeGroup config.codeOffset config.constellationVersion config.harqProcessID config.modulationScheme config.newData config.redundancyVersion config.systematicPriority config.transportBlockSize config.transportBlockSizeID config.ueID config.virtualBufferCapacity config.modulationScheme2 config.transportBlockSize2 config.transportBlockSizeID2
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config.redundancyVersion2 config.systematicPriority2 config.constellationVersion2 config.w2index config.trBlocks config.UEConfiguredFor64QAM
The function returns two outputs: 1. The HS-SCCH coded bits for a subframe 2. A structure with the output from the intermediate HS-SCCH Type3 coding stages: mux (X1) mux (X2) UE specific CRC attachment (Y) channel coding 1 (Z1) channel coding 2 (Z2) rate matching 1 (R1) rate matching 2 (R2) UE specific masking (S1)
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7.25 FddHSSCCH The toolbox function FddHSSCCH returns the high speed shared control channel chips. Syntax: [chipsout] = FddHSSCCH(CONFIG) If non-MIMO mode i.e. HS-SCCH Type 1 encoding
Input Range Description
CONFIG is the input configuration structure with the fields as below: codeGroup codeOffset harqProcessID modulationScheme constellationVersion redundancyVersion systematicPriority transportBlockSize transportBlockSizeID ueID newData HSSCCHChannel scramblingCode NSubframe UEConfiguredFor64QAM (optional) Output chipsout Integer >= 0 Integer >= 0 0, 1 or 2 0, 1, 2 or 3 0, 1, 2 or 3 0 or 1 Integer > 0 Integer > 0 0...65535 0 or 1 Integer> = 0 Integer >= 0 0 or 1 The code group number. The offset to the first code. The harq process identifier. 0 (QPSK), 1 (16QAM), 2 (64QAM) The constellation version. 0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM) The systematic priority indicator. The transport block size. The transport block size ID. The UE ID The new data indicator. 0 (False) or 1 (True) The HS-SCCH channel number. The valid scrambling code. The subframe number. 0 (False) Default or 1(True)
Range -
Description The HS-SCCH channel chips.
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If MIMO mode i.e. HS-SCCH Type 3 encoding

Input Range Description
CONFIG is the input configuration structure with the fields as below: codeGroup codeOffset harqProcessID modulationScheme constellationVersion redundancyVersion systematicPriority transportBlockSize transportBlockSizeID ueID w2index trBlocks HSSCCHChannel scramblingCode NSubframe modulationScheme2 (if secondary block present) constellationVersion2 (if secondary block present) redundancyVersion2 (if secondary block present) systematicPriority2 (if secondary block present) transportBlockSize2 (if secondary block present) Integer >= 0 Integer >= 0 0, 1 or 2 0, 1, 2 or 3 0, 1, 2 or 3 0 or 1 Integer > 0 Integer > 0 0...65535 0, 1, 2 or 3 1 or 2 Integer> = 0 Integer >= 0 0, 1 or 2 The code group number. The offset to the first code. The harq process identifier. 0 (QPSK), 1 (16QAM), 2 (64QAM) The constellation version. 0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM) The systematic priority indicator. The primary transport block size. The primary transport block size ID. The UE ID The precoding weight index for MIMO transmission. The number of active tranport blocks. The HS-SCCH channel number. The valid scrambling code. The subframe number. 0 (QPSK), 1 (16QAM), 2 (64QAM)
0, 1, 2 or 3
The constellation version. 0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM) The systematic priority indicator. The secondary transport block size.
0, 1, 2 or 3
0 or 1
Integer > 0

Input transportBlockSizeID2 (if secondary block present) Output chipsout Range Integer > 0 Description The secondary transport block size ID. Description The HS-SCCH channel chips.
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Range -
The function can also perform just the physical channel processing stages assuming the input is the HS-SCCH encoded bits. In this case, use the syntax given below: [chipsout] = FddHSSCCH(CONFIG, codedbits)
Input
Range
Description
CONFIG is the input configuration structure with the fields as below: HSSCCHChannel scramblingCode NSubframe Integer> = 0 Integer >= 0 The HS-SCCH channel number. The valid scrambling code. The subframe number.
codedbits
The HS-SCCH channel encoded bits. Description The vector of HS-SCCH chips.
Output chipsout
Range -
Description: The toolbox function FddHSSCCH generates the high speed shared control channel for a subframe. The function can either calculate the chips from the channel configuration, or alternatively it can process the encoded HS-SCCH bits to generate the chips. [CHIPSOUT] = FddHSSCCH(CONFIG) generates the HS-SCCH chips for a subframe for the configuration specified by CONFIG. [CHIPSOUT] = FddHSSCCH(CONFIG,CODEDBITS) generates the HS-SCCH chips for a subframe by performing the physical channel processing on the encoded HS-SCCH bits. The processing stages include the modulation, spreading and
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scrambling. The encoded HS-SCCH bits can be generated by FddHSSCCHCoding for non MIMO mode and FddHSSCCHCodingType3 for MIMO mode respectively.
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7.26 FddHSHARQACKEncoding The toolbox function FddHSHARQACKEncoder performs the coding of the HARQ-ACK message bits for the HS-DPCCH. Syntax: [codedbits] = FddHSHARQACKEncoder(CONFIG)
Input CONFIG
Range -
Description The input configuration structure with the fields as described below: The vector with one or two HARQACK Messages: 0 (NACK), 1 (ACK), 2(PRE), 3(POST) MIMO indicator. Must be set to 1 for MIMO and 0 when Secondary_Cell_Active is 1. Only required when Secondary_Cell_Active is 1 and only one HARQACK message is present. Used for signalling secondary serving cell. 1 = secondary cell active, 0 = primary cell active (default).
HARQACK
UEConfiguredForMIMO
1...38400
secServingCell (optional)
0 or 1
Output codedbits
Range --
Description The encoded HS-DPCCH HARQACK message.
Description: This function generates the coded HARQ-ACK message bits for the HS-DPCCH channel.
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7.27 FddHSCQIEncoding The toolbox function FddHSCQIEncoder performs the coding of the composite PCI and CQI information. Syntax: [codedbits] = FddHSCQIEncoder(CONFIG)
Input CONFIG CQI
Range -
Description The input configuration structure with the fields as described below: The CQI value vector with one or two values. The PCI info (0:3). Only required when UE is configured in MIMO mode. Specifies the CQI Type when UE is configured in MIMO mode. -1 = Disable MIMO mode, 0 = Type A, 1 = Type B.
PCI(optional)
1...38400
CQIType(optional)
-1, 0 or 1
Output codedbits
Range --
Description The encoded HS-DPCCH HARQACK message.
Description: The FddHSCQIEncoder toolbox returns the coded channel quality indication (CQI) bits if UE is not configured in MIMO mode or the coded composite precoding control indication(PCI) and channel quality indication(CQI) bits if UE is configured in MIMO mode or the coded composite channel quality indication bits if Secondary_Cell_Active is 1. When UE is configured in MIMO mode, two types of CQI reports are supported by the UE. Type A CQI reports use values 0...255 and type B CQI reports use values 0..30 respectively. When Secondary_Cell_Active is 1, the composite CQI report consists of two individual reports from the serving HS-DSCH cell and secondary serving HSDSCH cell. Hence the CQI must be a vector with two values.
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7.28 FddEDCHCoding The toolbox function FddEDCHCoding takes a vector of bit data in input, and redundancy and frameCapacity scalar parameters and returns a vector of coded bits out with size frameCapacity. Syntax: [out] = FddEDCHCoding(input,redundancy,frameCapacity)
Input input
Range vector of bits {0,1}
Description The input data block to be encoded. The Redundancy Version to encode when performing the Hybrid-ARQ rate matching. the output block size, equal to the frame capacity of the set of EDPDCHs used to transmit the coded data.
redundancy
{0,1,2,3}
frameCapacity
1...38400
Output out
Range --
Description A coded block of size frameCapacity, containing the coded data.
Description: This function generates one subframe of the EDCH coded data bits.
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7.29 FddEDPCCHCoding The toolbox function FddEDPCCHCoding returns the complex values representing mapped data, 30 complex values per subframe i.e. 30 complex values per each element of the input vectors. Syntax: [out] =FddEDPCCHCoding(happy,rsn,etfci)
Input happy
Range {0,1}
Description The E-DCH happy bit value, or a vector of such values. Valid values are 0 and 1. The Retransmission Sequence Number, or a vector of such numbers. Valid values are 0, 1, 2 and 3. The E-TFCI (Transport Format Combination Indicator), or a vector of such indicators. Valid values are in the range 0 to 127.
rsn
{0,1,2,3}
etfci
0...127
Output out
Range --
Description 30 coded bits per subframe available at the input.
Description: This function generates one subframe of the EDPCCH coded data.
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7.30 FddERGCHCoding The toolbox function FddERGCHCoding returns the complex values representing mapped data, 20 values for each slot so either 60, 240 or 300 complex values depending on number of slots parameter. Syntax: [out] = FddERGCHCoding(rgComm,seqIndex,slots)
Input
Range
Description The relative grant vector. The Relative Grant command is mapped to the relative grant value as shown above for the Simulink Block input. The sequence index number. This is the range of the number of slots which also indicates the output length.
rgComm
{-1,0,+1}
seqIndex slots
0...31 {3,12,15}
Output
Range
Description Complex values representing mapped data, 20 values for each slot so either 60, 240 or 300 complex values depending on number of slots parameter.
out
--
Description: This function generates one subframe of the ERGCH coded data.
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7.31 FddEHICHCoding The toolbox function FddEHICHCoding returns the complex values representing mapped data, 20 values per slot so either 60 or 240 complex values depending on the 'Slots' parameter. Syntax: [out] = FddEHICHCoding(input,seqIndex,slots)
Input
Range
Description The vector containing the HARQ acknowledgement indicator values. +1 = ACK 0 = NACK (RLSs not containing the serving E-DCH cell. -1 = NACK (RLS containing the serving E-DCH cell. The sequence index number. This is the range of the number of slots which also indicates the output length.
input
{-1,0,+1}
seqIndex slots
0...31 {3,12}
Output
Range
Description Complex values representing mapped data, 20 values for each slot so either 60 or 240 complex values depending on the number of slots parameter.
out
--
Description: This function generates one subframe of the EHICH coded complex data symbols.
236
7.32 FddEAGCHCoding The toolbox function FddEAGCHCoding returns the complex values representing mapped data, 30 complex values per subframe i.e. 30 complex values per each element of the vectors "Absolute Grant Values" and "Absolute Grant Scope". Syntax: [codedData,codingValues]=FddEAGCHCoding(ERNTI,AGValue,AGScope)
Input ERNTI
Range 0...65535
Description Enhanced Radio Network Identifier. The Absolute Grant Values. These are the indices corresponding to the values and can be input as scalar or vector. This scalar or vector input indicates the Absolute Grant Scope(s). 1 = Per HARQ process 0 = All HARQ processes.
AGValue(s)
0...31
AGScope(s)
{0,1}
Output
Range
Description Complex values representing mapped data, 30 complex values per subframe i.e. 30 complex values per each element of the vectors at inputs 1 and 2. The structure having the outputs of the ID specific CRC attachment, channel coding and ratematching stages.
codedData
--
codingValues
--
Description: This function performs the EAGCH encoding operation. The function has two outputs: 1. The EAGCH coded subframe complex symbols. 2. The structure containing the outputs of the ID specific CRC attachment, channel coding and rate matching stages.
237
7.33 FddHSDSCH The toolbox function FddHSDSCH returns the HSDSCH transport channel coded data. Syntax: [codedout] = FddHSDSCH(CONFIG,trBlock)
Input CONFIG codeGroup modulationScheme systematicPriority redundancyVersion virtualBufferCapacity modulationScheme2 (if secondary block present) systematicPriority2 (if secondary block present)
Range 0, 1 or 2 0 or 1 0, 1 or 2
Description The input configuration structure with the fields as below: The code group number. 0 (QPSK), 1 (16QAM), 2 (64QAM) The systematic priority indicator. 0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM) The virtual buffer capacity. 0 (QPSK), 1 (16QAM), 2 (64QAM)
0 or 1
The systematic priority indicator.
redundancyVersion2 (if secondary block present)
0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM)
trBlock
The input transport data block.
Output
Range
Description Complex values representing mapped data, 30 complex values per subframe i.e. 30 complex values per each element of the vectors at inputs 1 and 2.
codedData
--
238
Description: The toolbox function performs the HS-DSCH transport channel coding operations. This includes the crc coding, bit scrambling, code block segmentation, channel coding, and the Hybrid-ARQ operations. The function can accept one or two transport blocks and returns a vector or cell array respectively.
239
7.34 FddHSDSCHDecode The toolbox function FddHSDSCHDecode returns the HSDSCH transport channel decoded data. Syntax: [decodedout] = FddHSDSCHDecode(CONFIG,coded)
Input CONFIG codeGroup modulationScheme systematicPriority redundancyVersion virtualBufferCapacity modulationScheme2 (if secondary block present)
Range 0, 1 or 2 0 or 1 -
Description The input configuration structure with the fields as below: The code group number. 0 (QPSK), 1 (16QAM), 2 (64QAM) The systematic priority indicator. 0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM) The virtual buffer capacity.
0, 1 or 2
0 (QPSK), 1 (16QAM), 2 (64QAM)
systematicPriority2 (if secondary block present)
0 or 1
The systematic priority indicator.
redundancyVersion2 (if secondary block present)
0, 1, 2 or 3 (QPSK) or 0,1 (16QAM & 64QAM)
coded Output decodedout Range --
The HS-DSCH coded data. Description The recovered tranport block(s).
Description: The toolbox function performs the HS-DSCH transport channel decoding. Hybrid-ARQ rate recovery, channel decoding, code block desegmentation, bit descrambling and crc decoding operations. The function can accept one or two coded blocks and returns a vector or cell array respectively.
240
7.35 FddHSPDSCH The toolbox function FddHSPDSCH returns the physical channel coded chips. Syntax: [chipsout] = FddHSPDSCH(CONFIG,bitsin)
Input CONFIG codeGroup codeOffset modulationScheme constellationVersion virtualBufferCapacity scramblingCode NSubframe w2index (optional) modulationScheme2 (if secondary block present) constellationVersion2 (if secondary block present)
Range Integer >= 0 0, 1 or 2 0, 1, 2 or 3 -
Description The input configuration structure with the fields as below: The code group number. The offset to the first code. 0 (QPSK), 1 (16QAM), 2 (64QAM) The constellation version parameter. The virtual buffer capacity. The scrambling code number.
Integer > = 0 -1, 0, 1, 2 or 3
The subframe number The precoding weight index. 1(default) indicates non-MIMO transmission. 0 (QPSK), 1 (16QAM), 2 (64QAM) The constellation version parameter.
0, 1 or 2
0, 1, 2 or 3
bitsin
The input coded transport block(s). The columns represent the individual blocks if secondary transport block is present. Description The vector or matrix of HSPDSCH chips .
Output chipsout
Range -
241
Description: The toolbox function performs the HS-PDSCH channel coding. The encoding includes the physical channel segmentation, interleaving, constellation rearranging, physical channel mapping, spreading and scrambling operations.
242
7.36 FddHSPDSCHDecode The toolbox function FddHSPDSCHDecode returns the physical channel decoded bits for the high speed downlink shared channel. Syntax: [bitsout] = FddHSPDSCHDecode(CONFIG,chipsin)
Input CONFIG codeGroup codeOffset modulationScheme constellationVersion virtualBufferCapacity scramblingCode NSubframe w2index (optional) trBlocks modulationScheme2 (if secondary block present) constellationVersion2 (if secondary block present)
Range Integer >= 0 0, 1 or 2 0, 1, 2 or 3 Integer > = 0
Description The input configuration structure with the fields as below: The code group number. The offset to the first code. 0 (QPSK), 1 (16QAM), 2 (64QAM) The constellation version parameter. The virtual buffer capacity. The scrambling code number. The subframe number The precoding weight index. -1(default) indicates non-MIMO transmission. The number of transport blocks transmitted. 0 (QPSK), 1 (16QAM), 2 (64QAM) The constellation version parameter.
-1, 0, 1, 2 or 3
1 or 2
0, 1 or 2
0, 1, 2 or 3
chipsin
The received chips. The columns represent the individual antenna if MIMO transmission.

Output bitsout Range Description
243
The vector or cell array containing the coded transport blocks.
Description: The decoding includes MIMO reception, descrambling, despreading, physical channel demapping, constellation dearranging, deinterleaving, and physical channel desegmentation operations. Note that the MIMO reception is assuming no channel conditions.
244
7.37 FddFadingChan The toolbox function FddFadingChan implements the the multipath Rayleigh fading channel. Syntax: [chipsout] = FddFadingChan(CONFIG,chipsin)
Input chipsin CONFIG Speed Fc NTerms
Range
Description The input data chips
>0 >0 4, 8, 16, 32 or 64
The input configuration structure with the fields as below: Speed of mobile station in km/h The carrier frequency in Hz. No. of terms used to calculate Rayleigh fading waveform The .txt file specifying the number of paths, average delay and power of each multipath. Specifies the phase selection. Phase for the component weight generation. If Random PhaseMode selected, this parameter is ignored and a random phase is chosen. The fading channel time offset The input data rate Description The fading channel output chips.
Filename
User-defined or Random
PhaseMode
InitPhase
0<InitPhase<2pi
InitTime SampleRate Output chipsout
>= 0 Range -
Description: FddFadingChan returns the multipath Rayleigh fading channel filtered data in the complex vector CHIPSOUT. CHIPSIN is the input spread data and CONFIG is the fading channel configuration structure.
245
246
Appendix A: 3GPP Definitions Term

Acceptable Cell
Definition
This is a cell that the UE may camp on to make emergency calls. It must satisfy certain conditions.
Access Stratum SDU (Service Data Unit) Unit of data transferred over the access stratum SAP (Service Access Point) in the Core Network or in the User Equipment. Active mode Active Set ALCAP Allowable PLMN Available PLMN Average transmit power Average Transmitter Power Per Traffic Channel (dBm) Cable, Connector, and Combiner Losses (Transmitter) (dB) Cable, Connector, and Splitter Losses (Receiver) (dB) Camped on a cell "Active mode" is the state of a User Equipment when processing a call Set of radio links simultaneously involved in a specific communication service between an User Equipment and a UTRAN access point. Generic name for the transport signaling protocols used to set-up and tear-down transport bearers. This is a PLMN which is not in the list of forbidden PLMNs in the UE. This is a PLMN where the UE has found a cell that satisfies certain conditions. The average transmitter output power obtained over any specified time interval, including periods with no transmission. The mean of the total transmitted power over an entire transmission period. The combined losses of all transmission system components between the transmitter output and the antenna input (all losses in positive dB values). These are the combined losses of all transmission system components between the receiving antenna output and the receiver input. The UE is in idle mode and has completed the cell selection/reselection process and has chosen a cell. The UE monitors system information and (in most cases) paging information. Note that the services may be limited, and that the PLMN may not be aware of the existence of the UE within the chosen cell. A cell is a geographical area that can be identified by a User Equipment from a (cell) identification that is broadcast from one UTRAN Access Point. A data stream resulting from encoding and multiplexing of one or several transport channels. A Channel not dedicated to a specific UE. A "control channel" is a logical channel that carries system control information. A role an RNC can take with respect to a specific set of UTRAN access points. There is only one Controlling RNC for any UTRAN access point. The Controlling RNC has the overall control of the logical resources of its UTRAN access point's. The "coverage area" is the area over which a UMTS service is provided with the service probability above a certain threshold. A channel dedicated to a specific UE. A "downlink" is a unidirectional radio link for the transmission of signals from a UTRAN access point to a UE. Also in general the direction from Network to UE. The role an RNS can take with respect to a specific connection between a User Equipment and UTRAN. An RNS that supports the Serving RNS with radio resources when the connection between the UTRAN and the User Equipment need to use cell(s) controlled by this RNS is referred to as Drift RNS. The individual time interval between reading initial paging information for specific UE. This is the effective gain achieved using diversity techniques. This is the gain/loss factor (+ or -) brought by hand-off to maintain specified reliability at the cell boundary. The transfer of a users connection from one radio channel to another (can be the same or different cell). Hard handover is a category of handover procedures where all the old radio links in the UE are abandoned before the new radio links are established. This is a PLMN where the Mobile Country Code (MCC) and Mobile Network Code (MNC) of the PLMN identity are the same as the MCC and MNC of the IMSI. Idle mode is the state of User Equipment switched on but which does not have any established RRC connection. Rate of the user information, which must be transmitted over the Air Interface. For example, output rate of the voice codec. This information indicates if the UE needs to continue to read more paging information and eventually receive a page message. The paging occasion the UE uses as starting point for its DRX cycle. An "inter-cell handover" is a handover between different cells. An inter-cell handover requires network connections to be altered.
Cell Coded Composite Transport Channel (CCTrCH) Common Channel Control channel Controlling RNC
Coverage area Dedicated Channel Downlink Drift RNS
DRX cycle Explicit Diversity Gain (dB) Hand-off Gain/Loss (dB) Handover Hard Handover Home PLMN Idle mode Rate Initial paging information Initial paging occasion Inter-cell handover
Term
Interference Signal Code Power (ISCP) Intra-cell handover Iu Iub Iur Location Registration (LR) Logical Channel Logical Model
Definition
Given only interference power is received, the average power of the received signal after despreading to the code and combining. An "intra-cell handover" is a handover within one sector or between different sectors of the same cell. An intra-cell handover does not require network connections to be altered. Interconnection point between an RNC and a Core Network. It is also considered as a reference point. Interface between an RNC and a Node B. A logical interface between two RNC. Whilst logically representing a point to point link between RNCs, the physical realisation may not be a point to point link. The UE registers its presence in a registration area, for instance regularly or when entering a new registration area. A logical channel is an information stream dedicated to the transfer of a specific type of information over the radio interface. Logical Channels are provided on top of the MAC layer. A Logical Model defines an abstract view of a network or network element by means of information objects representing network element, aggregations of network elements, the topological relationship between the elements, endpoints of connections (termination points), and transport entities (such as connections) that transport information between two or more termination points.The information objects defined in the Logical Model are used, among others, by connection management functions. In this way a physical implementation independent management is achieved. Logical O&M is the signaling associated with the control of logical resources (channels, cells,) owned by the RNC but physically implemented in the Node B. The RNC controls these logical resources. A number of O&M procedures physically implemented in Node B impact on the logical resources and therefore require an information exchange between RNC and Node B. All messages needed to support this information exchange are classified as Logical O&M forming an integral part of NBAP. Localised Service Area. A LSA is an operator-defined area, for which specific access conditions apply. This may correspond to an area in which the Core Network offers specific services. A LSA may be defined within a PLMN or globally. Therefore, a LSA may offer a non-contiguous radio coverage. "Macro cells" are outdoor cells with a large cell radius. "Macro diversity" is a operation state in which a User Equipment simultaneously has radio links with two or more UTRAN access points for the sole aim of improving quality of the radio connection or providing seamless. This refers to the measure of average power at the maximum power setting. The peak power observed when operating at a given maximum output power. The highest value of the Power control setting which can be used. The aggregate maximum transmit power of all channels. The maximum power at the transmitter output for a single traffic channel. "Micro cells" are small cells. Mobile evaluated handover (MEHO) is a type of handover triggered by an evaluation made in the mobile. The mobile evaluates the necessity of handover based on the measured radio environment and based on criteria defined by the network. When the evaluation meets the handoff criteria the necessary information is sent from the mobile to the network. The network then decides on the necessity of the handover based on the reported evaluation result and other conditions, e.g. uplink radio environment and/or availability of network resources, the network may then execute the handover. A "Mobile Station" (MS) is an entity capable of accessing a set of UMTS services via one or more radio interfaces. This entity may be stationary or in motion within the UMTS service area while accessing the UMTS services, and may simultaneously serve one or more users. A relation between the mobile station and the UTRAN that is used to set-up, maintain and release the various physical channels. A logical node responsible for radio transmission / reception in one or more cells to/from the User Equipment. Terminates the Iub interface towards the RNC. Protocols between UE and the core network that are not terminated in the UTRAN. Paging is the act of seeking a User Equipment. The time instances where it is possible to receive initial paging information. The instantaneous power of the RF envelope which is not expected to be exceeded for [99.9%] of the time. In the uplink, a data stream that is transmitted on one physical channel. In the downlink, a data stream that is transmitted on one physical channel in each cell of the active set.
Logical O&M
LSA
Macro cells Macro diversity handover.
Maximum output Power Maximum peak power Maximum Power Setting Maximum Total Transmitter Power (dBm): Maximum Transmitter Power Per Traffic Channel (dBm) Micro cells Mobile evaluated handover
Mobile Station
Mobility Management Node B Non-Access Stratum Paging Paging occasions Peak Power Physical channel data stream
Term
Physical Channel Pico cells Power Setting Radio access bearer Radio Access Mode Radio Access Network Application Part Radio Access System Radio Bearer Radio frame
Definition
In FDD mode, a physical channel is defined by code, frequency and, in the uplink, relative phase (I/Q). In TDD mode, a physical channel is defined by code, frequency, and time-slot. "Pico cells" are cells, mainly indoor cells, with a radius typically less than 50 metres. The value of the control signal, which determines the desired transmitter, output Power. Typically, the power setting would be altered in response to power control commands. The service that the access stratum provides to the non-access stratum for transfer of user data between User Equipment and CN. Mode of the cell, FDD or TDD. Radio Network Signalling over the Iu. UTRA, GSM etc. The service provided by the RLC layer for transfer of user data between User Equipment and Serving RNC. A radio frame is a numbered time interval of 10 ms duration used for data transmission on the radio physical channel. A radio frame is divided into 15 time slots of 0.666 ms duration. The unit of data that is mapped to a radio frame (10 ms time interval) may also be referred to as radio frame The "radio interface" is the tetherless interface between User Equipment and a UTRAN access point. This term encompasses all the functionality required to maintain such interfaces A "radio link" is a logical association between single User Equipment and a single UTRAN access point. Its physical realization comprises one or more radio bearer transmissions. The procedure where a new radio link is added to the active set. The procedure where a radio link is removed from the active set. This equipment in the RNS is in charge of controlling the use and the integrity of the radio resources. Radio Network Signaling over the Iur Either a full network or only the access part of a UTRAN offering the allocation and the release of specific radio resources to establish means of connection in between an UE and the UTRAN. A Radio Network Temporary Identifier is an identifier for a UE when an RRC connection exists. It is e.g. used by the MAC protocol on common Transport Channels (RACH, FACH, PCH). Given only signal power is received, the average power of the received signal after despreading and combining The maximum gain of the receiver antenna in the horizontal plane (specified as dB relative to an isotropic radiator). Receiver noise figure is the noise figure of the receiving system referenced to the receiver input This is the signal level needed at the receiver input that just satisfies the required Eb/(No+Io). This is the PLMN on which the UE has performed a location registration successfully. A (NAS) registration area is an area in which the UE may roam without a need to perform location registration, which is a NAS procedure. Terminal devices capable of ODMA relay communications Relay or Seed that communicates with the UTRAN, in either TDD or FDD mode Relaylink is a communications link between two ODMA relay nodes. A "repeater" is a radio transceiver used to extend the transmission of a base station beyond its normal range. The ratio between the received energy per information bit to the total effective noise and interference power density needed to satisfy the quality objectives ODMA relay node where communications originate or terminate A point-to-point bi-directional connection between RRC peer entities on the UE and the UTRAN sides, respectively. An UE has either zero or one RRC connection "Seamless handover" is a handover without perceptible interruption of the radio connection A "sector" is a sub-area of a cell. All sectors within one cell are served by the same base station. A radio link within a sector can be identified by a single logical identification belonging to that sector. Deployed ODMA relay node with or without a display/keypad. This is the PLMN that has been selected by the non-access stratum, either manually or automatically A role an RNS can take with respect to a specific connection between an UE and UTRAN. There is one Serving RNS for each UE that has a connection to UTRAN. The Serving RNS is in charge of the RRC connection between a UE and the UTRAN. The Serving RNS terminates the Iu for this
Radio interface Radio link Radio link addition Radio link removal Radio Network Controller Radio Network Subsystem Application Part Radio Network Subsystem Radio Network Temporary Identifier (RNTI): Received Signal Code Power (RSCP): Receiver Antenna Gain (dBi) Receiver Noise Figure (dB): Receiver Sensitivity (dBm): Registered PLMN (RPLMN): Registration Area Relay Relay/Seed Gateway Relaylink Repeater Required Eb/(No+Io) (dB): Root Relay RRC Connection Seamless handover Sector
Seed Selected PLMN Serving RNS
Term
Signaling connection Signaling link Soft Handover SRNS Relocation Suitable Cell Test environment
Definition
An acknowledged-mode link between the user equipment and the core network to transfer higher layer information between the entities in the non-access stratum. Provides an acknowledged-mode link layer to transfer the MS-UTRAN signaling messages as well as MS - Core Network signaling messages (using the signaling connection Soft handover is a category of handover procedures where the radio links are added and abandoned in such manner that the UE always keeps at least one radio link to the UTRAN. The change of Iu instance and transfer of the SRNS role to another RNS. This is a cell on which an UE may camp. It must satisfy certain conditions A "test environment" is the combination of a test propagation environment and a deployment scenario, which together describe the parameters necessary to perform a detailed analysis of a radio transmission technology. A "traffic channel" is a logical channel which carries user information Transmission Time Interval is defined as the inter-arrival time of Transport Block Sets, i.e. the time it should take to transmit a Transport Block Set. The maximum gain of the transmitter antenna in the horizontal plane (specified as dB relative to an isotropic radiator Transport Block is defined as the basic unit passed down to L1 from MAC, for L1 processing. An equivalent term for Transport Block is "MAC PDU". Transport Block Set is defined as a set of Transport Blocks that is passed to L1 from MAC at the same time instance using the same transport channel. An equivalent term for Transport Block Set is "MAC PDU Set". Transport Block Set Size is defined as the number of bits in a Transport Block Set Transport Block Size is defined as the size (number of bits) of a Transport Block The channels offered by the physical layer to Layer 2 for data transport between peer L1 entities are denoted as Transport Channels. Different types of transport channels are defined by how and with which characteristics data is transferred on the physical layer, e.g. whether using dedicated or common physical channels A Transport Format is defined as a format offered by L1 to MAC for the delivery of a Transport Block Set during a Transmission Time Interval on a Transport Channel. The Transport Format constitutes of two parts one dynamic part and one semi-static part. A Transport Format Combination is defined as the combination of currently valid Transport Formats on all Transport Channels of an MS, i.e. containing one Transport Format from each Transport Channel. A Transport Format Combination Set is defined as a set of Transport Format Combinations to be used by an MS A Transport Format Combination Indicator is a representation of the current Transport Format Combination A label for a specific Transport Format within a Transport Format Set. A set of Transport Formats. For example, a variable rate DCH has a Transport Format Set (one Transport Format for each rate), whereas a fixed rate DCH has a single Transport Format UTRAN is a conceptual term identifying that part of the network which consists of RNCs and Node Bs between Iu an Uu An "uplink" is a unidirectional radio link for the transmission of signals from a UE to a base station, from a Mobile Station to a mobile base station or from a mobile base station to a base station URA updating is a family of procedures that updates the UTRAN registration area of a UE when a RRC connection exists and the position of the UE is known on URA level in the UTRAN A Mobile Equipment with one or several UMTS Subscriber Identity Modules(s). The UTRAN Registration Area is an area covered by a number of cells. The URA is only internally known in the UTRAN. A conceptual point within the UTRAN performing radio transmission and reception. A UTRAN access point is associated with one specific cell, i.e. there exists one UTRAN access point for each cell. It is the UTRAN-side end point of a radio link. The Radio interface between UTRAN and the User Equipment This is a PLMN, different from the home PLMN, where the MCC part of the PLMN identity is the same as the MCC of the IMSI.
Traffic channel Transmission Time Interval Transmitter Antenna Gain (dBi) Transport Block Transport Block Set
Transport Block Set Size Transport Block Size Transport channel
Transport Format
Transport Format Combination
Transport Format Combination Set Transport Format Combination Indicator (TFCI) Transport Format Identification (TFI) Transport Format Set Universal Terrestrial Radio Access Network Uplink
URA updating User Equipment UTRAN Registration Area (URA) UTRAN access point
Uu Visited PLMN of home country
Appendix B: 3GPP Abbreviations
Abbreviation
AAL AAL2 AAL5 ACCH ACIR ACK ACLR ACS AESA AI AICH ALCAP AP ARP ARQ AS ASC ASN.1 ATM AWGN BCCH BCFE BCH BER BID BLER BPSK BS BSC BSS BTS CCA CAA CB CBR CC CCCH CCH CCPCH CCTrCH CD CDA CDMA CFN CN CPICH CPCH CPCS ATM Adaptation Layer ATM Adaptation Layer type 2 ATM Adaptation Layer type 5 Associated Control Channel
Definition
Adjacent Channel Interference Ratio Acknowledgement Adjacent Channel Leakage Power Ratio Adjacent Channel Selectivity ATM End System Address Acquisition Indicator Acquisition Indication Channel Access Link Control Application Protocol Access preamble Address Resolution Protocol Automatic Repeat Request Access Stratum Access Service Class Abstract Syntax Notation One Asynchronous Transfer Mode Additive White Gaussian Noise Broadcast Control Channel Broadcast Control Functional Entity Broadcast Channel Bit Error Rate Binding Identity Block Error Rate Binary Phase Shift Keying Base Station Base Station Controller Base Station System Base Transceiver Station ControlCapacity Allocation Capacity Allocation Acknowledgement Cell Broadcast Constant Bit Rate Call Control Common Control Channel Control Channel Common Control Physical Channel Coded Composite Transport Channel Capacity Deallocation or Collision Detection Capacity Deallocation Acknowledgement Code Division Multiple Access Connection Frame Number Core Network Common Pilot Channel Common Packet Channel Common Part Convergence Sublayer
Abbreviation
CPS CRC CRNC CS CTCH CTDMA SCTP CW DC DCA DCCH DCH DHO DL DPCCH DPCH DPDCH DRNC DRNS DRX DS-CDMA DSCH DTCH DTX EIRP FACH FAUSCH FBI FCS FDD FDMA FEC FER FN FP GC GMSK GP GPRS GSM GTP HCS HHO HO IMA IMSI IP IP-M ISCP ITU JD JP kbps Common Part Sublayer Cyclic Redundancy Check
Definition
Controlling Radio Network Controller Circuit Switched Common Traffic Channel Code Time Division Multiple Access S Common Transport Protocol CHECK WITH wg3 Continuous Wave (unmodulated signal) Dedicated Control (SAP) Dynamic Channel Allocation Dedicated Control Channel Dedicated Channel Diversity Handover Downlink (Forward Link) Dedicated Physical Control Channel Dedicated Physical Channel Dedicated Physical Data Channel Drift Radio Network Controller Drift RNS Discontinuous Reception Direct-Sequence Code Division Multiple Access Downlink Shared Channel Dedicated Traffic Channel Discontinuous Transmission Equivalent Isotropic Radiated Power Forward Access Channel Fast Uplink Signaling Channel Feedback Information Frame Check Sequence Frequency Division Duplex Frequency Division Multiple Access Forward Error Correction Frame Erasure Rate, Frame Error Rate Frame Number Frame Protocol General Control (SAP) Gaussian Minimum Shift Keying Guard Period General Packet Radio System Global System for Mobile communications GPRS Tunneling Protocol Hierarchical Cell Structure Hard Handover Handover Inverse Multiplexing on ATM International Mobile Subscriber Identity Internet Protocol IP Multicast Interference Signal Code Power International Telecommunication Union Joint Detection Joint Predistortion kilo-bits per second
Abbreviation
ksps L1 L2 L3 LAC LAI LCD LLC LSA MA MAC MCC Mcps MDS ME MEHO MER MM MNC MO MOHO MS MSID MSC MT MTP MTP3-B MUI NAS NBAP NEHO NNI NRT NSAP Nt OCCCH ODCCH ODCH ODMA O&M ORACH ODTCH OVSF PC PCCC PCCH PCH PCPCH PCCPCH PCS PDH PDSCH PDU kilo-symbols per second Layer 1 (physical layer) Layer 2 (data link layer) Layer 3 (network layer) Link Access Control Location Area Identity Low Constrained Delay Logical Link Control Local Service Area Multiple Access Medium Access Control Mobile Country Code Mega-chips per second
Definition
Multimedia Distribution Service Mobile Equipment Mobile evaluated handover Message Error Rate Mobility Management Mobile Network Code Mobile Originated Mobile Originated Handover Mobile Station Mobile Station Identifier Mobile Services Switching Center Mobile Terminated Message Transfer Part Message Transfer Part level 3 Mobile User Identifier Non-Access Stratum Node B Application Part Network evaluated handover Network-Node Interface Non-Real Time Network Service Access Point Notification (SAP) ODMA Common Control Channel ODMA Dedicated Control Channel ODMA Dedicated Channel Opportunity Driven Multiple Access Operation and Management ODMA Random Access Channel ODMA Dedicated Traffic Channel Orthogonal Variable Spreading Factor Power Control Parallel Concatenated Convolutional Code Paging Control Channel Paging Channel Physical Common Packet Channel Primary Common Control Physical Channel Personal Communication System Plesiochronous Digital Hierarchy Physical Downlink Shared Channel Protocol Data Unit
Abbreviation
PG PHS PHY PhyCH PI PICH PID PLMN PMD PN PPM PRACH PS PSC PSCH PTM PTM-G PTM-M PU QoS QPSK RAB RACH RANAP RF RL RLC RLCP RNC RNS RNSAP RNTI RRC RRM RSCP RSSI RT RU RX SAAL SACCH SAP SAR SCCH SCCPCH SCH SDCCH SDH SDU SF SFN SIR SMS Processing Gain
Definition
Personal Handyphone System Physical layer Physical Channel Page Indicator Page Indication Channel Packet Identification Public Land Mobile Network Physical Media Dependent Pseudo Noise Parts Per Million Physical Random Access Channel Packet Switched Primary Synchronization Code PSCCCH Physical Shared Channel Point-to-Multipoint PTM Group Call PTM Multicast Payload Unit Quality of Service Quadrature (Quaternary) Phase Shift Keying Radio Access Bearer Random Access Channel Radio Access Network Application Part Radio Frequency Radio Link Radio Link Control Radio Link Control Protocol Radio Network Controller Radio Network Subsystem Radio Network Subsystem Application Part Radio Network Temporary Identity Radio Resource Control Radio Resource Management Received Signal Code Power Received Signal Strength Indicator Real Time Resource Unit Receive Signaling ATM Adaptation Layer Slow Associated Control Channel Service Access Point Segmentation and Reassembly Synchronization Control Channel Secondary Common Control Physical Channel Synchronization Channel Stand-Alone Dedicated Control Channel Synchronous Digital Hierarchy Service Data Unit Spreading Factor System Frame Number Signal-to-Interference Ratio Short Message Service
Abbreviation
SMS-CB SP SRNC SRNS SS7 SSC SSCOP SSCF SSCF-NNI SSCS SSDT SSSAR STC STTD TC TCH TDD TDMA TF TFC TFCI TFCS TFI TFS TMSI TN TPC TrCH TSTD TTI TX UARFCN UARFN UDD UDP UE UER UL UMTS UNI UP URA USCH USIM UTRA UTRAN VA VBR VC WCDMA SMS Cell Broadcast Switching Point
Definition
Serving Radio Network Controller Serving RNS Signaling System No. 7 Secondary Synchronization Code Service Specific Connection Oriented Protocol Service Specific Co-ordination Function Service Specific Coordination Function Network Node Interface Service Specific Convergence Sublayer Site Selection Diversity Transmission Service Specific Segmentation and Re-assembly sublayer Signaling Transport Converter Space Time Transmit Diversity Transmission Convergence Traffic Channel Time Division Duplex Time Division Multiple Access Transport Format Transport Format Combination Transport Format Combination Indicator Transport Format Combination Set Transport Format Indicator Transport Format Set Temporary Mobile Subscriber Identity Termination Node Transmit Power Control Transport Channel Time Switched Transmit Diversity Transmission Timing Interval Transmit UTRA Absolute Radio Frequency Channel Number UTRA Absolute Radio Frequency Number Unconstrained Delay Data User Datagram Protocol User Equipment User Equipment with ODMA relay operation enabled Uplink (Reverse Link) Universal Mobile Telecommunications System User-Network Interface User Plane User Registration Area Uplink Shared Channel UMTS Subscriber Identity Module Universal Terrestrial Radio Access Universal Terrestrial Radio Access Network Voice Activity factor Variable Bit Rate Virtual Circuit Wideband Code Division Multiple Access

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3.4 3.5 3.6 4

Propagation Channel Measurements & Synchronisation HSUPA

Code and Channel Generators

Multiplexers, Demultiplexers and Integrators

Appendix A:3GPP Definitions

Appendix B:3GPP Abbreviations

Scope of this Document

3GPP FDD Library Version Number

Distribution and Support

3GPP Standard Documentation

3GPP Web Site

Key FDD Standard Document Numbers

Physical layer procedures Services provided by the physical layer.

Comments and Support Requests

This Document Licence

FDD Library Version

Figure 1.3.1: Simulation groupings for the library.

Installing the 3GPP:fdd Library

docs General Examples Compressed Mode Downlink

2 Why FDD? - The 3GPP Proposal for IMT2000

2 Why FDD? - The 3GPP Proposal for IMT2000

2 Why FDD? - The 3GPP Proposal for IMT2000

2 Why FDD? - The 3GPP Proposal for IMT2000

3 FDD Block Overview

3 FDD Block Overview

Uplink Generator Downlink Generator HSDPA Transmission Generator

3 FDD Block Overview

3.3.3 3.4 3.5 3.6

Complex Gain Rayleigh Fading Channel Moving Channel Birth-Death Channel

Measurements & Synchronisation

4 Using the Library

4 Using the Library

4 Using the Library

3GPP FDD - Uplink Transmit

Cyclic Redundancy Coding

CRCGen Convolutional Coding Turbo Coding ConvEnc

or TurboEnc Transport Channel Codec TrChCdr

1st Interleaving IntLeave

Transport Channel Mux Physical Control Chan Gen. IntLeave TChMux

2nd Interleaving IntLeave

DPCCHGen In-Phase Data

OVSF Real and Imaginary

Imag Cplx Mpy

Real Short Code Gen. Long Code Gen. ULSCGen ULLCGen

Complex data path

Pulse Shaping RF Modulation

Complex Gain, Channel Models

Complex Data Output

4 Using the Library

3GPP FDD - Uplink Receive

Pulse Shaping RF Demodulation

Clock Generator ClockGen

OVSF Real and Imaginary

Cmplx Gain IntDump Data (real) Physical layer control (imag)

2nd Deinterleaving DeIntLev

RateM Transport Channel Codec TrChCdr

1st Deinterleaving DeIntLev Convolutional Decoding Turbo Decoding ConvDec

Cyclic Redundancy Decode

4 Using the Library

Downlink Transmit and Receive.

4 Using the Library