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Digital Logic
Digital Logic
___________________________________________________________________________________________________________________________________________________________________
Decimal:
1,998
Binary:
11111001110 = 1x210 +1x29 +1x28 +1x27 +1x26 +1x23 +1x22 +1x21 =
1,024+512+258+128+64+8+4+2 = 1,998
Emil M. Petriu
Powers of 2
____________________________________________________________________________________________________________________________________________________________________
2N
Comments
_____________________________________________________________________________________________________________________________________________________________________
0
1
2
3
4
5
6
7
8
9
10
11
1
2
4
8
16
32
64
128
256
512
1,024
2,048
.....
15
32,768
.....
20
1,048,576
...
30
1,073,741,824
____________________________________________________________________________________________________________________________________________________________________
Emil M. Petriu
Negative Powers of 2
_____________________________________________________________
N <0
2N
____________________________________________________________
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
2-1 = 0.5
2-2 = 0.25
2-3 = 0.125
2-4 = 0.0625
2-5 = 0.03125
2-6 = 0.015625
2-7 = 0.0078125
2-8 = 0.00390625
2-9 = 0.001953125
2-10 = 0.0009765625
_____________________________________________________________
Emil M. Petriu
Decimal value
-----------------------------------------------------------------------------------------------------------------
HEXADECIMAL
----------------------------------------------------------------------------------------------------
Binary:
11111001110
----------------------------------------------------------------------------------------------------
12
14 <== Decimal
Hexadecimal: 7CE
= 7x162 +12x161
+14x160 = 1998
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
----------------------------------------------------------------------------------------------------
Emil M. Petriu
Emil M. Petriu
GATES
NOT
A
1
0
AND
A .B
_____________________________________
0
0
1
1
______________________
0
1
F =A
0
1
0
1
0
0
0
1
A
B
_____________________________________
OR
A+B
_____________________________________
0
0
1
1
0
1
0
1
0
1
1
1
_____________________________________
Emil M. Petriu
A
F=A+B
B
F =A . B
more GATES
NAND
A .B
_____________________________________
0
0
1
1
0
1
0
1
1
1
1
0
F =A . B
_____________________________________
NOR
A +B
_____________________________________
0
0
1
1
0
1
0
1
1
0
0
0
_____________________________________
Emil M. Petriu
A
F=A+B
B
XOR
A B
_____________________________________
0
0
1
1
0
1
0
1
0
1
1
0
F = A B
_____________________________________
EQU or XNOR
A B
_____________________________________
0
0
1
1
0
1
0
1
1
0
0
1
_____________________________________
Emil M. Petriu
A
B
F = A B
EXAMPLES OF
GATES WITH
THREE INPUTS
A+B+C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
A
B
C
A
B
C
AND
OR
F =A.B.C
F = A+B+C
A
B
C
Emil M. Petriu
NAND
F =A.B.C
A
B
C
NOR
F = A+B+C
F = A .B .C + A .B .C
+ A .B .C + A .B .C
________________________________________
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
A .B .C
A .B .C
F
A .B .C
_________________________________________
A .B .C
A
Emil M. Petriu
B
A
C
B
Sum-of-products
form of the logic circuit.
BOOLEAN ALGEBRA
Proof :
AND rules
A .A = A
A B C A. (B+C) A.B+A.C
____________________________________________________________
.A=0
A
0 .A = 0
1 .A = A
A .B = B .A
A . (B . C) = (A . B) . C
A . (B + C) = A . B + A . C
A .B = A + B
Emil M. Petriu
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
OR rules
A B C A + B.C (A+B) . (A+C)
A +A = A
A +A = 1
0 +A = A
1 +A = 1
A +B = B +A
A + (B + C) = (A + B) + C
A + B . C = (A + B) . (A +C)
A +B = A. B
Emil M. Petriu
_____________________________________________________________________
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
DeMorgans Theorem
A B A . B A + B A + B A.B
A.B = A + B
A+B=A.B
Emil M. Petriu
_______________________________
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
A .B .C
F
A .B .C
A .B .C
B
A
C
B
C
Emil M. Petriu
F = AB + AC
A .B
F
A .C
Emil M. Petriu
Emil M. Petriu
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
A B C
0
0
0
0
1
1
1
1
...
...
...
...
...
...
...
...
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AB
00 01 11 10
C
0
A B C D F
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
...
...
...
...
...
...
...
...
AB
00 01 11 10
CD
00 0 4 12 8
01
13
11
15 11
10
14 10
Emil M. Petriu
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Emil M. Petriu
A B C F
AB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
00 01 11 10
0 0
1 0
AB
AC
F = AB + AC
A B C D F
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
AB
00 01 11 10
CD
00 1 0 1
0
01 0 1 1
0
11
10
ABD
AB
BD
F = A B D + AB + BD
Emil M. Petriu
DeMorgans
Theorem
=A+B
A
B
A+B=A.B
A
B
A.B
A .B
A+B
A+B
A
B
A. B
Emil M. Petriu
F = AB + AC
A
X=(X)
A B
F
A
Emil M. Petriu
0+
0
0+
1
1+
0
1+
1
__________
__________
__________
__________
Truth table
Inputs
A B
0
0
1
1
0
1
0
1
Outputs
Carry Sum
0
0
0
1
0
1
1
0
Sum = A + B
Carry
(over)
A
The binary
number 10 is
equivalent to
the decimal 2
10
Sum
Sum
B
Half-Adder
circuit
Carry
Carry = A . B
Emil M. Petriu
____________________________________
11 000 110
Sum
01 111 000
Carry
S7 S6 S5 S4 S3 S2 S1 S0
A7 B7
A6 B6
A5 B5
A4 B4
A3 B3
A2 B2
A1 B1
A0 B0
A B
A B
A B
A B
A B
A B
A B
A B
CO CI
CO CI
CO CI
CO CI
CO CI
CO CI
CO CI
CO CI
S7
S6
S5
S4
S3
S2
S1
S0
Carry In = 0
Carry Out
A7 A6 A5 A4 A3 A2 A1 A0 +
B7 B6 B5 B4 B3 B2 B1 B0
0 1 1 0 1 1 00 +
0 1 0 1 1 0 10
108 D +
90D
198 D
Emil M. Petriu
Full Adder
A B
CO CI
S
Sum
Carry In
Carry Out
Inputs
A B CI
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Outputs
CO S
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
AB
CI
S
00 01 11 10
0 0
1 1
CO
AB
CI
A.B
00 01 11 10
0 0
1 0
B. CI
A . CI
S = A . B . CI + A . B . CI + A . B . CI + A . B . CI
C = A . B + B . CI + A . CI
Emil M. Petriu
B3 B2 B1 B0
_________________________
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(A)
(B)
(C)
(D)
(E)
(F)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Four-bit
machine
representation
of the hex
digits
S1
S6
S5
S7 S6
S5
S2
S7
S4
S4
S3
S3
S2
7 SEGMENT
HEX
B3
B2 B1
B0
S1
Emil M. Petriu
S1
B3 B2 B1 B0
S1
S1
S1
S1
_________________________
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(A)
(B)
(C)
(D)
(E)
(F)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S6
S2
S7
S5
S6
S3
S4
S2
S7
S5
S3
S4
S1
S6
S5
S2
S3
S5
S7
S4
S5
S6
S5
S2
S3
S6
S5
S7
S4
S1 = 0+2 +3+5+6+7+8+9+A+C+E+F
S2 = 0+1+2+3+4+7+8+9+A+D
S3
S4
S2
S7
S3
S4
S6
S5
S3
S6
S5
S3 S5
S4
S6
S5
S2
S7
S3
S4
S7
S4
S3
S6
S5
S3
S4
S6
S5
S1
S2
S7
S3
S4
S1
S2
S2
S7
S1
S1
S2
S2 S6
S7
S1
S1
S1
S6
S2
S7
S1
S7
S4
S6
S7
S4
S6
S5
S2
S7
S4
S3
S1
S2
S3
S6
S5
S7
S4
S2
S3
S1
S6
S3 = 0+1+3+4+5+6+7+8+9+A+B+D
S4 = 0+2+3+5+6+8+9+B+C+D+E
S5 = 0+2+6+8+A+B+C+D+E+F
S6 = 0+4+5+6+8+9+A+B+C+E+F
S7 = 2+3+4+5+6+8+9+A+B+D+E+F
S5
S7
S4
S2
S3
Emil M. Petriu
Hex-to-7 segment
B3 B2 B1 B0
_________________________
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(A)
(B)
(C)
(D)
(E)
(F)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S1 = 0+2 +3+5+6+7+8+9+A+C+E+F
S2 = 0+1+2+3+4+7+8+9+A+D
S3 = 0+1+3+4+5+6+7+8+9+A+B+D
S4 = 0+2+3+5+6+8+9+B+C+D+E
B3 B2
B1 B0
00 01 11 10
S5 = 0+2+6+8+A+B+C+D+E+F
00 0 4 C 8
S6 = 0+4+5+6+8+9+A+B+C+E+F
01
1 5 D 9
S7 = 2+3+4+5+6+8+9+A+B+D+E+F
11
10
Emil M. Petriu
Hex-to-7 segment
B3 B2
Mapping the ad-hoc binary-hex
logic equations onto Karnaugh maps:
B1 B0
B3 B2
B1 B0
00 01 11 10
S1
B3 B2
00 01 11 10
B1 B0
S2
00 01 11 10
00
00
01
01
11
1 0
11
0 0
10
1 1
10
0 1
00 0 4 C 8
01
1 5 D 9
11
10
B3 B2
B1 B0
S1 = 0+2 +3+5+6+7+8+9+A+C+E+F
S2 = 0+1+2+3+4+7+8+9+A+D
S3 = 0+1+3+4+5+6+7+8+9+A+B+D
S4 = 0+2+3+5+6+8+9+B+C+D+E
S3
B3 B2
00 01 11 10
B1 B0
S4
00 01 11 10
00
00
01
01
11
0 1
11
0 1
10
0 1
10
1 0
Emil M. Petriu
Hex-to-7 segment
B3 B2
B1 B0
B3 B2
S5
B3 B2
00 01 11 10
B1 B0
S6
00 01 11 10
00
00
01
01
00 0 4 C 8
11
1 1
11
1 1
01
1 5 D 9
10
1 1
10
1 1
11
10
B1 B0
00 01 11 10
B3 B2
B1 B0
S5 = 0+2+6+8+A+B+C+D+E+F
S6 = 0+4+5+6+8+9+A+B+C+E+F
S7 = 2+3+4+5+6+8+9+A+B+D+E+F
S7
00 01 11 10
00
01
11
1 1
10
1 1
Emil M. Petriu
2- bit Comparator
A1 A0 B1 B0 F 1 F2 F 3
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
A=B
F1 = (0,5,10,15)
A>B
F2 = (4,8,9,12,13,14)
A<B
F3 = (1,2,3,6,7,11)
Emil M. Petriu
2- bit Comparator
F1 = (0,5,10,15)
A=B
A1A0
B1B0
A1 A0
B1 B0
00 01 11 10
00 01 11 10
00 1 0 0
01 0 1 0
0
0
00 0
12
11
01
13
10
11
15 11
10
14 10
F1 = 1 when both numbers, A and B,
are equal which happens when all
their bits of the same order are identical,
i.e. A0 = B 0 AND A1 = B1
2- bit Comparator
F3 = (1,2,3,6,7,11)
A<B
A1 A0
B1 B0
00 01 11 10
00 0
12
01
13
11
15 11
10
14 10
A1A0
B1B0 00 01 11 10
00 0 0 0
0
01 1 0 0
0
11
10
Emil M. Petriu
2- bit Comparator
A1 A0
F2 = (4,8,9,12,13,14)
A>B
B1 B0
A1A0
B1B0
00 01 11 10
00 0
01 0
11 0
10 0
F1+F3
A1A0
10
Emil M. Petriu
00 0
12
01
13
11
15 11
10
14 10
F2 = F1 + F3
F1
A1A0
B1B0 00 01 11 10
00 1 0 0
0
01 1 1 0
0
11 1 1 1
1
00 01 11 10
B1B0
F3
A1A0
00 01 11 10
00 1 0 0
01 0 1 0
11
10
B1B0 00 01 11 10
00 0 0 0
0
01 1 0 0
0
11 1 1 0
1
10
2- bit Comparator
B1 B 0 A1 A0
F3 = A0B1B 0+A1B1+A1A0B 0
A1 B 1
F1 = (A0B0) (A1 B1)
A0 B 0
F2 = F1 + F3
F3 = A0B1B 0+A1B1+A1A0B 0
Emil M. Petriu
3-to-8 Decoder
F0
A B C F0 F1 F2 F3 F4 F5 F6 F7
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
F1
F2
F3
F4
F5
F6
F7
Emil M. Petriu
F0
A B C E F0 F1 F2 F3 F4 F5 F6 F7
(x)
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
x
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
1 1
0 0
0 1
0 1
0 1
0 1
0 1
01
01
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
F1
F2
F3
F4
F5
F6
F7
Emil M. Petriu
B3 B2 B1 B0
_________________________
S6
S5
S7 S6
S5
S2
S7
S4
S4
S3
S3
S2
7 SEGMENT
BCD
B3
Emil M. Petriu
B2 B1
B0
S1
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(x)
(x)
(x)
(x)
(x)
(x)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B3 B2
B1 B0
00 01 11 10
00 0
01
11
10
BCD-to-7 segment
S1
B3 B2 B1 B0
S6
S7
S1
S2
S6
S7
S1
S2
S6
S7
S1
S2
S6
S7
S1
S2 S6
S7
S2
_________________________
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(x)
(x)
(x)
(x)
(x)
(x)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Emil M. Petriu
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S5
S4
S3
S5
S1
S6
S5
S7
S4
S4
S3
S5
S1
S2
S3
S6
S5
S7
S4
S4
S3
S5
S1
S2
S3
S6
S5
S7
S4
S4
S3 S5
S1
S2
S3
S6
S5
S7
S4
S4
S3
S1
S2 S6
S3 S5
S7
S4
S4 = 0+2+3+5+6+8+9
S1 = 0+2 +3+5+6+7+8+9
S5 = 0+2+6+8
S2 = 0+1+2+3+4+7+8+9
S6 = 0+4+5+6+8+9
S3 = 0+1+3+4+5+6+7+8+9
S7 = 2+3+4+5+6+8+9
S2
S3
B3 B2
BCD-to-7 segment
B1 B0
S1 = 0+2 +3+5
+6+7+8+9
B3 B2
B1 B0
00
S1
00 01 11 10
1
01
11
x x
10
x x
00 01 11 10
00 0
01
11
10
S2 = 0+1+2+3
+4+7+8+9
S2
B3 B2
00 01 11 10
B1 B0
00 1 1 x 1
01
11
x x
10
x x
S1 = B3 + B2B0 + B1
+ B2B1 + B2B0
S2 = B3 + B2 + B1B0 + B1B0
Emil M. Petriu
BCD-to-7 segment
B3 B2
B1 B0
S3 = 0+1+3+4+5+6+7+8+9
S3
B3 B2
00 01 11 10
B1 B0
00 1 1 x 1
00 0
01
11
10
S4 = 0+2+3+5+6+8+9
B3 B2
B1 B0
S4
00 01 11 10
00
01
01
11
x x
11
10
x x
10
S3 = B3 + B1B0 + B1 + B2
Emil M. Petriu
00 01 11 10
B3 B2
B1 B0
00 01 11 10
00 0
01
11
10
1
3
2
7
6
x
x
B1 B0
00
S7 = 2+3+4+5+6+8+9
S6 = 0+4+5+6+8+9
B3 B2
B1 B0
S6
00
01
01
11
x x
11
x x
10
x x
10
x x
B2B0 + B1B0
00
01
11
10
00 01 11 10
S5 =
00 01 11 10
B1 B0
S5
00 01 11 10
S7
B3 B2
S5 = 0+2+6+8
B3 B2
BCD-to-7 segment
S7 = B3 + B2B1
+ B1B2 + B1B0
I1 I2 F
MEMORY ELEMENTS:
LATCHES AND FLIP-FLOPS
R-S Latch
S=0
(Reset-Set)
S
I1
I2
0
0
1
1
0
1
0
1
1
1
1
0
Q =1
S=0
Q =1
R= 1
Q =0
R= 0
Q =1
S=1
S R
Q Q
0
0
1
1
1 1
1 0
0 1
Q Q
0
1
0
1
Emil M. Petriu
Q =0
S =1
Q=1
R= 1
Q =0
Weird state
Set state
Reset state
Hold state
R= 0
Q =1
D (Transparent) Latch
S
Q
R
Enable D
Q Q
Q Q
1
1
0
1
0 1
1 0
Enable
Enable D S R
Q Q
S R
Q Q
0
0
1
1
1 1
1 0
0 1
Q Q
1 1
Q Q
1 1
Q Q
1 0
1 1
1 0
0 1
0 1
1 0
Emil M. Petriu
0
1
0
1
D Latch
S
Enable D S R
Q
R
Enable
Q Q
1 1
Q Q
1 1
Q Q
1 0
1 1
1 0
0 1
0 1
1 0
Enable
0
1
0
1
0
1
0
1
Hold
Holdstate
Transparent state
Holdstate
Emil M. Petriu
Latch 1
D
Enab.
CLK
EN1
Din*
Synchronous D Flip-Flop
Latch 2
Q
Q
D1
D
Enab.
Q
Q
Q
Q
Positive-Edge
-Triggered
D Flip-Flop
D
CLK
Latch 1 is
Transparent
D1
EN2
1
Input data D may change
0
1
0
1
Latch 1 is Holding
D1 = Din*
Latch 2 is Holding
Latch 1 is Transparent
Latch 2 is Holding
Q = D1 = Din*
The state of the flip-flops output Q copies input
D when the positive edge of the clock CLK occurs
Emil M. Petriu
EN2
CLK
EN1
0
1
0
1
0
1
0
Positive-Edge-Triggered
D Flip-Flop
Synchronous D Flip-Flop
Vcc CLR2
14
13
D2
CLK2 PR2 Q2
12
11
10
Q2
9
Connection diagram
of the 7474 Dual
Positive-Edge-Triggered
D Flip-Flops with Preset
and Clear.
1
CLR1
2
D1
CLK1 PR1
Q1
Q1
7
GND
Emil M. Petriu
COUNTERS
4-Bit Synchronous Counter using D Flip-Flops
Q3
Q2
Q1
Q0
CL
CK
15
14
CL
13
Q = Qi 2i
.
12
11
10
i=0
CK
0
1
CL
0 1
2 3 4 5 6
7 8
9 10 11 12 13 14 15 0 1
2 3 4 5
6
Emil M. Petriu
DECIMAL
STATE
Q
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
BINARY STATE OF
THE COUNTER
Q3 Q2 Q1 Q0
D3 D2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D3
Q3 Q2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D1 D0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D2
Q3 Q2
00 01 11 10
Q1 Q0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D1
Q3 Q2
00 01 11 10
Q1 Q0
00 01 11 10
Q1 Q0
D0
Q3 Q2
00 01 11 10
Q1 Q0
00
00
00
00
01
01
01
01
11
11
11
11
10
10
10
10
Emil M. Petriu
D3
Q3 Q2
00 01 11 10
Q1 Q0
D2
Q3 Q2
00 01 11 10
Q1 Q0
00
00
01
01
11
11
10
10
D1
Q3 Q2
Q1 Q0
00 01 11 10
Q1 Q0
0
D0
Q3 Q2
00 01 11 10
00
01
11
10
D1 = Q1. Q0 + Q1. Q0
00
01
11
10
D0 = Q0
Emil M. Petriu
CL
CK
Q0
D
CLK
R
Q0
D0 = Q0
Q1
D
D1 = Q1. Q0 + Q1. Q0
CLK
D2 =
Q2. Q0
Q2.
Q1 +
Q2. Q1. Q0
Q1
Q2
+ Q3.Q2.Q1.Q0
CLK
R
Q2
Q3
D
CLK
R
Emil M. Petriu
Q3