module fifo_top(Rd_data,ff_full,ff_h_full,ff_empty,ff_h_empty,ff_rdy,Rd_d_vld,Wr _done,Rd_done,ff_wr_err,ff_rd_err,ff_wr_ptr, ff_rd_ptr, Wr_data,Wr_clk,Rd_clk,Wr_req,Rd_req,ff_flush,Wr_reset ,Rd_reset,ff_stall_wr,ff_stall_rd); parameter f_width=32; parameter f_depth=256; parameter f_bit_width=8; output [f_width-1:0] Rd_data;

reg [f_width-1:0] Rd_data; output [f_bit_width-1:0] ff_wr_ptr; reg [f_bit_width-1:0] ff_wr_ptr; output [f_bit_width-1:0] ff_rd_ptr; reg [f_bit_width-1:0] ff_rd_ptr; output ff_full,ff_h_full,ff_empty,ff_h_empty,ff_rdy,Rd_d_vld,Wr_done,Rd_done,ff_ wr_err,ff_rd_err; reg ff_full,ff_h_full,ff_empty,ff_h_empty,ff_rdy,Rd_d_vld,Wr_done,Rd_done,ff_wr_ err,ff_rd_err; input [f_width-1:0] Wr_data; input Wr_clk,Rd_clk,Wr_req,Rd_req,ff_flush,Wr_reset,Rd_reset,ff_stall_wr,ff_stal l_rd; //internal wires/reg reg rd_next_en,wr_next_en; reg [f_bit_width-1:0] Ptr_diff; counter rd_counter(ff_rd_ptr,Rd_reset,Rd_clk,rd_next_en); counter wr_counter(ff_wr_ptr,Wr_reset,Wr_clk,wr_next_en); memory ram(Rd_data,Wr_done,Rd_done,Rd_d_vld,Wr_clk,Rd_clk,Wr_reset,Rd_reset,ff_w r_ptr,ff_rd_ptr,Wr_req,Rd_req, ff_stall_wr,ff_stall_rd,ff_flush,ff_rdy); fifo_ctrl control(Ptr_diff,ff_empty,ff_full,ff_h_full,ff_h_empty,ff_wr_err,ff_rd _err,Wr_req,Rd_req,ff_wr_ptr,ff_rd_ptr, ff_stall_rd,ff_stall_wr);

endmodule