//testbench module fifo_tb; parameter depth=256; reg w_data,w_clk,r_clk,w_req,r_req,fifo_flush,w_reset,r_reset,f_stall_w,f_stall_ r; wire r_data,fifo_full,fifo_h_full,fifo_empty,fifo_h_empty,fifo_rdy,r_d_vld,w_don e,r_done,fifo_wr_err,fifo_rd_err,fifo_wr_ptr,fifo_rd_ptr; initial begin $monitor($time,"r_data=%b,fifo_full=%b,fifo_h_full=%b,fifo_empty=%b,fifo_h_emp ty=%b,fifo_rdy=%b,r_d_vld=%b,w_done=%b,r_done=%b,fifo_wr_err=%b,fifo_rd_err=%b, fifo_wr_ptr=%b,fifo_rd_ptr=%b,w_data=%b,w_clk=%b,r_clk=%b,w_req=%b,r_

req=%b,fifo_flush=%b,w_reset=%b,r_reset=%b,f_stall_w=%b,f_stall_r=%b", r_data,fifo_full,fifo_h_full,fifo_empty,fifo_h_empty,fifo_rdy,r_d_vld ,w_done,r_done,fifo_wr_err,fifo_rd_err,fifo_wr_ptr,fifo_rd_ptr, w_data,w_clk,r_clk,w_req,r_req,fifo_flush,w_reset,r_reset,f_stall_w,f _stall_r); end //instantiate module fifo fifo f1 (r_data,fifo_full,fifo_h_full,fifo_empty,fifo_h_empty,fifo_rdy,r_d_vld,w _done,r_done,fifo_wr_err,fifo_rd_err,fifo_wr_ptr,fifo_rd_ptr, w_data,w_clk,r_clk,w_req,r_req,fifo_flush,w_reset,r_reset,f_stall_w,f_s tall_r);

initial #5000 $stop; initial begin r_clk=1'b0; forever #5 r_clk=~r_clk; end initial begin w_clk=1'b0; forever #5 w_clk=~w_clk; end initial begin fifo_flush=1'b0; w_reset=1'b1; r_reset=1'b1; f_stall_w=1'b0; f_stall_r=1'b0; w_data=1; fork #10 w_reset=1'b0; #10 r_reset=1'b0;join repeat(depth)@(posedge w_clk) begin repeat(2)@(posedge w_clk) begin w_req=1'b1;

r_req=1'b0; w_data=w_data+1; end repeat(1)@(posedge r_clk) begin r_req=1'b1; w_req=1'b0; end end

repeat(depth)@(posedge r_clk) begin repeat(2)@(posedge r_clk) begin r_req=1'b1; w_req=1'b0; end repeat(1)@(posedge w_clk) begin w_req=1'b1; r_req=1'b0; w_data=w_data+1; end end end