Chng 2.

KIN TRC VI X L ARM

2.1 ARM7 (32-bit)

2.1.1 Gii thiu tng quan Ra i vo nm 1994, ARM7 pht trin rt thnh cng v gip ARM tr thnh kin trc c la chn ca th gii k thut s. Trong vi nm qua, hn 10 t thit b c s dng chip ARM7 c ng dng trong nhiu lnh vc ca i sng. Hin nay, ARM7 vn tip tc c s dng rng ri thit k cc thit b 32 bit n gin. Kin trc ARM da trn nguyn l RISC (Reduced Instruction Set Computer). Tp lnh gim v c ch gii m n gin hn nhiu so vi thit k CISC (Complex Instruction Set Computer). c im ni bt ca ARM7: Kin trc cng nghip chun. D dng thit k v debug.

Lnh vc ng dng ca ARM7: Nhng: USB controllers, HDD controllers, Bluetooth controllers, Networking/WiFi , my qut y khoa. Tiu dng: chi in t, thit b cm tay, GPS, MP3 Player, my thu pht cm tay. T ng: chn on, bo tr, gii tr, cm ng. Cng nghip: ng h nng lng, b ngt mch, UPS, t ng ha nh my. u c th, my ATM, my tnh tin, my bn hng H ARM7 gm c cc vi x l: ARM7TDMI-S, ARM7TDMI, ARM7EJ-S.

2.1.1

ARM7TDMI-S ARM7TDMI-S l mt thnh phn ca b vi x l a dng 32 bit h ARM. Vi x l h ARM c hiu qu cao v tiu th nng lng thp v s lng cng logic t.

2.1.1.1 Kin trc b vi x l ARM7TDMI-S

Vi x l ARM7TDMI-S c hai tp lnh: 2.1.1.1.1

Tp lnh ARM 32 bit Tp lnh Thumb 16 bit

Tng quan v tp lnh

Vi kin trc 32 bit, c th thao tc trn s nguyn 32 bit ch vi nhng lnh n v nh a ch trn khng gian a ch ln, c hiu qu hn nhiu so vi kin trc 16 bit. Khi x l d liu 32 bit, kin trc 16 bit phi s dng t nht 2 lnh thc hin c cng cng vic nh mt lnh 32 bit. Kin trc 32 bit ch c lnh 32 bit v kin trc 16 bit ch c lnh 16 bit, do kin trc 16 bit c mt code dy c hn. Thumb b sung tp lnh 16 bit trn kin trc 32 bit nn hiu qu cao hn kin trc 16 bit v mt code dy c hn kin trc 32 bit. Tp lnh Thumb Tp lnh Thumb l tp con ca nhng lnh ARM 32 bit thng c s dng nht. Mi lnh trong tp lnh Thumb c di 16 bit v c mt lnh ARM 32 bit tng ng. Tp lnh Thumb thao tc c vi cu hnh thanh ghi ARM chun, to ra s kt hp nhng im tt nht ca trng thi ARM v Thumb. Tp lnh Thumb c tt c nhng thun li ca vi x l 32 bit: Khng gian a ch 32 bit Thanh ghi 32 bit Shifter v ALU 32 bit Mang chuyn b nh 32 bit

Do , tp lnh Thumb c phm vi cho tng thnh phn di hn, thao tc s hc mnh m v khng gian a ch rng ln. M lnh Thumb c kch thc ch bng 65% m lnh ARM v cung cp 160% hiu nng so vi m lnh ARM khi chy trn h thng 16 bit. Tp lnh Thumb lm cho vi x l ARM7TDMI-S thch hp mt cch l tng cho cc ng dng nhng vn hn ch v b nh.
2.1.1.2 M hnh lp trnh ARM7TDMI-S
2.1.1.2.1 Trng thi thao tc ca vi x l

Vi x l ARM7TDMI-S c hai trng thi thao tc: Trng thi ARM: cc lnh ARM 32 bit c thc thi Trng thi Thumb: cc lnh Thumb 16 bit c thc thi.

Vic chuyn i gia 2 trng thi ny khng nh hng n kiu thao tc ca vi x l v ni dung ca cc thanh ghi. Chuyn i trng thi gia ARM v Thumb s dng lnh BX Tt c cc x l exception din ra trng thi ARM. Nu exception xy ra trng thi Thumb, vi x l tr li trng thi ARM. Vic chuyn i tr li trng thi Thumb din ra t ng khi exception c tr v.
2.1.1.2.2 T chc b nh

Vi x l ARM7TDMI-S xem b nh nh l tp hp dy cc byte c nh s tng t 0. V d: Byte 0 n byte 3 lu t (word) th nht. Byte 4 n byte 7 lu t (word) th hai. Byte 8 n byte 11 lu t (word) th ba.

Vi x l ARM7TDMI-S c th thao tc vi cc t (word) c lu tr trong b nh theo 2 kiu nh dng Little-endian v Big-endian. Little-endian Trong kiu nh dng Litte-endian, byte c nh s thp nht trong mt Word l byte t quan trng nht ca Word v byte c nh s cao nht l byte quan trng nht.

Hnh 2-1 Cch nh a ch byte kiu Little-endian ca vi x l ARM7TDMI-S

Big-endian Trong kiu nh dng big-endian, ARM7TDMI-S lu tr byte quan trng nht ca Word ti byte c nh s thp nht v byte t quan trng nht ca Word c nh s cao nht.

Hnh 2-2 Cch nh a ch byte kiu Big-endian ca vi x l ARM7TDMI-S

2.1.1.2.3

Kiu d liu

Vi x l ARM7EJ-S h tr cc kiu d liu sau: 2.1.1.2.4

word (32-bit) halfword (16-bit) byte (8-bit).

Kiu thao tc

Vi x l ARM7TDMI-S c 7 kiu thao tc: User mode: trng thi thc thi chng trnh thng thng ca ARM, c dng thc thi hu ht cc ng dng. Fast interrupt (FIQ) mode: h tr vn chuyn d liu. Interrupt (IRQ) mode: x l cc ngt thng thng Supervisor mode: kiu thao tc c bo v cho h iu hnh Abort mode: c gi sau mt d liu hoc lnh Prefetch Abort

System mode: mode c quyn dnh cho h iu hnh Undefined mode: c dng khi xy ra exception lnh cha c nh ngha.

Cc kiu thao tc khc User mode cn c bit n nh l kiu thao tc c quyn (privileged modes). Kiu thao tc c quyn c dng phc v interrupt hoc exception hoc truy xut n cc ti nguyn c bo v.
2.1.1.2.5 Thanh ghi

Vi x l ARM7TDMI-S c tt c 37 thanh ghi: 31 thanh ghi a dng 32 bit v 6 thanh ghi trng thi. Khng th truy xut tt c cc thanh ghi cng thi im. Trng thi v kiu thao tc ca vi x l s quyt nh thanh ghi no c php truy xut. Tp thanh ghi trng thi ARM trng thi ARM, 16 thanh ghi a dng v 1 hoc 2 thanh ghi trng thi (status register) c th c truy xut ti bt k thi im no. Trong kiu thao tc c quyn, cc cc thanh ghi banked (banked register) c th c truy xut. Tp thanh ghi trng thi ARM bao gm 16 thanh ghi c th truy xut trc tip (r0-r15) v mt thanh ghi trng thi chng trnh (CPSR Current Program Status Register) cha cc c iu kin v bit kiu thao tc. Thanh ghi a dng r0 n r13 dng lu tr d liu hoc a ch. Thanh ghi r14, r15 c nhng chc nng c bit: Thanh ghi lin kt (Link register) Thanh ghi r14 c s dng nh l thanh ghi lin kt LR Thanh ghi r14 nhn gi tr sao chp t thanh ghi r15 khi lnh BL (Branch with Link) c thc thi. Ngoi thi im ny, thanh ghi r14 c th c s dng nh thanh ghi a dng. Cc thanh ghi banked tng ng: r14_svc, r14_irq, r14_fiq, r14_abt v r14_und cng c th c s dng lu gi tr tr v ca

thanh ghi r15 khi c ngt v exception xy ra hoc khi lnh BL c thc thi bn trong ngt hoc exception. Thanh ghi PC (Program Counter): Thanh ghi r15 t chc b m chng trnh (Program Counter). trng thi ARM, thanh ghi r15 c gi tr bit [1:0] l 0 v bit [31:2] cha b m chng trnh. trng thi Thumb, thanh ghi r15 c gi tr bit [0] l 0, bit [31:1] cha b m chng trnh. cc kiu thao tc c quyn, thanh ghi SPSR (Saved Program Status Register) c php truy xut. Khi c exception xy ra khin kiu thao tc no c gi th thanh ghi SPSR lu li cc bt c v cc bit kiu thao tc. Cc thanh ghi banked l cc thanh ghi vt l ring bit nm trong li v ng vi cc thanh ghi sn c ty thuc vo kiu thao tc hin ti ca vi x l. Ni dung ca cc thanh ghi banked c lu tr khi kiu thao tc thay i. Mi thanh ghi banked c mt nh danh kiu thao tc ch ra kiu thao tc no ca thanh ghi ang c nh x ti. Kiu thao tc FIQ (Fast Interrupt) c 7 thanh ghi banked ng vi cc thanh ghi t r8 n r14 (r8_fiq n r14_fiq). Do , hu ht cc x l FIQ khng cn phi lu li bt k thanh ghi no. Cc kiu thao tc cn li (Supervisor, Abort, IRQ, Undefined), mi kiu thao tc c 2 thanh ghi banked ng vi thanh ghi r13 v r14.

Hnh 2-3 T chc thanh ghi trng thi ARM

Tp thanh ghi trng thi Thumb Tp thanh ghi trng thi Thumb l tp con ca tp thanh ghi trng thi ARM. trng thi Thumb, c th trc tip truy xut: 8 thanh ghi a dng, r0-r7 Thanh ghi PC Stack Pointer (SP), ARM r13 Thanh ghi lin kt LR (Link Register), ARM r14 Thanh ghi trng thi chng trnh CPSR

Mi kiu thao tc c quyn u c cc thanh ghi banked SP, LR, SPSR.

Hnh 2-4 T chc thanh ghi trng thi Thumb vi x l ARM7TDMI-S

2.2 ARM9 (32-bit)

2.2.1 Gii thiu tng quan H vi x l ARM9 l gii php vi x l n cho cc ng dng microcontroller, DSP (Digital Signal Processing) v Java. ARM9 em n th trng chip gi r v gim bt s phc tp, tit kim nng lng v thi gian giao dch. H ARM9 gm c cc vi x l ARM968E-S, ARM946E-S, ARM926E-S. Cc vi x l ARM9 l tri tim ca nhng sn phm tn hiu s cao cp. H vi x l ARM9 p ng c cc yu cu kht khe v tnh hiu qu cao, tnh linh hot v chi ph cho cc ng dng nhng. Lnh vc ng dng ARM9: Tiu dng: Smartphones, PDA, Set top box, chi in t, my quay phim k thut s.

Mng: Wireless LAN, 802.11, Bluetooth, SCSI, 2.5G/3G, Baseband Xe hi: Power train, ABS, Body systems, Navigation, Infotainment. Nhng: USB controllers, Bluetooth controllers, my qut y khoa Lu tr: HDD controllers, cng trng thi rn (solid state drive) So snh cc c im gia cc vi x l trong h ARM9 ARM968E-S y l vi x l ARM9 nh nht vi s ci tin DSP gim s tiu th nng lng cho cc ng dng nhng thi gian thc. Vi x l hot ng c hiu qu nh vo Tightly Coupled Memory c tch hp thng qua giao din chun. ARM946E-S ARM946E-S c s ci tin v b x l cache vi MPU cho cc ng dng thi gian thc chy trn RTOS. Vi x l hng thi gian thc c b sung thm cc Memory Protection Unit. Vi x l ny c ch cho cc ng dng m phn ln code nm trong b nh chnh v c nhu cu np vo cache. Vic x l cc exception v d liu c th thc hin ti Tightly Coupled Memory. ARM926EJ-S Vi x l c h tr Java, DSP v MMU (Memory Management Unit) dnh cho cc ng dng chy trn h iu hnh. ARM926EJ-S l vi x l c kh nng h tr y cc h iu hnh nh Linux, WindowsCE v Symbian. Vi x l ny thch hp cho nhiu ng dng cn giao din ha.

Hnh 2-5 So snh c im gia cc vi x l trong h ARM9

2.2.2

ARM968E-S

2.2.2.1 Gii thiu ARM968E-S

Vi x l ARM968E-S l thnh vin ca h ARM9 vi kin trc ARMv5TE. Vi x l ny h tr tp lnh ARM 32 bit v Thumb 16-bit.
2.2.2.2 M hnh lp trnh
2.2.2.2.1 Kiu thao tc ca vi x l

C 7 kiu thao tc ca vi x l: User: thc thi cc chng trnh thng thng. Fast interrupt (FIQ): x l cc ngt khn cp. Interrupt (IRQ): x l cc ngt thng thng. Supervisor: dnh cho cc chc nng ca h iu hnh. Abort: x l Data Aborts v Prefetch Aborts. System: dnh cho cc chc nng ca h iu hnh. Undefined: x l cc lnh cha c nh ngha.

Ngoi kiu thao tc User mode th cc kiu thao tc cn li c bit n nh l kiu thao tc c quyn. Kiu thao tc c quyn c dng phc v cho cc ngt hoc truy xut n cc ti nguyn c bo v.
2.2.2.2.2 Tp thanh ghi ca ARM968E-S

Vi x l ARM968E-S c 37 thanh ghi 32-bit:

16 thanh ghi a dng 1 thanh ghi trng thi chng trnh hin ti 15 thanh ghi banked c dng nh thanh ghi a dng v cc kiu thao tc 5 thanh ghi banked c dng nh thanh ghi lu trng thi chng trnh cho cc kiu thao tc.

Cc thanh ghi ny khng th truy xut cng thi im. Trng thi v kiu thao tc ca vi x l s quyt nh thanh ghi no c th dng c ti thi im .

Hnh 2-6 Tp thanh ghi ca vi x l ARM968E-S

ARM9 c nhiu ci tin ln so vi ARM7 bng vic s dng thm nhiu transitor, gm c: Ci tin tn s ng h: t kin trc pipleline 3 giai on thnh 5 giai on tc ng h tng gn nh gp i Ci tin chu k xung nhp: np v lu tr nhanh hn, nhiu lnh ch tn mt chu k ng h, ti u ha lc bin dch. Vi x l ARM9 kt hp cht ch gia cc lnh gia tng vic x l tn hiu s nh a thc thi h tr c hiu qu vic thi hnh cc thut ton x l tn hiu s.

 Truy xut tp thanh ghi trng thi Thumb trng thi Thumb, ngoi cc cu lnh nh trng thi ARM, cn c cc cu lnh truy xut n cc thanh ghi trng thi chng trnh v cc thanh ghi cao hn (r8-r15): trng thi Thumb, khng c lnh MRS hoc MSR di chuyn d liu gia CPSR hoc SPSR v cc thanh ghi a dng. trng thi Thumb, ch c nhng lnh sau c th truy cp vo cc thanh ghi cao: ADD, CMP, MOV, BLX Thanh ghi trng thi chng trnh Vi x l c mt thanh ghi trng thi chng trnh hin thi (CPSR) v 5 thanh ghi trng thi chng trnh c lu li (SPSRs) x l cc exception. Thanh ghi trng thi chng trnh c nhim v: Lu tr thng tin v nhng thao tc tnh ton gn y nht c thc hin trong ALU. iu khin m v ng cc ngt Thit lp kiu thao tc ca vi x l

Hnh 2-7 Thanh ghi trng thi chng trnh ca vi x l ARM968E-S

N: c overflow Z: c Zero C: c Carry/borrow V: c Negative hoc nh hn

I: bit hy IRQ F: bit hy FIQ T: c trng thi Thumb M: c trng thi (Mode field)

2.2.2.2.3

T chc b nh

Vi x l ARM968E-S t chc vng nh nh l mt tp hp tuyn tnh cc byte c nh s th t tng dn t 0. V d: Byte 0-3 lu Word u tin Byte 4-7 lu Word th hai

Cc Word trong b nh c th c lu tr di dng: little-endian hoc big-endian. Trong nh dng little-endian, byte c a ch thp nht l byte t quan trng nht ca Word (LSB). Byte c a ch cao nht l byte quan trng nht ca Word (MSB).

Hnh 2-8 T chc d liu kiu little-endian

Trong nh dng big-endian, byte c a ch thp nht l byte quan trng nht ca Word (MSB). Byte c a ch cao nht l byte t quan trng nht ca Word (LSB).

Hnh 2-9 T chc d liu kiu big-endian

2.3 Cortex-M3
2.3.1 Gii thiu tng quan B vi x l ARM Cortex-M3 l b x l ARM th h mi cho cc h thng nhng. N c pht trin cung cp mt nn tng chi ph thp, p ng yu cu thc thi ca MCU vi vic gim s bng bn dn trong li ARM Cortex dn ti tiu th nng lng thp v gim gi thnh vi x l, ng thi cung cp hiu nng tnh ton cao v mt h thng tin tin p ng ngt. B vi x l ARM Cortex-M3 32-bit RISC t hiu sut cao hn so vi ARM7TDMI-S. Dng Cortex gm c 3 phn nhnh chnh: dng A dnh cho cc ng dng cao cp, dng R dnh cho cc ng dng thi gian thc nh cc u c v dng M dnh cho cc ng dng vi iu khin v chi ph thp. Khng ging vi ARM7 c thit k theo kin trc Von Neumann (b nh chng trnh v b nh d liu chung vi nhau), Cortex-M3 c thit k da theo kin trc Harvard (b nh chng trnh v b nh d liu tch bit vi

nhau), v c nhiu bus cho php thc hin cc thao tc song song vi nhau, do lm tng hiu sut ca chip. B x l Cortex-M3 l mt vi iu khin c tiu chun ha gm mt CPU 32 bit, cu trc bus, n v x l ngt c h tr tnh nng lng ngt vo nhau (nested interrupt unit), h thng kim li (debug system) v tiu chun b tr b nh (standard memory layout). Dng Cortex c thit k h tr tp lnh ARM Thumb-2, tp lnh ny c pha trn gia tp lnh 16 v 32 bit, nhm t c hiu sut cao ca tp lnh ARM 32-bit vi mt m chng trnh ti u ca tp lnh Thumb 16 bit. Tp lnh Thumb-2 c thit k c bit dnh cho trnh bin dich C/C++, tc l cc ng dng da trn nn Cortex hon ton c th c vit bng ngn ng C m khng cn n chng trnh khi ng vit bng assembler nh ARM7 v ARM9.

Hnh 2-10 Cc thnh phn chnh ca vi x l Cortex-M3 Ngun: http://www.arm.com/products/processors/cortex-m/cortex-m3.php

2.3.2

M hnh lp trnh

2.3.2.1 Kiu thao tc

B x l Cortex c hai ch hot ng: ch Thread v ch Handler. CPU s chy ch Thread trong khi n ang thc thi ch nn khng c ngt xy ra v s chuyn sang ch Handler khi n ang thc thi cc ngt c

bit (exceptions). Ngoi ra, CPU Cortex c th thc thi m trong ch c quyn hoc khng c quyn (privileged hoc non-privileged). Trong ch c quyn, CPU c quyn truy cp tt c cc lnh. Trong ch khng c c quyn, mt s lnh b cm truy cp. Ngoi ra, vic truy cp cc thanh ghi iu khin h thng trong b vi x l Cortex cng b cm. Cch s dng ngn xp cng c th c cu hnh. Ngn xp chnh (main stack-R13) c th c s dng bi c hai ch Thread v Handler. Ch Handler c th c cu hnh s dng ngn xp qu trnh. Sau khi reset, b x l Cortex s chy trong cu hnh phng. C hai ch Thread v Handler c thc thi trong ch c quyn (privileged mode), do , khng c s gii hn no v quyn truy cp vo bt k ti nguyn ca b x l. C hai ch Thread v Handler u s dng ngn xp chnh. bt u thc hin, b x l Cortex n gin ch cn vector reset v a ch bt u ca ngn xp c cu hnh trc khi c th bt u thc thi chng trnh ng dng C. Tuy nhin, nu ngi dng ang s dng mt h iu hnh thi gian thc (RTOS) hoc ang pht trin mt ng dng i hi khc khe v an ton, chip c th c s dng trong ch cu hnh nng cao, ni ch Handler (exceptions v RTOS) chy trong ch c quyn v s dng ngn xp chnh, trong khi m ng dng chy trong ch Thread v khng c c quyn truy cp v s dng ngn xp qu trnh. Bng cch ny m h thng v m ng dng c phn vng v cc li trong m ng dng s khng lm cho RTOS sp .
2.3.2.2 Tp thanh ghi

Vi x l Cortex-M3 c cc thanh ghi 32 bit: 13 thanh ghi a dng, r0-r12 Stack Pointer (SP) Thanh ghi lin kt LR (Link Register), r14 Thanh ghi PC (Program Counter), r15 Thanh ghi trng thi chng trnh c bit (xPSR)

CPU Cortex l b x l da trn kin trc RISC, do h tr kin trc np v lu tr (load and store architecture). thc hin lnh x l d liu, cc ton hng phi c np vo mt tp thanh ghi trung tm, cc php tnh d liu phi c thc hin trn cc thanh ghi ny v kt qu sau c lu li trong b nh.

Hnh 2-11 Kin trc load v store ca vi x l ARM Cortex-M3 Ngun: http://www.arm.vn/default.aspx?tabid=748&g=posts&t=20

Do vy tt c cc hot ng ca chng trnh tp trung xung quanh tp thanh ghi ca CPU. Tp thanh ghi ny bao gm 16 thanh ghi 32 bit. Cc thanh ghi R0-R12 l cc thanh ghi n gin, c th c dng cha cc bin ca chng trnh. Cc thanh ghi R13-R15 c chc nng c bit trong CPU Cortex. Thanh ghi R13 c dng nh l con tr ngn xp (stack pointer). Thanh ghi ny c chia thnh nhm (banked), cho php CPU Cortex c hai ch hot ng, mi ch c khng gian ngn xp ring bit. c im ny thng c h iu hnh thi gian thc (Real Time Operating System) d dng c th chy m h thng ca mnh trong mt ch bo v. Trong CPU Cortex c hai ngn xp c gi l main stack v process stack. Thanh ghi R14 tip theo c gi l thanh ghi lin kt (link register). Thanh ghi ny c s dng lu tr cc a ch tr v khi mt cuc gi th tc (call a procedure) c thc hin. iu ny cho php CPU Cortex thc hin rt nhanh vic nhp v thot khi mt th tc. Nu chng trnh ca bn gi su vo nhiu lp chng trnh con, trnh bin dch s t ng lu R14 trn ngn xp.

Thanh ghi cui cng R15 l b m chng trnh (Program Counter); n l mt phn ca tp thanh ghi trung tm, n c th c c v thao tc ging nh bt k thanh ghi no khc.

Hnh 2-12 Tp thanh ghi ca vi x l ARM Cortex-M3 Ngun: http://www.arm.vn/default.aspx?tabid=748&g=posts&t=20

Thanh ghi XPSR Ngoi tp thanh ghi trung tm cn c mt thanh ghi ring bit c gi l thanh ghi trng thi chng trnh (Program Status Register). N khng phi l mt phn ca tp thanh ghi chnh v ch c teher truy cp thng qua hai lnh chuyn dng. XPSR cha mt s cc vng chc nng quan trng nh hng n vic thc thi ca CPU Cortex.

Hnh 2-13 Thanh ghi trng thi chng trnh ca vi x l Cortex-M3 Ngun: http://www.arm.vn/default.aspx?tabid=748&g=posts&t=20

Thanh ghi XPSR cng c th c truy cp thng qua ba bit hiu c bit cho php truy cp vo cc bit trong XPSR. Nm bit u l nhng c m iu kin v c gn bit hiu (aliased) nh thanh ghi trng thi chng trnh ng dng. Bn c N, Z, C, V (Negative, Zero, Carry v Overflow) s c thit lp

v xa ty thuc vo kt qu ca mt lnh x l d liu. Bit Q l c s dng bi cc lnh ton hc DPS ch ra rng mt bing t gi tr ti a hoc ti thiu ca n. Ging nh tp lnh ARM 32 bit, cc lnh Thumb-2 ch c thc hin nu m iu kin ca lnh ph hp vi trng thi ca cc c trong thanh ghi trng thi chng trnh ng dng. Nu m iu kin ca lnh khng ph hp, th lnh i ngang qua ng ng nh l mt lnh NOP (lnh ny khng lm g c). 2.3.3 c im ni bt ca Cortex-M3 Nu ngi dng s dng mt vi iu khin da trn li ARM, th s thy cc cng c pht trin c h tr tp lnh Thumb-2 v dng Cortex. Ngoi ra nh sn xut cng cung cp mt th vin iu khin thit b ngoi vi, mt b th vin pht trin USB nh l mt th vin ANSI C v m ngun l tng thch vi cc th vin trc c cng b cho vi iu khin STR7 v STR9. C rt nhiu RTOS m ngun m, thng mi v middleware (TCP/IP, h thng tp tin) h tr cho h Cortex. Dng Cortex-M3 cng i km vi mt h thng g li hon ton mi gi l CoreSight. Truy cp vo h thng CoreSight thng qua cng truy cp Debug , cng ny h tr kt ni chun JTAG hoc giao din 2 dy (serial wire-2 Pin), cng nh cung cp trnh iu khin chy g li, h thng CoreSight trn Cortex-M3 cung cp mt data watchpoint v mt cng c theo di (instrumentation trace). Cng c ny c th gi thng tin v ng dng c la chn n cng c g li. iu ny c th cung cp thm cc thng tin g li v cng c th c s dng trong qu trnh th nghim phn mm.