BBT 2103: COMPUTER ORGANIZATION

Lecture 5: Computer Arithmetic

Overview
In this lecture, we focus on the ALU and its operation
Overview of the ALU itself Data representation (review!) Computer Arithmetic and its H/W implementation

Reading: Stallings, Chapter 8

The ALU
ALU performs arithmetic and logical operations on data All other system elements are there (mainly) to bring data to the ALU for processing or to take results from the ALU In early machines, simplicity and reliability determined the overall structure of the CPU and its ALU
Result was machines built around a single register, the accumulator

Today general registers can be used as sources and destinations for many ALU operations
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Number Representation
Any number can be represented in any base by the simple sum of each digit's value, positional notation: d * basei Examples
The value 294 in decimal (29410) equals 2 * 102 + 9 * 101 + 4 * 100 The value 1011 (binary) equals 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 ( 11 in decimal).
As a 16 bit number this would be represented as follows:

0000 0000 0000 1011

With 16 bits it is possible to have unsigned numbers that range from 0 to 216 - 1 = 65535.
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Signed Integers
It is highly useful to be able to represent negative as well as positive integers. Several representation methods are possible:
Sign-magnitude format Ones Complement Format Twos Complement format

Signed-magnitude format
Positional representation using n bits Left most bit (MSB) position is the sign bit, which can be
0 for positive number 1 for negative number

Remaining n-1 bits represent the magnitude Range of numbers that can be represented is: {-2n-1-1, +2n-1-1} Problems:
Sign must be considered during arithmetic operations Has a dual representation of zero (-0 and +0)
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One's Complement format

Negative numbers are represented by a bit-by-bit complementation of the positive magnitude The sign bit is interpreted in the same way as sign magnitude format. The range of numbers that can be represented using this format is : {-2n-1-1, +2n-1-1} Example: for an 8-bit number
-1 = 1111 1110 +1 = 0000 0001

This representation still suffers from the problem of dual representation of Zero
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Twos Complement Format

Any negative number X can be represented using n bits by the the pseudo-positive number 2n - |X| Format has only one representation for 0 With the 2n symbols, the format can represent
2n-1-1 positive numbers 2n-1 negative numbers

All negative numbers have 1 in the most significant bit position, making sign detection very simple
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Twos Complement Format

Given the representation of +X, the Negation (-X) in twos complement format can be obtained as follows
Take the Boolean complement of each bit of the corresponding positive number( X), then add 1 to the resulting bit pattern

For Example to determine -7

+7 = 0111 Complement (Invert the bits) = 1000 Add 1 1 Result = 1001 = (-7)

Exercise: Convert the following decimal numbers into to two's complement binary 42, -70 9

Converting between word lengths

Converting between two word lengths (e.g. 16-bit format to a 32-bit format) requires sign extension
The sign bit is extended from its current location up to the new location. All bits in the extension takes on the value of the old sign bit

Example: Convert from 8 to 16 bits +18 = 00010010 +18 = 00000000 00010010 -18 = 11101110 -18 = 11111111 11101110
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Integer Addition of n-bit numbers

Addition is performed by adding bit by bit from right to left with carries passed to the next digit to the left Example: Perform the operation 7 + 6 0000 0111 7 + 0000 0110 +6 0000 1101 = 13 Exercise: Using a 4-bit 2s Complement representation perform the operations (a) 3+4 ; (b) 5+4; (c) -4 + -6; (d) -7 + -6
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Overflow
An overflow can occur whenever the sum of two N bit numbers cannot be represented by another N bit number To detect an overflow the following rule is observed
If both the operands are positive or negative, and the result is of the opposite sign, then overflow occurs

Overflows can be handled in several ways:

An exception or interrupt can be asserted A bit in a status register can be set It can be completely ignored
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Hardware implementation
A single full adder is the simplest hardware
Must implement an n-repetition for-loop for an nbit addition This is lots of overhead for a typical addition

Circuit Diagram

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The Ripple Adder Unit

The ripple adder uses n full adder units cascaded together In adding A and B together
unit i adds Ai and Bi to produce SUMi and CARRYi The carry out of each stage is the carry in to the next stage

A 4 bit ripple carry adder

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Ripple adder (2)

The Disadvantage of Ripple Carry
The carry bit may have to propagate from LSB to MSB In the worst case, it takes n times the delay of each adder unit to determine the results. Equivalent to an 2n gate delay

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Carry Look-ahead Adders

Alternatives to the ripple adder
do not wait for the carry to ripple through the circuit. entire adder Provides additional hardware to detect where carries will occur or when the carry propagation is completed

Carry Look-ahead Adders

Predict where carry outs will occur Generate all of the carries at once

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Integer Subtraction
Subtraction uses addition: The appropriate operand is negated before being added The following illustrates this (a) Direct subtraction 0000 0111 7 - 0000 0110 - 6 0000 0001 =1 (b) Using Twos Complement 0000 0111 7 + 1111 1010 +-6 0000 0001 =1
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Adder-Subtractor Hardware
The general hardware to accomplish addition and subtraction is shown below

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Multiplication Example
Example: using paper and pen perform 11 * 13
1011 x 1101 1011 00000 101100 1011000 10001111 (11) (13)

(143)

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Integer Multiplication
A number of methods exist for the implementation of multiplication
Repeated addition Shift and add High speed (special purpose) hardware multipliers

Repeated addition
Least sophisticated method Just use adder over and over again If the multiplier is n bits, can have as many as 2n iterations of addition Not used in an ALU
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Shift and Add

Computers version of the pen and paper approach The computer, however, accumulates the partial products into a running (partial) sum as the algorithm progresses Each partial product generation results in an add and shift operation

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Multiplication Implementation
A possible hardware implementation is shown below

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Multiplication Flowchart

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Execution Example

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Twos Complement Multiplication

To multiply signed numbers (2s complement) Normal shift and add does not work (no sign extension to 2n bits)

Convert numbers to positive magnitudes, multiple, then figure out the correct sign Or use a method that works for both positive and negative numbers
E.g Booths Algorithm

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Booths Algorithm
As in S&A, strings of 0s in the multiplier only require shifting (no addition steps) In other words
At the right end of a string of 1s in the multiplier (10), perform a subtraction At the left end of the string perform an addition (01) For all of the 1s in between, just do shifts

To determine operation (add and shift, subtract and shift, shift) examine the bits Q0Q-1
00 or 11: just shift 10: subtract and shift 01: add and shift
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Booths Algorithm

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Example of Booths Algorithm

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Booths Algorithm (2)

Hardware modifications required in Figure of slide 22
Ability to perform subtraction Ability to perform arithmetic shifting rather than logical shifting (for sign extension) A flip flop for bit Q-1

Advantages of Booths Algorithm:

Treats positive and negative numbers uniformly Strings of 1s and 0s can be skipped over with shift operations for faster execution time

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High Speed Hardware Multipliers

High performance multipliers
Reduce computation time by employing more hardware than found in a S&A multiplier Not generally used in general-purpose processors due to expense Examples
Combinational multipliers Pipelined Wallace Tree adders

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Integer Division
Once you have committed to implementing multiplication, implementing division is a relatively easy next step that utilizes much of the same hardware The goal is to find a quotient, Q, and remainder, R, such that
D=QxV+R

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Integer Division Example

Divide a) 10010011 by 1011 b) 100010 by 1000
00001101 1011 10010011 1011 001110 1011 001111 1011 100

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Restore Division
Adapted from pen and paper approach Uses essentially the same ALU hardware as the Booth multiplication algorithm

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Integer Division Flowchart

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Signed Integer Division

For twos complement numbers, we must deal with the sign extension problem Sample Algorithm:
Perform division operation as normal If the signs of the divisor and the dividend were the same, quotient is correct, otherwise, Q is the 2s complement of the quotient

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Floating Point Representation

Integer fixed point schemes do not have the ability to represent very large or very small numbers
Fixed point (integer): -2n-1 (2n-1 1)

Requires the ability to dynamically move the decimal point to a convenient location
Similar to scientific notation: 3.14159 x 1023

Format: +/-S x B +/-E

where S is significand (or mantissa), and E is exponent, B is base
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Floating Point format

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Floating Point format

A floating point number can be expressed in several ways
e.g. 1.0 x 105 = 0.1 x 106 = 10.0 x 104

To simplify operations on fp numbers, the mantissas are stored in a normalized format

i.e. 0.1xxxxx Since the 1 is required, there is no need to explicitly store it in the data word

Exponents can be positive or negative values

Use biasing (Excess coding) to avoid operating on negative exponents Bias is added to all exponents to store as positive numbers
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Range vs Precision
For a fixed n-bit representation length, there are 2n combinations of symbols If floating point increases the range of numbers in the format (compared to integer representation) then the spacing between the numbers must increase
This causes a decrease in the formats precision

If more bits are allocated to the exponent, range is increased at the expense of decreased precision Similarly, more mantissa bits increases the precision and reduces the range
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Example
For a 32 bit number
8 bit exponent
+/-2256 1.5 x 1077

23 bit mantissa 2-23 1.2 x 10-7

About 6 decimal places

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Problem with FP Representation

Problems to deal with in the format
Representation of zero Over and underflow and how to detect Rounding operations

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IEEE 754 format

Standard for floating point storage on Different Platforms The IEEE 754 format defines single and double precision formats (32 and 64 bits)
8 and 11 bit exponent respectively Mantissa of form 1.xxx with 1 hidden Has extended formats (both mantissa and exponent) for intermediate results

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IEEE 754 format (cont.)

Single precision
Range 10-38 to 10+38 8-bit exponent with 127 bias 23-bit mantissa

Double precision
Range 10-308 to 10+308 11-bit exponent with 1023 bias 52-bit mantissa

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FP Arithmetic
Addition and subtraction
First, align decimal points Then, add or subtract mantissas Finally, normalize result

Example
9.997 x 102 4.631 x 10-1 Sum Normalized 9.997000 x 102 0.004631 x 102 10.001631 x 102 1.0001631 x 103

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FP Arithmetic
Multiplication
Add exponents Multiply mantissas Post normalize

Division
Subtract exponents Divide mantissas Post normalize

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Summary
Looked at the basic concepts associated with computer arithmetic
Number representation Basic ALU construction Hardware and software algorithms Floating point numbers and arithmetic

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