library ieee;

use ieee.std_logic_1164.all;
entity simple_fir is
generic (taps : integer_vector);
port (
clk

: in

std_logic;

sample

: in

integer;

filtered : out integer := 0);

end entity simple_fir;
--------------------------------------------------------------------------------------------------------------------------------architecture a1 of simple_fir is
begin

-- architecture a1

process (clk) is
variable delay_line : integer_vector(0 to taps'length-1) := (others => 0);
variable sum : integer;
begin

-- process

if rising_edge(clk) then

-- rising clock edge

delay_line := sample & delay_line(0 to taps'length-2);

sum := 0;
for i in 0 to taps'length-1 loop
sum := sum + delay_line(i)*taps(taps'high-i);
end loop;
filtered <= sum;
end if;
end process;
end architecture a1;
---------------------------------------------------------------------------------------------------------------------------------- testbench
--------------------------------------------------------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity tb_simple_fir is
end entity tb_simple_fir;
architecture test of tb_simple_fir is
-- component generics
constant lp_taps : integer_vector := ( 1, 1, 1, 1, 1);
constant hp_taps : integer_vector := (-1, 0, 1);
constant samples : integer_vector := (0,0,0,0,1,1,1,1,1);
signal sample

: integer;

signal filtered : integer;

signal Clk : std_logic := '1';
signal finished : std_logic;
begin

-- architecture test

DUT: entity work.simple_fir

generic map (taps => lp_taps)

-- try other taps in here

port map (
clk

=> clk,

sample

=> sample,

filtered => filtered);

-- waveform generation
WaveGen_Proc: process
begin
finished <= '0';
for i in samples'range loop
sample <= samples(i);
wait until rising_edge(clk);
end loop;
-- allow pipeline to empty - input will stay constant
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
finished <= '1';
report (time'image(now) & " Finished");
wait;
end process WaveGen_Proc;
-- clock generation
Clk <= not Clk after 10 ns when finished /= '1' else '0';
end architecture test;