Ree wemn FE 1 WS AH A Pa DT, AP LAH TD SOY FHS PCIBASE_ADDRESS_O i PCIBASE_ADDRESS_1 (Ji 78 #179 47) this F 1 ASM. PCL PSEA RAZ lil, HR PCLPRIMARY_BUS 4! PCILSECONDARY_BUS IA 2 at #208 THEE FSW SES, Fe PCI_SECONDARY_BUS a 22% PCI SFE AYE AI.A82%, Th] PCLSUBORDINATE_BUS St) ii! BEELR, ZED SARE CR ANY SAktt Ze. CPU THOSE ROTTER RE LIE, TLL PREP S BEB IME. 4 CPU FE /O 8977 2 OxCR8 HS A—MoR er HWAEBL, ALOR Free, SES PCL SHE SHEP MBAS SAS BASAL, UREA SEA REBFAPRE, Wee —Hieie+ BASS PCLSUBORDINATE_BUS PRIA BStHE, MRA PEASE TMT, RIL ALMA FINS RR PCI HE, BAVARIA TER. SF, RARARA AME. WHR, BAER RARER, sek TAC, CPU RELAIS Ay KO AS a dT TIRE, PRAAE 1 USK Be Ht eae ee 8 tt A BS I ST eR JG Ff 2 BLAME “PCL-CardBus $f" ff), CardBus 2 Ei AM, BANE BABE. BF PCL SARA EVE AUS PAPE, PC PLBLEPIIZE BIOS BRET PCL SRE, EN PCL AeA RSNA SURE RNS RS. HP PCL BRAS ECAR SIRO BTL TUS ic BL 2 OT AS RE ACER EU DR BIOS WEP RRS. ALE BIULL EY PC BLE READ PRA RP RAAT, BIOS HUL32 0 T — MEP ARAY PCI ETAL, Bhi tr tRR A SRBRATEY CPU iF. SBE T HED AE SIRI BIOS #5 “PCI BIOS”. 5138184 Linux Ay iK ta (RAE BIOS FERN PCL RU BCSATAC BEE, (GR OAT A ay PCI AREA PRET BIOS. BLE, 2 ‘RA PCI BIOS HELIS HEA EEA. BIZE BRAG Linux ABEL 8S PCT ARETE (UR, AB RAR RA ALE, AM A BIOS RET MAF. BUPA TE BHAT. Aid, EAH Linux ARTEL PCI BIOS HERMES, HOARE BAM BA AR peibios. JSP BL7E AYR LAH A BIOS, ALBEIT SS) RRR RAR, BEST WRL. BVA IL MCE PR, 1 Mee oN RL ia 5 7F-BS OXCFS 4 OXCFC RS HAR a EMC AA SERRA AY. MERC RE AS APSE AIRS HEIRS, AO MF. 32 ARF ATES. AHI RACHA gee TESTER ROUGE P RUE EE AER, SNEEZE driversipeilpei.c Ps 418 /* 479 * rappers for all PCT configuration access functions. They just check 480 * alignment, do locking and call the low-level functions pointed to 481 * by pei_dev->ops. 482 #/ 483 484 define PCI byte BAD 0 485 define PCI word BAD (pos & 1) 486 define PCT_dword BAD (nos & 3) 487 +185.Linux BOR 488 #define PCI_OP(rw, size, type) \ 489 int pci_##rwe# config ##size (struct pci_dev *dev, int pos, type value) \ 490 \ 491 int res; \ 492 unsigned long flags; \ 493, if (PCI_##sizot## BAD) return PCIBIOS_BAD_REGISTER NUMBER; —\ 494 spin_lock_irgsave(&pci_lock, flags); \ 495 ves = dev->bus~Dops>rwi#t ##size(dev, pos, value); \ 496 spin_unlock irgrestore(@pei_lock, flags) : \ 497 return res; \ 498} 499 500 PCI_OP(read, byte, u8 *) 501 PCI_OP(read, word, ul6 *) 502 PCI_OP(read, dword, u32 *) 503 © PCL_OP(write, byte, u8) 504 PCI_OP(write, word, ul6) 2X 501 AF HB, Bt goo WAAR HAH BREE wT BH Me pci_read_config_word( JA X+ int pei_read_config_word (struct pci_dev *dev, int pos, ul6* value) int res; unsigned long flags; if (PCI_vord_BAD) return PCTBTOS_BAD_REGISTER NUMBER; spin_lock_irgsave (&pci_lock, flags) ; res = dey->bus->ops->read_word(dev, pos, value) ; spin_uniock_irgrestore (&pci_lock, flags) ; return res; } fal FF Sh, HE fh JL 47 BL BE KT pei_read_config_byte( ) . pci_read_config_dword( ) , pei_write_config_byte( ), pei_write_config_word( )F aa HN Me FP pci_read_config_word( )HU((F3. A ItIH tH HetE PCIword_BAD RreiHEbL pos B45 16 th FLA A, WRF RCE AAS fe FP iin ae Piast ce ET CARE. ES A dev HHPRA Bi iN pei_dev BURGH, TATE BH pci_dev SARIN EN, RE BUNT AMI — BOT ROLE. KM AT MEET bus, RAB RARE pei_bus SHR 45+ ML), if pci_bus Sifa'h MAMET ops, Fil—4* pei_ops SGESiH9, ix MCE #4lN EX ZE includeflinux/pei.h P: 424 /* Low-level architecture-dependent routines */ 425 426 struct pei_ops { 427 int (*read_byte) (struct pci_dev *, int where, u8 *val); 428 int (read word) (struct pci_dev *, int where, ul6 #val); + 186 +RS MT 429 int Gkread_dword) (struct pei_dev *, int where, u92 4val); 430 int (#write_byte) (struct pei_dev *, int where, u8 val); 431 int (write word) (struct pei_dev *, int where, ul6 val); 432 int (twrite dword) (struct pei_dev *, int where, u32 val); 433}; SB, AR PM de, SG RATTE TIL Se PBL A — AR Ea HO. CR HP BR GE RHEE RAR AD R/S PCL LS MAL ELE TE SERY. AUP AT pci_ops BaRSIM, SHH TAT iB 1 AL” A “2 0” AY PCL AD RAP TERRE YE GQERRAVZ | 141 2 MAVILAB), LL AGES BIOS SEmAvee {E3952 SF arch/i386/kerneVpci-pe.c. CPU Ze Ui HIN ARTE A FEE SON BES MYR I = I HORA. fe PCL ARRAN TAR, APSE “TAE—PCI BF” BALL “2 AU” PCI ACR ASTER BRE, (LR a2 de PCT MR bR HESS LES A SOE ASE PHL “FR E—-PCI Bh". HFLL, pei_direct_conf2 Au T SATB TE RUA Pee TCR ATRIA, SEE AA SHEFF pei_direct_confl « a2 static struct pci_ops pei_direct_confl = { 83 pei_confl_read_config byte, 84 pei_confl_read_config word, 85 pei confl read_config dvord, 86 pei confl write config byte, 87 pei_confl_write config word, 88 pei_confl_write config dword 89}; WML, LM pei_read_config_word( )JEiH i pci_confl_read_config_word( )7E AIH, JACH3ZE arcl/i386/kernel/pci-pe.c ‘T's 45 static int pei_confl_read_config_word(struct pci_dev #dev, int where, uJ6 #value) 46 47 cout (CONFIG_CMD (dev, where), OxCFS) ; 48 vvalue = inw(0xCFC + (where&2)) ; 49 return PCIBIOS_SUCCESSFUL; 50} EPL VEEL OxCF8 #1 OxCFC APY FEARS EM. ST AAR, PUTTER RAB GB, LDL TPO ENR BA AGEN F pei-pe.c). 153 static struct pei_ops pei_direct_conf2 = ( 154 pei_conf2 read config byte, 155 ‘onf2_read_config word, 156 pei_conf2_read_config dvord, 137 pei_conf2_write_config_byte, 158 pei_conf2_write_config word, 159 pei__conf2_write_config_dword 160} + 187»