CHNG 3

B NH BNG ROM

B NH BNG ROM

3.1

Tng quan

3.2
3.3

Cu trc v phn lai

Thit k h t hp dng ROM

3.4

Thit k h tun t dng ROM

3.1

Tng quan:

B nh bn dn c chia ra lm 2 lai chnh:

B nh bng (table memory) B nh hm (function memory): Cha cc hm logic (Boolean) thay v l cc bng. Mi bin ca bng chntr c th c biu din bng hm logic. Vi cc b nh bng, a ch A c nh ngha trong
dy: 0 A 2N -1

V d: Bng cho ROM c N=3bit a ch, m=2 bit d liu

Vit di dng tch chun th hm logic ca bin d0 v d trn l:

3.1

Tng quan:

B nh bn dn chia lm 2 loi chnh:

B NH BN DN
Vi: RAM= Random Access Memory (b nh truy cp ngu nhin)

ROM= Read Only Memory

M= Mask Programmed (c lp trnh bng che mt n) P = Programmable (lp trnh c, kh lp trnh) EP = Erasable and Programmable EEP = Electrically Erasable and Programmable (xa v lp trnh bng in) PLD = Programmable Logic Device PLA = Programmable Logic Array (mng logic lp trnh c) PAL = Programmable Array Logic (logic mng lp trnh c) LCA = Logic Cell Array (Mng t bo logic)

3.2 ROM (Read-Only Memory)

3.2.1 ROM:
ROM l mt mch t hp c n ng vo v m ng ra (hnh 3.1). Cc ng vo c gi l cc ng vo a ch (address inputs) v thng c t tn l A0, A1 ,..., An-1. Cc ng ra c gi l cc ng ra d liu (data outputs) v thng c t tn l D0, D1 ,..., Dm-1.

Kch thc ca ROM l 2n x m (bit)

Ni dung ca ROM cha bng chn tr ca mt hm logic t hp n ng vo, m

ng ra: c m+n ct v 2m hng. B qua cc tr hon thi gian, cc ng ra d liu

ca ROM mi lc l cc bit ra ca hng trong bng chn tr c chn bi cc ng vo a ch. V d: Bng chn tr cho hm t hp c 3 ng vo v 4 ng ra

Bng 3.1: Bng chn tr ca hm logic t hp 3 ng vo, 4 ng ra Ch : - C th dng ROM nh bt c phn t logic t hp no - ROM l b nh khng bc hi v ni dung ca n vn gi c ngay c khi khng cp in.

3.2.2 Dng ROM cho cc hm logic t hp ngu nhin:

Bng 3.1 l bng chn tr ca b gii m 2 sang 4 vi iu khin cc tnh ng ra, hm ny c th xy dng bng cc cng nh hnh 3.2

Hnh 3.2 B gii m 2 sang 4 vi iu khin cc tnh gi tr ra

3.2.2 Dng ROM cho cc hm logic t hp ngu nhin: (tt)

Nh vy ta c 2 cch xy dng b gii m : vi cc cng ri, hoc vi ROM 8x4 m cha bng chn tr nh hnh 3.3.

Hnh 3.3 Kt ni xy dng b gii m 2 sang 4 dng ROM 8x4 Ch : Vn hon v cc ct bit trong bng chn tr ca hm cn ghi ROM.

Khi dng ROM cha mt bng chn tr cho trc, cc tn hiu xut v nhp
c t phi sang tri trong bng chn tr thng c gn vo cc ng vo a ch v ng ra d liu ca ROM vi cc nhm theo th t tng dn. Khi thit k dng ROM ta cn xc nh kch thc v bng chn tr ca ROM

3.2.2 Dng ROM cho cc hm logic t hp ngu nhin: (tt)

V d: Dng ROM thc hin hm nhn nh phn khng du cho 2 s nh
phn 4 bit. Nu dng mch ri ta dng cc IC 74284 v 74285, cn dng ROM th s dng ROM 28 x 8 (256 x 8) vi kt ni nh hnh 3.4

Hnh 3.4 Kt ni thc hin nhn nh phn khng du dng ROM 256x8

3.2.2 Dng ROM cho cc hm logic t hp ngu nhin: (tt)

Ni dung ghi ROM trn nh sau (dng file vn bn hex):

3.2.2 Dng ROM cho cc hm logic t hp ngu nhin: (tt)

Ni dung ghi ROM trn nh sau (dng file vn bn hex):

3.2.3 Cu trc ni ca ROM:

C ch s dng ROM lu tr th thay i ng vi cc cng ngh ca ROM khc

nhau. Trong phn ln cc ROM, s xut hin hoc vng mt ca mt diode hay
transistor s phn bit gia 0 v 1.

3.2.3 Cu trc ni ca ROM: a./ Cu trc vi gii m 1 chiu:

S ROM 8x 4 vi cu trc gii m 1 chiu (dng 1 b gii m TTL v cc diode).

b./ Cu trc vi gii m 2 chiu:

Nu xy dng mt ROM 128x1 dng cu trc phn trc phi s dng
mt b gii m 7 sang 128, ngha l phi s dng n mt lng ln 128 cc cng NAND 7 ng vo, nu thit k cho ROM vi hng triu bit hoc nhiu hn s khng c b gii m 20 sang 1048576. Thay vo ngi ta s s dng cu trc khc c gi l gii m hai chiu (two-dimentional decoding). 3 bit a ch cao A6A5A4 s chn hng, mi hng cha 16 bit bt u ti a ch A6A5A40000. Khi t a ch cho ROM, 16 bit hng c chn a vo b MUX v 4 bit a ch thp s chn bit data mong mun.

b./ Cu trc vi gii m 2 chiu:

Ngoi vic gim tnh phc tp vic gii m, gii m 2 chiu c mt thun li
khc l ROM c mt kch thc vt l gn vung, iu ny quan trng cho vic ch to v ng gi IC Vi ROM c nhiu ng ra d liu, cc dy lu tr tng ng vi mi ng ra d liu c th c lm hp hn t c b tr chip gn vi hnh vung hn. V d, Mt b tr ca ROM 32K x 8:

3.2.4 Cc kiu ROM thng mi:

3.2.4 Cc kiu ROM thng mi:

Cc ROM thng dng nht l cc EPROM: 2764, 27128, 27256, v 27512

Ch :

Chn VCC phi ni vi +5V Chn VIH phi ni vi tn hiu logic HIGH hp l Chn VPP dng a vo in p lp trnh

3.2.5 Cc ng vo iu khin v nh th ROM:

Cc ng ra ca ROM thng phi c ni vo mt BUS 3 trng thi, cc
thit b khc c th li BUS cc thi im khc nhau. Do , phn ln cc chip ROM thng mi c ng ra d liu 3 trng thi v mt ng vo Output Enable (OE: cho php xut) cho php cc ng ra. Nhiu ng dng ROM c bit l ng dng lu tr chng trnh s c nhiu ROM c ni chung vo 1 BUS, mi ln ch c 1 ROM li BUS. Phn ln cc ROM c ng vo chip select (CS: chn chip) lm n gin vic thit k cc h thng. Ngoi OE cn cn phi c CS cho php ng ra 3 trng thi. Tuy nhin trong nhiu ROM, CS cng lm vic nh ng vo ct ngun cp in (power down input), CS mc khng tch cc th khng cp ngun cho cc decoder ni, cc driver v cc MUX ca ROM. ch ch ny (standby mode) 1 ROM tiu th t hn 10% cng sut so vi ch hot ng (active mode).

3.2.5 Cc ng vo iu khin v nh th ROM:

Hnh sau ch cc ng vo CS v OE c s dng nh th no bn trong
mt ROM tiu biu

3.2.5 Cc ng vo iu khin v nh th ROM:

Cng m ba trng thi (Tristate Output Buffer):
- 3 trng thi (tristate): LOW / HIGH / HIGH impedance - Trng thi tng tr cao (HIGH impedance): ng ra h mch - Ng iu khin 3 trng thi: * HIGH: The buffer is Active * LOW: HIGH impedance

3.2.6 Thit k h tun t dng ROM:

C th thit k d dng mt h tun t dng ROM kt hp vi cc FF. M hnh tng qut ca h tun t dng ROM v cc D-FF c xung nhp:

Phn t hp ca h tun t c th dng ROM thc hin cc hm ra (Z1, Z2, , Zn) v cc hm trng thi k (Q1+, Q2+, , Qk+).

3.2.6 Thit k h tun t dng ROM:

Trng thi ca h c cha trong mt thanh ghi (to bng cc D-FF) v a hi tip v ng vo ca ROM. Nh vy h tun t vi m input, n output v k bin trng thi c th c ci t bng k D-FF v ROM vi (m+k) input (ngha l 2m+k t [word]) v (n+k) output.

Thng dng D FF hn JK FF v s dng cc FF vi 2 ng vo s cn phi

tng s ng ra ROM.

3.2.6 Thit k h tun t dng ROM:

V d, Thit k mch chuyn i m BCD sang m qu 3, ng vo v ra l
ni tip vi LSB i trc.

Ta c bng nh sau:

Bng trn lit k cc input v output mong mun ti cc thi im t0, t1, t2 v t3

Ta thnh lp bng trng thi nh sau:

Rt gn bng trng thi bng cch so cc hng ging nhau th gom li. Khi

so cc hng c cha du gch ngang (y l trng hp dont care) th du

gch ngang s khp vi bt c trng thi no hoc bt c gi tr ra no. Bng cch so khp cc hng theo cch ny, ta c H I J K L v M N P, sau

khi kh I, J, K, L, N v P thy rng E F G v bng c thu gn thnh 7

hng nh sau:

C th dng mt cch khc suy ra bng trn bng cch bt u bng gin trng thi. Gin trng thi c dng hnh cy. Mi ng bt u trng thi reset biudin mt trong 10 chui vo c th c.

Bng gn trng thi v bng chuyn trng thi:

Ci t b chuyn i m ny dng ROM v cc D-FF. V c 7 trng thi

nn cn 3 DFF. Nh vy cn ROM c 4 input (24 word) v 4 output . Dng gn

nh phn trc tip, xy dng bng chuyn trng thi cho trng thi k ca cc D-FF nh l hm ca trng thi hin ti v input.

V ang s dng cc D-FF, D1 = Q1+, D2+ = Q2 , D3+ = Q3 Bng chn tr cho ROM xy dng c d dng t bng chuyn trng thi. Nh vy cc output ca ROM (Z, D1, D2, D3) l cc hm ca cc input ca ROM (X, Q1, Q2, Q3).

Bng chn tr cho ROM:

Ci t mng tun t dng ROM: