BT-IC input clock, input reset, input [31:0] instruction, //Lnh 32 bit vo c m ha input [31:0] data_i, // D liu t CPU

U input [31:0] address, // a ch t CPU input [31:0] mReadData, // D liu t b nh input MemRead, // Lnh c d liu t CPU input MemWrite, // Lnh ghi d liu t CPU input dataMem_Ready, // Tn hiu cho php c t b nh input Byte, // Load/Store d liu 8 bit input Half, // Load/Store d liu 16 bit input SignExtend, // D liu m rng 32 bit input Left, // Load/Store 16 bit bn tri input Right, // Load/Store 16 bit bn phi

output [31:0] pc, //Program Couter output reg [31:0] data_o, // D liu n CPU output [31:0] MWriteData, // D liu n b nh output reg [3:0] WriteEnable, // Ghi tn hiu Enable cho mi //4 bytes ca b nh output ReadEnable, // c tn hiu Enable ca b nh output M_Stall, output EXC_AdEL, // Load Exception( Ngoi l) output EXC_AdES // Store Exception( Ngoi l) Khi ta mun thc hin mt chng trnh th u tin CPU gii m lnh cn thc hin sau CPU ly a ch ca d liu trong b nh cho vo bin address v gi lnh c ti b nh MemRead, nu tn hiu sn sng dataMem_Ready mc tch cc th CPU s load d liu t b nh ln x l ty theo kiu d liu nu 32 bit CPU s load lm 2 chu k mi chu k 16 bit. Khi d liu c x l xong bin m chng trnh PC s tng ln 2 trong trng hp lnh 16-bit MIPS16e hoc 4 nu 32 bit trc khi cu lnh tip theo c thc hin.

Hin ti d liu c x l ang trong CPU, thc hin lnh tip theo th CPU phi xut d liu ra b nh. lm vic ny, b x l gi mt lnh ghi d liu ti b nh v c tn hiu Enable ca b nh, nu tn hiu mc tch cc th b nh sn sng ghi d liu t CPU ra b nh hay cn gi l lu tr d liu-store( tng t nh khi c d liu).