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6.1 Gii thieu 6.2 Ly thuyet hoat ong cua JFET 6.3 Ly thuyet hoat ong cua MOSFET 6.4 Giai tch o th va phan cc 6.5 Giai tch tn hieu ln S sai dang 6.6 Giai tch tn hieu nho 6.7 M rong
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6.2.2 Hoat ong: Gia s S va G noi at; vDS > 0: Dong iD : D S: Phu thuoc vao vDS va ien tr kenh n (Rn-Channel) Dong iChannel Gate 0: Do Diode tao bi tiep xuc pn Channel-Gate phan cc nghch (a) Khi vDS tang: Vung khuyet (depletion region vung gach cheo) tang Rn-Channel tang
(b) vDS = Vpo (ien ap nghen: pinch-off voltage): Hai vung khuyet cham nhau: iD = Ipo
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Gia s vDS = const; vGS thay oi: vGS < 0: Tang vung khuyet i) RChannel tang iD giam ii) Vpo giam vGS > 0: Giam vung khuyet i) RChannel giam iD tang ii) Vpo tang
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Lu y: n-JFET: Phan cc sao cho khong co dong IChannel-Gate (vGS 0 hoac vGS nho > 0) 6.2.3 ac tuyen: ien ap vDS tai iem nghen: vDS-Pinch Off = Vp = Vpo + vGS ien ap anh thung: BVDSX BVDSS + vGS ac tuyen VA trong vung bao hoa (Gia ien ap nghen va anh thung: Vp < vDS < BVDSX) 3/ 2 3v v iD = I po 1 + GS + 2 GS vi vGS < 0 V V po po Nhan xet: vGS = 0: iD = Ipo
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VGS = - Vpo: iD = 0 Trong vung bao hoa: iD khong phu thuoc vDS Anh hng nhiet o: 3/ 2 3/ 2 v 3v T iD = I ' po 0 1 + GS + 2 GS V V po T po trong o: Ipo = iD khi vGS = 0 tai nhiet o T0.
Nhan xet:
Ban au cha co kenh dan gia D va S (enhancement mode) Cc cong Gate: Metal Oxide Semiconductor (MOS)
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6.3.2 Hoat ong: Hoat ong loai tang (enhancement mode): vGS > 0: Hnh thanh kenh dan cam ng: vGS > VTN : ien ap ngng Tao kenh dan n cam ng gia S va D
vGS tang Be rong va ien dan (conductivity) kenh dan tang Thay oi vDS: Tng t JFET: (a) Khi vDS tang Tang vung khuyet Rn-Channel tang: Vung tuyen tnh
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(c)
o th:
6.3.3 ac tuyen: ien ap vDS tai iem nghen: vDS Pinch Off = Vp = vGS VTN = vGS + Vpo (Vi Vpo = - VTN < 0) ac tuyen VA trong vung tuyen tnh (vDS < vGS - VTN = Vp): 2 i DS = k n [2(vGS VTN ) v DS ] ac tuyen VA trong vung bao hoa (vDS vGS - VTN = Vp):
i DS v = k n [vGS VTN ] 2 = I po 1 + GS vi Ipo = knVTN2 va Vpo = - VTN V po n-JFET: vGS 0, Vpo > 0; Enhancement mode n-MOSFET: vGS > 0, Vpo < 0 ac tuyen VA: JFET: Bac 3/2 MOSFET: Bac 2
2
Nhan xet:
Xem gan ung cho ca hai loai FET: i DS = k n [vGS Anh hng nhiet o: 3/ 2 ' To I po = I po T
v VTN ] 2 = I po 1 + GS V po
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9 DCLL: VDD = vDS + iD (Rd + Rs) 9 Phng trnh phan cc: vGS = - iD Rs (Xem iG 0) Nhan xet: Mach t phan cc (self-bias): Do vGS < 0 tao ra bi Rs V du: Thiet ke mach vi tnh iem Q: VDSQ = 15V; IDQ = 3,5 mA Thay vao DCLL: Rd +Rs = (VDD VDSQ) / IDQ = (30 15) / 3,5 = 4,3 K T ac tuyen VA: VGSQ = -1 V Rs = - VDSQ / IDQ = 1V / 3,5 mA = 286 Rd 4 K Chon Rs = 270 va Rd = 3,9 K
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6.4.2 Phan cc MOSFET: Cong phan cc thuan (forward-biased gate) s dung mach phan cc ngoai (tng t BJT):
9 DCLL: VDD = vDS + iD (Rd + Rs) R1 9 Phng trnh phan cc: vGS = R +R V DD i D RS = VGG iD Rs 1 2 R1 trong o: VGG = R +R V DD : ien ap cung cap cho cc cong 1 2 Nhan xet: Rs: Cai thien s on nh tnh iem Q bang dong DC hoi tiep. R3: Khong co tac dung DC, dung e tang tr khang ngo vao AC. Bai toan: Xac nh mach phan cc (VGG, Rs, Rd) e cc tieu hoa s thay oi Q theo t0
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3/ 2 vGS ' T0 T phng trnh: i D = I po 1+ T V po di / i 3/ 2 iD o nhay: S T = D D = dT / T V RS i D RS 1 + 2 I 'po (To / T ) 3 / 2 1 + GG V V po po Nhan xet: Rs 0 lam giam o nhay iD theo t0 Cai thien o on nh iD e cc tieu S T :
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