B CNG THNG TRNG CAO NG K THUT CAO THNG KHOA IN T - TIN HC

TI:

THIT K BNG PHA MU LED MA TRN DNG IC GHI DCH CD4094 V VI X L PIC 16F877A.

Vi s pht trin khng ngng ca khoa hc cng ngh, cuc sng con ngi ngy cng tr nn tin nghi v hin i hn. iu em li cho chng ta nhiu gii php tt hn, a dng hn trong vic x l nhng vn tng chng nh rt phc tp gp phi trong cuc sng. Vic ng dng cc thnh tu khoa hc k thut hin i trong tt c cc lnh vc v ang rt ph bin trn ton th gii, thay th dn nhng phng thc th cng , lc hu v ngy cng c ci tin hin i hn, hon m hn. Cng vi s pht trin chung , nc ta cng ang mnh m tin hnh cng cuc cng nghip ha v hin i ha t nc theo kp s pht trin ca cc nc trong khu vc v trn th gii. Trong lnh vc in t ang ngy cng ng vai tr quan trng trong vic pht trin kinh t v i sng con ngi. S ph bin ca n ng gp khng nh ti s pht trin ca tt c cc ngnh sn xut, gii tr, ...trong nhng nm gn y c bit trong lnh vc gii tr, qung co c s pht trin mnh m vi nhiu hnh thc, phng php tip cn, qung b v chia s thng tin hin i v ton din hn. Vi lng am m, yu thch ca mnh trong lnh vc ny, nhm chng em quyt nh chn ti Thit k bng pha mu led ma trn dng IC ghi dch cd4094 v vi x l Pic 16f877a lm n tt nghip. Trong thi gian ngn thc hin ti cng vi kin thc cn nhiu hn ch, nn trong tp n ny khng trnh khi thiu st, nhm thc hin rt mong c s ng gp kin ca thy c v cc bn sinh vin.

LI CM N
Trong sut kha hc (2006-2009) ti Trng Cao ng K Thut Cao Thng, vi s gip ca qu thy c v gio vin hng dn v mi mt t nhiu pha v nht l trong thi gian thc hin ti, nn ti c hon thnh ng thi gian qui nh. Nhm thc hin xin chn thnh cm n n : Qu thy c trong khoa in t -Tin hc ging dy nhng kin thc chuyn mn lm c s thc hin tt n tt nghip v to iu kin thun li cho nhng ngi thc hin hon tt kha hc. c bit,thy TNG THANH NHN gio vin hng dn ti nhit tnh gip v cho nhm thc hin nhng li ch dy qu bu, gip nhm thc hin nh hng tt trong khi thc hin n. Tt c bn b gip v ng vin trong sut qu trnh lm n tt nghip.

MC LC
NHN XT CA GIO VIN HNG DN NHN XT CA GIO VIN PHN BIN NHN XT CA HI NG BO V LI NI U LI CM N CHNG 1: DN NHP. 1.1 T VN . 1.2 MC CH YU CU CA TI. 1.3 GII HN CA TI . Trang 1 Trang 1 Trang 1 Trang 1

CHNG 2 : CC LINH KIN S DNG TRONG MCH. 2.1 DIODE PHT QUANG ( LED N). 2.2 IN TR . 2.3 T IN. 2.4 IC CD4094. 2.5. VI X L PIC16F877A. CHNG 3:BNG PHA MU LED MA TRN. 3.1. GII THIU V BNG PHA MU LED MA TRN. 3.2. NGUYN L LM VIC CA MCH. 3.2. S NGUYN L MCH IN. 4.M NGUN CHNG TRNH. LI KT TI LIU THAM KHO

Trang 2 Trang 2 Trang 3 Trang 4 Trang 8 Trang 12 Trang 68 Trang 68 Trang 71 Trang 72 Trang 75

CHNG 1: DN NHP.
1.1 T VN . Ngy nay cng vi s pht trin ca cc ngnh khoa hc k thut, k thut in t m trong l k thut s dng vi x l v cc linh lin in t khc c tnh cht hin th nh led 7 on, led ma trn, led n vo cc ng dng thc t nh nhm p ng nhu cu ngy cng nhiu trong cc lnh vc khc nhau nh hin th, bng qung bo, . do chng ta phi nm bt v vn dng n mt cch c hiu qu nhm gp phn vo s pht trin nn khoa hc k thut th gii ni chung v trong s pht trin k thut in t ni ring. Xut pht t thc t m nhm sinh vin thc hin chng em c iu kin tip xc v tham quan ti mt s c s ti nhiu im trong thnh ph, rt nhiu cc bng qung co, logo u c hin th thng qua cc linh kin quang. Tuy nhin ty theo tnh cht v mc s dng m cc linh kin quang ny c th khc nhau, c ni th s dng led ma trn nhiu mu, led ma trn mt mu, led n nhiu mu, led n mt mu. T nhng iu thy c v trong kh nng ca chng em, chng em mun thit k mt mch quang bo m cng c th p ng c nhng yu cu nh trn. 1.2 MC CH YU CU CA TI. Trong n ny chng em thc hin mch hin th thng qua led n nh cc tn hiu c xut ra t vi x l 16f877a. Tn hiu t vi x l a ra cho ic cd4094 ghi dch t ic cd4094 iu khin cc led n vi mt khong delay nht nh s hin th c cc hnh nh, vn bn m ta mun hin th. T nhng vn trn th yu cu cn thit khi thit k mch ny l: - Lp trnh bng CCS. - B phn hin th phi r rng. - iu khin 3 mu c bn RGB. - a vo cc hiu ng mu sc cho bng led. - a vo cc hiu ng ch,s cng nhiu cng tt. 1.3 GII HN CA TI. Do kin thc cn hn ch,linh kin c nhng con ln u tin s dng nn trong qu trnh thi cng phn cng ca mch c nhng sai st nh xy ra. Do c im ca mch l quang bo nn chng ch hot ng thc s hiu qu vo ban m, hoc l khi nh sang ngoi tri b gim i do thi tit,..

CHNG 2: CC LINH KIN S DNG TRONG MCH .

2.1 DIODE PHT QUANG ( LED N).

Hnh 1: Mt s hnh nh v led n.

- K hiu:

D7 LED

- p dng hiu ng in quang . -Led ch pht sng khi c phn cc thun. -Mi led pht mt bc x nht nh ty theo vt liu ch to v cht pha. GaAs bc sng = 0,77-0,88 Al,Sb = 0,65 GaAsP GaPZn h phch GaAsS = 0,57-0,58 vng GaPN2 = 0.55-0,56 lc - Dng trung bnh qua led thng c chn l: 10 n 20 miliAmpere.

2.2 IN TR.

in tr loi dn

Hnh 2: Mt s hnh nh v in tr. - K hiu:

- H thc: - Hay i(t) = G.v(t)

v(t) = R.i(t)

Trong G =1/R: c gi l in dn . - n v ca in tr l Ohm( c l m) - n v ca in dn l Siemen. 2.3 T IN. a.S lc v t in. T in l mt linh kin in t th ng bao gm hai mt dn in gi l khung, c phn cch bi mt cht cch in, gi l in mi (khng kh, giy, mica, du nhn, nha, cao su, gm, thu tinh...)

Gi tr ca t in l in dung, c o bng n v Farad (k hiu l F). Gi tr F l rt ln nn hay dng cc gi tr nh hn nh micro fara (F), nano Fara (nF) hay picro Fara (pF). b. Phn loi t in thng gp. 1/. Theo tnh cht l ha v ng dng : C cc loi t in : T in phn cc : l loi t in c hai u (-) v (+) r rng, khng th mc ngc u trong mng in DC. Chng thng l t ha hc v t tantalium. T in khng phn cc : L t khng qui nh cc tnh.

T in h (thp) p v cao p : Do in p lm vic m c phn bit ny. T lc (ngun) v t lin lc (lin tng) : T in dng vo mc tiu c th th gi tn theo ng dng. T in tnh v t in ng (iu chnh c) : a s t in c mt tr s in dung "danh nh" nhng cng c cc loi t in cn iu chnh tr s cho ph hp yu cu ca mch in, nh t in trong mch cng hng hay dao ng chng hn. 2/. Theo cu to v dng thc : T in gm (t t) : Gi tn nh th l do chng c lm bng ceramic, bn ngoi bc keo hay nhum mu. Gm in mi c dng l COG, X7R, Z5U v.v...

T gm a lp: L loi t gm c nhiu lp bn cc cch in bng gm. T ny p ng cao tn v in p cao hn loi t gm thng khong 4 --> 5 ln. T giy : L t in c bn cc l cc l nhm hoc thic cch nhau bng lp giy tm du cch in lm dung mi.

T mica mng mng : Cu to vi cc lp in mi l mica nhn to hay nha c cu to mng mng (thin film) nh Mylar, Polycarbonate, Polyester, Polystyrene (n nh nhit 150 ppm / C). T bc - mica : l loi t in mica c bn cc bng bc, kh nng. in dung t vi pF n vi nF, n nhit rt b. T ha hc : L t giy c dung mi ha hc c hiu => to in dung cao v rt cao cho t in. Nu bn ngoi c v nhm bc nha th cn gi l t nhm.

Ngoi ra cn rt nhiu cc loi t khc v d nh :T siu ha,t ha sinh, T tantalium, T vi chnh v t xoay,

T in loi dn

2.4 IC CD4094

S chn

Data input : Ng vo d liu ra ( Data) . Clock input : Ng vo xung clock ( clock ). Strobe input : Ng vo Strobe ( STR ) . Output enable input : Ng vo cho php xut d liu ra ( OE ) . Q1 Q8 : Ng ra song song . Bng hot ng

Hi-z : Trng thi tt. Q7 : Thng tin trong tng ghi dch th 7.

X : Khng quan tm. 0 : Mc thp. 1 : Mc cao. Parallel Output : Ng ra song song. Serial Output : Ng ra ni tip. IC CD4094 l mt thanh ghi dch ni tip 8 tng , c 1 mch cht lu tr mi tng c kt hp vi nhau Strobe d liu t ng vo ni tip n cc ng ra song song m 3 trng thi Q1Q8.Cc ng ra song song c th c ni trc tip n cc Bus.D liu c dch da trn s bin i cnh ln ca xung Clock.D liu trong mi tng ghi dch c chuyn n thanh ghi lu tr khi chn Strobe (STR) mc cao.D liu trong thanh ghi lu tr xut hin ti cc ng ra khi m tn hiu cho php xut (EO) mc cao. Hai ng ra ni tip (QS v QS) c s dng cho vic ghp ni tng cc h IC 4094.D liu c sn QS theo cnh l n ca xung Clock cho php vn hnh tc cao trong h thng ni tng c thi gian ln ca xung clock l ngn .Thng tin ni tip tng t c sn QS theo cnh xung ca Clock v thc hin ni tng ca IC 4094 khi thi gian ln ca xung Clock l di .
S logic .

Gin thi gian

IC CD4094 loi dn

IC CD4094 loi thng

2.5. VI X L PIC16F877A.
2.5.1. Gii thiu v cu trc phn cng PIC16F877A. 2.1 S CHN VI IU KHIN PIC16F877A.

2.2 MT VI THNG S V VI IU KHIN PIC16F877A y l vi iu khin thuc h PIC16Fxxx vi tp lnh gm 35 lnh c di 14 bit. Mi lnh u c thc thi trong mt chu k xung clock. Tc hot ng ti a cho php l 20 MHz vi mt chu k lnh l 200ns. B nh chng trnh 8Kx14 bit, b nh d liu 368x8 byte RAM v b nh d liu EEPROM vi dung lng 256x8 byte. S PORT I/O l 5 vi 33 pin I/O. Cc c tnh ngoi vi bao gmcc khi chc nng sau: Timer0: b m 8 bit vi b chia tn s 8 bit .

 Timer1: b m 16 bit vi b chia tn s, c th thc hin chc nng m da vo xung clock ngoi vi ngay khi vi iu khin hot ng ch sleep. Timer2: b m 8 bit vi b chia tn s, b postcaler. Hai b Capture/so snh/iu ch rng xung. Cc chun giao tip ni tip SSP (Synchronous Serial Port), SPI v I2C. Chun giao tip ni tip USART vi 9 bit a ch. Cng giao tip song song PSP (Parallel Slave Port) vi cc chn iu khin RD, WR, CS bn ngoi. Cc c tnh Analog: 8 knh chuyn i ADC 10 bit. Hai b so snh. Bn cnh l mt vi c tnh khc ca vi iu khin nh: B nh flash vi kh nng ghi xa c 100.000 ln. B nh EEPROM vi kh nng ghi xa c 1.000.000 ln. D liu b nh EEPROM c th lu tr trn 40 nm. Kh nng t np chng trnh vi s iu khin ca phn mm. Np c chng trnh ngay trn mch in ICSP (In Circuit Serial Programming) thng qua 2 chn. Watchdog Timer vi b dao ng trong. Chc nng bo mt m chng trnh. Ch Sleep. C th hot ng vi nhiu dng Oscillator khc nhau. 2.3 S KHI VI IU KHIN PIC16F877A

2.4 T CHC B NH Cu trc b nh ca vi iu khin PIC16F877A bao gm b nh chng trnh (Program memory) v b nh d liu (Data Memory). 2.4.1 B NH CHNG TRNH B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b nh 8K word (1 word = 14 bit) v c phn thnh nhiu trang (t page0 n page 3) . Nh vy b nh chng trnh c kh nng cha c 8*1024 = 8192 lnh (v mt lnh sau khi m ha s c dung lng 1 word (14 bit). m ha c a ch ca 8K word b nh chng trnh, b m chng trnh c dung lng 13 bit (PC<12:0>). Khi vi iu khin c reset, b m chng trnh s ch n a ch 0000h (Reset vector). Khi c ngt xy ra, b m chng trnh s ch n a ch 0004h (Interrupt vector). B nh chng trnh khng bao gm: B nh stack v khng c a ch ha bi b m chng trnh. B nh stack s c cp c th trong phn sau.

2.4.2 B NH D LIU B nh d liu ca PIC l b nh EEPROM c chia ra lm nhiu bank. i vi PIC16F877A b nh d liu c chia ra lm 4 bank. Mi bank c dung lng 128 byte, bao gm cc thanh ghi c chc nng c bit SFG (Special Function Register) nm cc vng a ch thp v cc thanh ghi mc ch chung GPR (General Purpose Register) nm vng a ch cn li trong bank. Cc thanh ghi SFR thng xuyn c s dng (v d nh thanh ghi STATUS) s c t tt c cc bank ca b nh d liu gip thun tin trong qu trnh truy xut v lm gim bt lnh ca chng trnh. S c th ca b nh d liu PIC16F877A nh sau:

2.4.2.1 THANH GHI CHC NNG C BIT SFR

y l cc thanh ghi c s dng bi CPU hoc c dng thit lp v iu khin cc khi chc nng c tch hp bn trong vi iu khin. C th phn thanh ghi SFR lm hai lai: thanh ghi SFR lin quan n cc chc nng bn trong (CPU) v thanh ghi SRF dng thit lp v iu khin cc khi chc nng bn ngoi (v d nh ADC, PWM, ). Phn ny s cp n cc thanh ghi lin quan n cc chc nng bn trong. Cc thanh ghi dng thit lp v iu khin cc khi chc nng s c nhc n khi ta cp n cc khi chc nng . Chi tit v cc thanh ghi SFR s c lit k c th trong bng ph lc 2. Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha kt qu thc hin php ton ca khi ALU, trng thi reset v cc bit chn bank cn truy xut trong b nh d liu. Thanh ghi OPTION_REG (81h, 181h): thanh ghi ny cho php c v ghi, cho php iu khin chc nng pull-up ca cc chn trong PORTB, xc lp cc tham s v xung tc ng, cnh tc ng ca ngt ngoi vi v b m Timer0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho php c v ghi, cha cc bit iu khin v cc bit c hiu khi t imer0 b trn, ngt ngoi vi RB0/INT v ngt interrputon-change ti cc chn ca PORTB.

Thanh ghi PIE1 (8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi chc nng ngoi vi.

Thanh ghi PIR1 (0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE1.

Thanh ghi PIE2 (8Dh): cha cc bit iu khin cc ngt ca cc khi chc nng CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM.

Thanh ghi PIR2 (0Dh): cha cc c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE2.

Thanh ghi PCON (8Eh): cha cc c hiu cho bit trng thi cc ch reset ca vi iu khin.

2.4.2.2 THANH GHI MC CH CHUNG GPR

Cc thanh ghi ny c th c truy xut trc tip hoc gin tip thng qua thanh ghi FSG (File Select Register). y l cc thanh ghi d liu thng thng, ngi s dng c th ty theo mc ch chng trnh m c th dng cc thanh ghi ny cha cc bin s, hng s, kt qu hoc cc tham s phc v cho chng trnh. 2.4.3 STACK Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng nh c bit khng cho php c hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xy ra lm chng trnh b r nhnh, gi tr ca b m chng trnh PC t ng c vi iu khin ct vo trong stack. Khi mt trong cc lnh RETURN, RETLW hat RETFIE c thc thi, gi tr PC s t ng c ly ra t trong stack, vi iu khin s thc hin tip chng trnh theo ng qui trnh nh trc. B nh Stack trong vi iu khin PIC h 16F87xA c kh nng cha c 8 a ch v hot ng theo c ch xoay vng. Ngha l gi tr ct vo b nh Stack ln th 9 s ghi ln gi tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th 10 s ghi ln gi tri6 ct vo Stack ln th 2. Cn ch l khng c c hiu no cho bit trng thi stack, do ta khng bit c khi no stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng c lnh POP hay PUSH, cc thao tc vi b nh stack s hon ton c iu khin bi CPU. 2.5 CC CNG XUT NHP CA PIC16F877A Cng xut nhp (I/O port) chnh l phng tin m vi iu khin dng tng tc vi th gii bn ngoi. S tng tc ny rt a dng v thng qua qu trnh t ng tc , chc nng ca vi iu khin c th hin mt cch r rng. Mt cng xut nhp ca vi iu khin bao gm nhiu chn (I/O pin), t y theo cch b tr v chc nng ca vi iu khin m s lng cng xut nhp v s lng chn trong mi cng c th khc nhau. Bn cnh , do vi iu khin c tch hp sn bn trong cc c tnh giao tip ngoi vi nn bn cnh chc nng l cng xut nhp thng thng, mt s chn xut nhp cn c thm cc chc nng khc th hin s tc ng ca cc c tnh ngoi vi nu trn i vi th gii bn ngoi. Chc nng ca tng chn xut nhp trong mi cng ho n ton c th c xc lp v iu khin c thng qua cc thanh ghi SFR lin quan n chn xut nhp . Vi iu khin PIC16F877A c 5 cng xut nhp, bao gm PORTA, PORTB, PORTC, PORTD v PORTE. Cu trc v chc nng ca tng cng xut nhp s c cp c th trong phn sau. 2.5.1 PORTA PORTA (RPA) bao gm 6 I/O pin. y l cc chn hai chiu (bidirectional pin), ngha l c th xut v nhp c. Chc nng I/O ny c iu khin bi thanh ghi TRISA (a ch 85h). Mun xc lp chc nng ca mt chn trong PORTA l input, ta set bit iu khin tng ng vi chn trong thanh ghi TRISA v ngc li, mun xc lp chc nng ca mt chn trong PORTA l output, ta clear bit iu khin tng ng vi chn trong thanh ghi TRISA. Thao tc ny hon ton tng t i vi cc PORT v cc thanh ghi iu khin tng ng TRIS (i vi PORTA l TRISA, i vi PORTB l TRISB, i vi PORTC l TRISC, i vi PORTD l TRISD vi vi PORTE l TRISE). Bn cnh PORTA cn l ng ra ca b ADC, b so snh, ng vo analog ng vo xung clock ca Timer0 v ng vo ca b giao tip MSSP (Master Synchronous Serial Port). c tnh ny s c trnh by c th trong phn sau. Cu trc bn trong v chc nng c th ca tng chn trong PORTA s c trnh by c th trong Ph lc 1. Cc thanh ghi SFR lin quan n PORTA bao gm: PORTA (a ch 05h) : cha gi tr cc pin trong PORTA.

TRISA (a ch 85h) : iu khin xut nhp. CMCON (a ch 9Ch) : thanh ghi iu khin b so snh. CVRCON (a ch 9Dh) : thanh ghi iu khin b so snh in p. ADCON1 (a ch 9Fh) : thanh ghi iu khin b ADC. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.5.2 PORTB PORTB (RPB) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISB. Bn cnh mt s chn ca PORTB cn c s dng trong qu trnh np chng trnh cho vi iu khin vi cc ch np khc nhau. PORTB cn lin quan n ngt ngoi vi v b Timer0. PORTB cn c tch hp chc nng in tr ko ln c iu khin bi chng trnh. Cu trc bn trong v chc nng c th ca tng chn trong PORTB s c trnh by c th trong Ph lc 1. Cc thanh ghi SFR lin quan n PORTB bao gm: PORTB (a ch 06h,106h) : cha gi tr cc pin trong PORTB TRISB (a ch 86h,186h) : iu khin xut nhp OPTION_REG (a ch 81h,181h) : iu khin ngt ngoi vi v b Timer0. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.5.3 PORTC PORTC (RPC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISC. Bn cnh PORTC cn cha cc chn chc nng ca b so snh, b Timer1, b PWM v cc chun giao tip ni tip I2C, SPI, SSP, USART. Cu trc bn trong v chc nng c th ca tng chn trong PORTC s c trnh by c th trong Ph lc 1. Cc thanh ghi iu khin lin quan n PORTC: PORTC (a ch 07h) : cha gi tr cc pin trong PORTC TRISC (a ch 87h) : iu khin xut nhp. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.5.4 PORTD PORTD (RPD) gm 8 chn I/O, thanh ghi iu khin xut nhp tng ng l TRISD. PORTD cn l cng xut d liu ca chun giao tip PSP (Parallel Slave Port). Cu trc bn trong v chc nng c th ca tng chn trong PORTD s c trnh by c th trong Ph lc 1. Cc thanh ghi lin quan n PORTD bao gm: Thanh ghi PORTD : cha gi tr cc pin trong PORTD. Thanh ghi TRISD : iu khin xut nhp. Thanh ghi TRISE : iu khin xut nhp PORTE v chun giao tip PSP. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.5.5 PORTE PORTE (RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng l TRISE. Cc chn ca PORTE c ng vo analog. Bn cnh PORTE cn l cc chn iu khin ca chun giao tip PSP. Cu trc bn trong v chc nng c th ca tng chn trong PORTE s c trnh by c th trong Ph lc 1. Cc thanh ghi lin quan n PORTE bao gm: PORTE : cha gi tr cc chn trong PORTE. TRISE : iu khin xut nhp v xc lp cc thng s cho chun giao tip PSP. ADCON1 : thanh ghi iu khin khi ADC.

Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.6 TIMER_0 S khi ca Timer0 nh sau:

y l mt trong ba b m hoc b nh thi ca vi iu khin PIC16F877A. Timer0 l b m 8 bit c kt ni vi b chia tn s (prescaler) 8 bit. Cu trc ca Timer0 cho php ta la chn xung clock tc ng v cnh tch cc ca xung clock. Ngt Timer0 s xut hin khi Timer0 b trn. Bit TMR0IE (INTCON<5>) l bit iu khin ca Timer0. TMR0IE=1 cho php ngt Timer0 tc ng, TMR0IF= 0 khng cho php ngt Timer0 tc ng. Mun Timer0 hot ng ch Timer ta clear bit TOSC (OPTION_REG<5>), khi gi tr thanh ghi TMR0 s tng theo tng chu k xung ng h (tn s vo Timer0 bng tn s oscillator). Khi gi tr thanh ghi TMR0 t FFh tr v 00h, ngt Timer0 s xut hin. Thanh ghi TMR0 cho php ghi v xa c gip ta n nh thi im ngt Timer0 xut hi n mt cch linh ng. Mun Timer0 hot ng ch counter ta set bit TOSC (OPTION_REG<5>). Khi xung tc ng ln b m c ly t chn RA4/TOCK1. Bit TOSE (OPTION_REG<4>) cho php la chn cnh tc ng vo bt m. Cnh tc ng s l cnh ln nu TOSE=0 v cnh tc ng s l cnh xung nu TOSE=1. Khi thanh ghi TMR0 b trn, bit TMR0IF (INTCON<2>) s c set. y chnh l c ngt ca Timer0. C ngt ny phi c xa bng chng trnh trc khi b m bt u thc hin li qu trnh m. Ngt Timer0 khng th nh thc vi iu khin t ch sleep. B chia tn s (prescaler) c chia s gia Timer0 v WDT (Watchdog Timer). iu c ngha l nu prescaler c s dng cho Timer0 th WDT s khng c c h tr ca prescaler v ngc li. Prescaler c iu khin bi thanh ghi OPTION_REG. Bit PSA (OPTION_REG<3>) xc nh i tng tc ng ca prescaler. Cc bit PS2:PS0 (OPTION_REG<2:0>) xc nh t s chia tn s ca prescaler. Xem li thanh ghi OPTION_REG xc nh li mt cch chi tit v cc bit iu khin trn. Cc lnh tc ng ln gi tr thanh ghi TMR0 s xa ch hot ng ca prescaler. Khi i tng tc ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa prescaler nhng khng lm thay i i tng tc ng ca prescaler.

Khi i tng tc ng l WDT, lnh CLRWDT s xa prescaler, ng thi prescaler s ngng tc v h tr cho WDT. Cc thanh ghi iu khin lin quan n Timer0 bao gm: TMR0 (a ch 01h, 101h) : cha gi tr m ca Timer0. INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE). OPTION_REG (a ch 81h, 181h): iu khin prescaler. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.7 TIMER_1 Timer1 l b nh thi 16 bit, gi tr ca Timer1 s c lu trong hai thanh ghi (TMR1H:TMR1L). C ngt ca Timer1 l bit TMR1IF (PIR1<0>). Bit iu khin ca Timer1 s l TMR1IE (PIE<0>). Tng t nh Timer0, Timer1 cng c hai ch hot ng: ch nh thi (timer) vi xung kch l xung clock ca oscillator (tn s ca timer bng tn s ca oscillator) v ch m (counter) vi xung kch l xung phn nh cc s kin cn m ly t bn ngoi thng qua chn RC0/T1OSO/T1CKI (cnh tc ng l cnh ln). Vic la chn xung tc ng (tng ng vi vic la chn ch hot ng l timer hay counter) c iu khin bi bit TMR1CS (T1CON<1>). Sau y l s khi ca Timer1:

Ngoi ra Timer1 cn c chc nng reset input bn trong c iu khin bi mt trong hai khi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c set, Timer1 s ly xung clock t hai chn RC1/T1OSI/CCP2 v RC0/T1OSO/T1CKI lm xung m. Timer1 s bt u m sau cnh xung u tin ca xung ng vo. Khi PORTC s b qua s tc ng ca hai bit TRISC<1:0> v PORTC<2:1> c gn gi tr 0. Khi clear bit T1OSCEN Timer1 s ly xung m t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1 c hai ch m l ng b (Synchronous) v bt ng b (Asynchronous). Ch m c quyt nh bi bit iu khin (T1CON<2>). Khi =1 xung m ly t bn ngoi s khng c ng b ha vi xung clock bn trong, Timer1 s tip tc qu trnh m khi vi iu khin ang ch sleep v ngt do Timer1 to ra khi b trn c kh nng nh thc vi iu khin. ch m bt ng b, Timer1 khng th c s dng lm ngun xung clock cho khi CCP (Capture/Compare/Pulse width

modulation). Khi =0 xung m vo Timer1 s c ng b ha vi xung clock bn trong. ch ny Timer1 s khng hot ng khi vi iu khin ang ch sleep. Cc thanh ghi lin quan n Timer1 bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE). PIR1 (a ch 0Ch): cha c ngt Timer1 (TMR1IF). PIE1( a ch 8Ch): cho php ngt Timer1 (TMR1IE). TMR1L (a ch 0Eh): cha gi tr 8 bit thp ca b m Timer1. TMR1H (a ch 0Eh): cha gi tr 8 bit cao ca b m Timer1. T1CON (a ch 10h): xc lp cc thng s cho Timer1. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.8 TIMER_2

Timer2 l b nh thi 8 bit v c h tr bi hai b chia tn s prescaler va postscaler. Thanh ghi cha gi tr m ca Timer2 l TMR2. Bit cho php ngt Timer2 tc ng l TMR2ON (T2CON<2>). C ngt ca Timer2 l bit TMR2IF (PIR1<1>). Xung ng vo (t n s bng tn s oscillator) c a qua b chia tn s prescaler 4 bit (vi cc t s chia tn s l 1:1, 1:4 hoc 1:16 v c iu khin bi cc bit T2CKPS1:T2CKPS0 (T2CON<1:0>)). Timer2 cn c h tr bi thanh ghi PR2. Gi tr m trong thanh ghi TMR2 s tng t 00h n gi tr cha trong thanh ghi PR2, sau c reset v 00h. Kh I reset thanh ghi PR2 c nhn gi tr mc nh FFh. Ng ra ca Timer2 c a qua b chia tn s postscaler vi cc mc chia t 1:1 n 1:16. Postscaler c iu khin bi 4 bit T2OUTPS3:T2OUTPS0. Ng ra ca postscaler ng vai tr quyt nh trong vic iu khin c ngt. Ngoi ra ng ra ca Timer2 cn c kt ni vi khi SSP, do Timer2 cn ng vai tr to ra xung clock ng b cho khi giao tip SSP. Cc thanh ghi lin quan n Timer2 bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php to n b cc ngt (GIE v PEIE). PIR1 (a ch 0Ch): cha c ngt Timer2 (TMR2IF). PIE1 (a ch 8Ch): cha bit iu khin Timer2 (TMR2IE).

TMR2 (a ch 11h): cha gi tr m ca Timer2. T2CON (a ch 12h): xc lp cc thng s cho Timer2. PR2 (a ch 92h): thanh ghi h tr cho Timer2. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. Ta c mt vi nhn xt v Timer0, Timer1 v Timer2 nh sau: Timer0 v Timer2 l b m 8 bit (gi tr m ti a l FFh), trong khi Timer1 l b m 16 bit (gi tr m ti a l FFFFh). Timer0, Timer1 v Timer2 u c hai ch hot ng l timer v counter. Xung clock c t n s bng tn s ca oscillator. Xung tc ng ln Timer0 c h tr bi prescaler v c th c thit lp nhiu ch khc nhau (tn s tc ng, cnh tc ng) trong khi cc thng s ca xung tc ng ln Timer1 l c nh. Timer2 c h tr bi hai b chia tn s prescaler v postcaler c lp, tuy nhin cnh tc ng vn c c nh l cnh ln. Timer1 c quan h vi khi CCP, trong khi Timer2 c kt ni vi khi SSP. Mt vi so snh s gip ta d dng la chn c Timer thch hp cho ng dng.

2.9 ADC ADC (Analog to Digital Converter) l b chuyn i tn hiu gia hai dng tng t v s. PIC16F877A c 8 ng vo analog (RA4:RA0 v RE2:RE0). Hiu in th chun VREF c th c la chn l VDD, VSS hay hiu in th chun c xc lp trn hai chn RA2 v RA3. Kt qu chuyn i t tn tiu tng t sang tn hiu s l 10 bit s tng ng v c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s dng b chuyn i ADC, cc thanh ghi ny c th c s dng nh cc thanh ghi thng thng khc. Khi qu trnh chuyn i hon tt, kt qu s c lu vo hai thanh ghi ADRESH:ADRESL, bit (ADCON0<2>) c xa v 0 v c ngt ADIF c set. Qui trnh chuyn i t tng t sang s bao gm cc bc sau: 1. Thit lp cc thng s cho b chuyn i ADC: Chn ng vo analog, chn in p mu (da trn cc thng s ca thanh ghi ADCON1) Chnh knh chuyn i AD (thanh ghi ADCON0). Chnh xung clock cho knh chuyn i AD (thanh ghi ADCON0). Cho php b chuyn i AD hot ng (thanh ghi ADCON0). 2. Thit lp cc c ngt cho b AD Clear bit ADIF. Set bit ADIE. Set bit PEIE. Set bit GIE. 3. i cho ti khi qu trnh ly mu hon tt. 4. Bt u qu trnh chuyn i (set bit ). 5. i cho ti khi qu trnh chuyn i hon tt bng cch: Kim tra bit . Nu =0, qu trnh chuyn i hon tt. Kim tra c ngt. 6. c kt qu chuyn i v xa c ngt, set bit (nu cn tip tc chuyn i). 7. Tip tc thc hin cc bc 1 & 2 cho qu trnh chuyn i tip theo

Cn ch l c hai cch lu kt qu chuyn i AD, vic la chn cch lu c iu khin bi bit ADFM v c minh ha c th trong hnh sau:

Cc thanh ghi lin quan n b chuyn i ADC bao gm:

INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ngt (cc bit GIE, PEIE). PIR1 (a ch 0Ch): cha c ngt AD (bit ADIF). PIE1 (a ch 8Ch): cha bit iu khin AD (ADIE). ADRESH (a ch 1Eh) v ADRESL (a ch 9Eh): cc thanh ghi cha kt qu chuyn i AD. ADCON0 (a ch 1Fh) v ADCON1 (a ch 9Fh): xc lp cc thng s cho b chuyn i AD. PORTA (a ch 05h) v TRISA (a ch 85h): lin quan n cc ng vo analog PORTA. PORTE (a ch 09h) v TRISE (a ch 89h): lin quan n cc ng vo analog PORTE. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.10 COMPARATOR B so snh bao gm hai b so so snh tn hiu analog v c t PORTA. g vo b so snh l cc chn RA3:RA0, ng ra l hai chn RA4 v RA5. Thanh ghi iu khin b so snh l CMCON. Cc bit CM2:CM0 trong thanh ghi CMCON ng vai tr chn la cc ch hot ng cho b Comparator (hnh 2.10). C ch hot ng ca b Comparator nh sau: Tn hiu analog chn VIN + s c s snh vi in p chun chn VIN- v tn hiu ng ra b so snh s thay i tng ng nh hnh v. Khi in p chn VIN+ ln hn in p chn VIN+ ng ra s mc 1 v ngc li. Da vo hnh v ta thy p ng ti ng ra khng phi l tc thi so vi thay i ti ng vo m cn c mt khong thi gian nht nh ng ra thay i trng thi (ti a l 10us). Cn ch n khong thi gian p ng ny khi s dng b so snh. Cc tnh ca cc b so snh c th thay i da vo cc gi tr t vo cc bit C2INV v C1INV (CMCON<4:5>).

Cc ch hot ng ca b comparator.

Cc bit C2OUT v C1OUT (CMCON<7:6>) ng vai tr ghi nhn s thay i tn hiu analog so vi in p t trc. Cc bit ny cn c x l thch hp bng chng trnh ghi nhn s thay i ca tn hiu ng vo. C ngt ca b so snh l bit CMIF (thanh ghi PIR1). C ngt ny phi c reset v 0. Bit iu khin b so snh l bit CMIE (Tranh ghi PIE). Cc thanh ghi lin quan n b so snh bao gm: CMCON (a ch 9Ch) v CVRCON (a ch 9Dh): xc lp cc thng s cho b so snh. Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php cc ngt (GIE v PEIE). Thanh ghi PIR2 (a ch 0Dh): cha c ngt ca b so snh (CMIF). Thanh ghi PIE2 (a ch 8Dh): cha bit cho php b so snh (CNIE). Thanh ghi PORTA (a ch 05h) v TRISA (a ch 85h): cc thanh ghi iu khin PORTA. Chi tit v cc thanh ghi s c trnh by c th trong ph lc 2. 2.10 B TO IN P SO SNH

B so snh ny ch hot ng khi b Comparator c nh dng hot ng ch 110. Khi cc pin RA0/AN0 v RA1/AN1 (khi CIS = 0) hoc pin RA3/AN3 v RA2/AN2 (khi CIS = 1) s l ng vo analog ca in p cn so snh a vo ng VIN- ca 2 b so snh C1 v C2 (xem chi tit hnh 2.10). Trong khi in p a vo ng VIN+ s c ly t mt b to in p so snh. S khi ca b to in p so snh c trnh by trong hnh v sau:

B to in p so snh ny bao gm mt thang in tr 16 mc ng vai tr l cu phn p chia nh in p VDD thnh nhiu mc khc nhau (16 mc). Mi mc c gi tr in p khc nhau ty thuc vo bit iu khin CVRR (CVRCON<5>). Nu CVRR mc logic 1, in tr 8R s khng c tc dng nh mt thnh phn ca cu phn p (BJT dn mnh v dng in khng i qua in tr 8R), khi 1 mc in p c gi tr VDD/24. Ngc li khi CVRR mc logic 0, dng in s qua in tr 8R v1 mc in p c gi tr VDD/32. Cc mc in p ny c a qua b MUX cho php ta chn c in p a ra pin RA2/AN2/VREF-/CVREF a vo ng VIN+ ca b so snh bng cch a cc gi tr thch hp vo cc bit CVR3:CVR0. B to in p so snh ny c th xem nh mt b chuyn i D/A n gin. Gi tr in p cn so snh ng vo Analog s c so snh vi cc mc in p do b to in p to ra cho ti khi hai in p ny t c gi tr xp x bng nhau. Khi kt qu chuyn i xem nh c cha trong cc bit CVR3:CVR0. Cc thanh ghi lin quan n b to in p so snh ny bao gm: Thanh ghi CVRCON (a ch 9Dh): thanh ghi trc tip iu khin b so snh in p. Thanh ghi CMCON (a ch 9Ch): thanh ghi iu khin b Comparator. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.11 CCP CCP (Capture/Compare/PWM) bao gm cc thao tc trn cc xung m cung cp bi cc b m Timer1 v Timer2. PIC16F877A c tch hp sn hai khi CCP : CCP1 v

CCP2.Mi CCP c mt thanh ghi 16 bit (CCPR1H:CCPR1L v CCPR2H:CCPR2L), pin iu khin dng cho khi CCPx l RC2/CCP1 v RC1/T1OSI/CCP2. Cc chc nng ca CCP bao gm: Capture. So snh (Compare). iu ch rng xung PWM (Pulse Width Modulation). C CCP1 v CCP2 v nguyn tc hot ng u ging nhau v chc nng ca tng khi l kh c lp. Tuy nhin trong mt s trng hp ngoi l CCP1 v CCP2 c kh nng phi hp vi nhau to ra cc hin tng c bit (Special event trigger) hoc cc tc ng ln Timer1 v Timer2. Cc trng hp ny c lit k trong bng sau:

Khi hot ng ch Capture th khi c mt hin tng xy ra ti pin RC2/CCP1 (hoc RC1/T1OSI/CCP2), gi tr ca thanh ghi TMR1 s c a vo thanh ghi CCPR1 (CCPR2). Cc hin tng c nh ngha bi cc bit CCPxM3:CCPxM0 (CCPxCON<3:0>) v c th l mt trong cc hin tng sau: Mi khi c cnh xung ti cc pin CCP. Mi khi c cnh ln. Mi cnh ln th 4. Mi cnh ln th 16. S khi CCP (Capture mode).

Sau khi gi tr ca thanh ghi TMR1 c a vo thanh ghi CCPRx, c ngt CCPIF c set v phi c xa bng chng trnh. Nu hin tng tip theo xy ra m gi tr trong thanh ghi CCPRx cha c x l, gi tr tip theo nhn c s t ng c ghi ln gi tr c. Mt s im cn ch khi s dng CCP nh sau: Cc pin dng cho khi CCP phi c n nh l input (set cc bit tng ng trong thanh ghi TRISC). Khi n nh cc pin dng cho khi CCP l output, vic a gi tr vo PORTC cng c th gy ra cc hin tng tc ng ln khi CCP do trng thi ca pin thay i. Timer1 phi c hot ng ch Timer hoc ch m ng b. Trnh s dng ngt CCP bng cch clear bit CCPxIE (thanh ghi PIE1), c ngt CCPIF nn c xa bng phn mm mi khi c set tip tc nhn nh c trng thi hot ng ca CCP. CCP cn c tch hp b chia tn s prescaler c iu khin bi cc bit CCPxM3:CCPxM0. Vic thay i i tng tc ng ca prescaler c th to ra hot ng ngt. Prescaler c xa khi CCP khng hot ng hoc khi reset. Xem cc thanh ghi iu khin khi CCP (ph lc 2 bit thm chi tit). Khi hot ng ch Compare, gi tr trong thanh ghi CCPRx s thng xuyn c so snh vi gi tr trong thanh ghi TMR1. Khi hai thanh ghi cha gi tr bng nhau, cc pin ca CCP c thay i trng thi (c a ln mc cao, a xung mc thp hoc gi nguyn trng thi), ng thi c ngt CCPIF cng s c set. S thay i trng thi ca pin c th c iu khin bi cc bit CCPxM3:CCPxM0 (CCPxCON <3:0>).

Tng t nh ch Capture, Timer1 phi c n nh ch hot ng l timer hoc m ng b. Ngoi ra, khi ch Compare, CCP c kh nng to ra hin tng c bit (Special Event trigger) lm reset gi tr thanh ghi TMR1 v khi ng b chuyn i ADC. iu ny cho php ta iu khin gi tr thanh ghi TMR1 mt cch linh ng hn. Khi hot ng ch PWM (Pulse Width Modulation _ khi iu ch rng xung), tn hiu sau khi iu ch s c a ra cc pin ca khi CCP (cn n nh cc pin ny l output). s dng chc nng iu ch ny trc tin ta cn tin hnh cc bc ci t sau: 1. Thit lp thi gian ca 1 chu k ca xung iu ch cho PWM (period) bng cch a gi tr thch hp vo thanh ghi PR2. 2. Thit lp rng xung cn iu ch (duty cycle) bng cch a gi tr vo thanh ghi CCPRxL v cc bit CCP1CON<5:4>. 3. iu khin cc pin ca CCP l output bng cch clear cc bit tng ng trong thanh ghi TRISC.

4. Thit lp gi tr b chia tn s prescaler ca Timer2 v cho php Timer2 hot ng bng cch a gi tr thch hp vo thanh ghi T2CON. 5. Cho php CCP hot ng ch PWM. Hnh 2.15 S khi CCP (PWM mode). Hnh 2.16 Cc tham s ca PWM Trong gi tr 1 chu k (period) ca xung iu ch c tnh bng cng thc: B chia tn s prescaler ca Timer2 ch c th nhn cc gi tr 1,4 hoc 16 (xem li Timer2 bit thm chi tit). Khi gi tr thanh ghi PR2 bng vi gi tr thanh ghi TMR2 th qu trnh sau xy ra: Thanh ghi TMR2 t ng c xa. Pin ca khi CCP c set. Gi tr thanh ghi CCPR1L (cha gi tr n nh rng xung iu ch duty cycle) c a vo thanh ghi CCPRxH. rng ca xung iu ch (duty cycle) c tnh theo cng thc: PWM period = [(PR2)+1]*4*TOSC*(gi tr b chia tn s ca TMR2) PWM duty cycle = (CCPRxL:CCPxCON<5:4>)*TOSC*(gi tr b chia tn s TMR2)Nh vy 2 bit CCPxCON<5:4> s cha 2 bit LSB. Thanh ghi CCPRxL cha byte cao ca gi tr quyt nh rng xung. Thanh ghi CCPRxH ng vai tr l buffer cho khi PWM. Khi gi tr trong thanh ghi CCPRxH bng vi gi tr trong thanh ghi TMR2 v hai bit CCPxCON<5:4> bng vi gi tr 2 bit ca b chia tn s prescaler, pin ca khi CCP li c a v mc thp, nh vy ta c c hnh nh ca xung iu ch ti ng ra ca khi PWM nh hnh 2.14. Mt s im cn ch khi s dng khi PWM: Timer2 c hai b chia tn s prescaler v postscaler. Tuy nhin b postscaler khng c s dng trong qu trnh iu ch rng xung ca khi PWM. Nu thi gian duty cycle di hn thi gian chu k xung period th xung ng ra tip tc c gi mc cao sau khi gi tr PR2 bng vi gi tr TMR2.

2.12 GIAO TIP NI TIP 1.12.1 USART USART (Universal Synchronous Asynchronous Receiver Transmitter) l mt trong hai chun giao tip ni tip.USART cn c gi l giao din giao tip ni tip ni tip SCI (Serial Communication Interface). C th s dng giao din ny cho cc giao tip vi cc thit b ngai vi, vi cc vi iu khin khc hay vi my tnh. Cc dng ca giao din USART ngai vi bao gm: Bt ng b (Asynchronous). ng b_ Master mode. ng b_ Slave mode. Hai pin dng cho giao din ny l RC6/TX/CK v RC7/RX/DT, trong RC6/TX/CK dng truyn xung clock (baud rate) v RC7/RX/DT dng truyn data. Trong trng hp ny ta phi set bit TRISC<7:6> v SPEN (RCSTA<7>) c0 cho php giao din USART. PIC16F877A c tch hp sn b to tc baud BRG (Baud Rate Genetator) 8 bit dng cho giao din USART. BRG thc cht l mt b m c th c s dng cho c hai dng ng b v bt ng b v c iu khin bi thanh ghi PSBRG. dng bt ng b, BRG cn c iu khin bi bit BRGH ( TXSTA<2>). dng ng b tc ng ca bit BRGH c b qua. Tc baud do BRG to ra c tnh theo cng thc sau:

Trong X l gi tr ca thanh ghi RSBRG ( X l s nguyn v 0<X<255). Cc thanh ghi lin quan n BRG bao gm: TXSTA (a ch 98h): chn ch ng b hay bt ng b ( bit SYNC) v chn mc tc baud (bit BRGH). RCSTA (a ch 18h): cho php hot ng cng ni tip (bit SPEN). RSBRG (a ch 99h): quyt nh tc baud. Chi tit v cc thanh ghi s c trnh bt c th trong ph lc 2. 2.12.1.1 USART BT NG B ch truyn ny USART hot ng theo chun NRZ (None-Return-to-Zero), ngha l cc bit truyn i s bao gm 1 bit Start, 8 hay 9 bit d liu (thng thng l 8 bit) v 1 bit Stop. Bit LSB s c truyn i trc. Cc khi truyn v nhn data c lp vi nhau s dng chung tn s tng ng vi tc baud cho qu tr nh dch d liu (tc baud gp 16 hay 64 ln tc dch d liu ty theo gi tr ca bit BRGH), v m bo tnh hiu qu ca d liu th hai khi truyn v nhn phi dng chung mt nh dng d liu. 2.12.1.1.1 TRUYN D LIU QUA CHUN GIAO TIP USART BT NG B Thnh phn quan trng nht ca khi truyn d liu l thanh ghi dch d liu TSR (Transmit Shift Register). Thanh ghi TSR s ly d liu t thanh ghi m dng cho qu trnh truyn d liu TXREG. D liu cn truyn phi c a trc vo thanh ghi TXREG. Ngay sau khi bit Stop ca d liu cn truyn trc c truyn xong, d liu t thanh ghi TXREG s c a vo thanh ghi TSR, thanh ghi TXREG b rng, ngt xy ra v c hiu TXIF (PIR1<4>) c set. Ngt ny c iu khin bi bit TXIE (PIE1<4>). C hiu TXIF vn c set bt chp trng thi ca bit TXIE hay tc ng ca chng trnh (khng th xa TXIF bng chng trnh) m ch reset v 0 khi c d liu mi c a vo thanhh ghi TXREG.

Trong khi c hiu TXIF ng vai tr ch th trng thi thanh ghi TXREG th c hiu TRMT (TXSTA<1>) c nhim v th hin trng thi thanh ghi TSR. Khi thanh ghi TSR rng, bit TRMT s c set. Bit ny ch c v khng c ngt no c gn vi trng thi ca n. Mt im cn ch na l thanh ghi TSR khng c trong b nh d liu v ch c iu khin bi CPU. Khi truyn d liu c cho php hot ng khi bit TXEN (TXSTA<5>) c set. Qu trnh truyn d liu ch thc s bt u khi c d liu trong thanh ghi TXREG v xung truyn baud c to ra. Khi khi truyn d liu c khi ng ln u tin, thanh ghi TSR rng. Ti thi im , d liu a vo thanh ghi TXREG ngay lp tc c load vo thanh ghi TSR v thanh ghi TXREG b rng. Lc ny ta c th hnh thnh mt chui d liu lin tc cho qu trnh truyn d liu. Trong qu trnh truyn d liu nu bit TXEN b reset v 0, qu trnh truyn kt thc, khi truyn d liu c reset v pin RC6/TX/CK chuyn n trng thi high-impedance. Trong trng hp d liu cn truyn l 9 bit, bit TX9 (TXSTA<6>) c set v bit d liu th 9 s c lu trong bit TX9D (TXSTA<0>). Nn ghi bit d liu th 9 vo trc, v khi ghi 8 bit d liu vo thanh ghi TXREG trc c th xy ra trng hp ni dung thanh ghi TXREG s c load vo thanh ghi TSG trc, nh vy d liu truyn i s b sai khc so vi yu cu. Tm li, truyn d liu theo giao din USART bt ng b, ta cn thc hin tun t cc bc sau: 1. To xung truyn baud bng cch a cc gi tr cn thit vo thanh ghi RSBRG v bit iu khin mc tc baud BRGH. 2. Cho php cng giao din ni tip ni tip bt ng b bng cch clear bit SYNC v set bit PSEN. 3. Set bit TXIE nu cn s dng ngt truyn. 4. Set bit TX9 nu nh dng d liu cn truyn l 9 bit. 5. Set bit TXEN cho php truyn d liu (lc ny bit TXIF cng s c set). 6. Nu nh dng d liu l 9 bit, a bit d liu th 9 vo bit TX9D. 7. a 8 bit d liu cn truyn vo thanh ghi TXREG. 8. Nu s dng ngt truyn, cn kim tra li cc bit GIE v PEIE (thanh ghi INTCON). Cc thanh ghi lin quan n qu trnh truyn d liu bng giao din USART bt ng b: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php tt c cc ngt.

 Thanh ghi PIR1 (a ch 0Ch): cha c hiu TXIF. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt truyn TXIE. Thanh ghi RCSTA (a ch 18h): cha bit cho php cng truyn d liu (hai pin RC6/TX/CK v RC7/RX/DT). Thanh ghi TXREG (a ch 19h): thanh ghi cha d liu cn truyn. Thanh ghi TXSTA (a ch 98h): xc lp cc thng s cho giao din. Thanh ghi SPBRG (a ch 99h): quyt nh tc baud. Chi tit v cc thanh ghi s c trnh by c th ph lc 2.

2.12.1.1.2 NHN D LIU QUA CHUN GIAO TIP USART BT NG B D liu c a vo t chn RC7/RX/DT s kch hot khi phc hi d liu. Khi phc hi d liu thc cht l mt b dch d liu ctc cao va c tn s hot ng gp 16 ln hoc 64 ln tn s baud. Trong khi tc dch ca thanh thanh ghi nhn d liu s bng vi tn s baud hoc tn s ca oscillator.

Bit iu khin cho php khi nhn d liu l bit RCEN (RCSTA<4>). Thnh phn quan trng nht ca khi nhn d liu l thsnh ghi nhn d liu RSR (Receive Shift Register). Sau khi nhn din bit Stop ca d liu truyn ti, d liu nhn c trong thanh ghi RSR s c a vo thanh ghi RCGER, sau c hiu RCIF (PIR1<5>) s c set v ngt nhn c kch hot. Ngt ny c iu khin bi bit RCIE (PIE1<5>). Bit c hiu RCIF l bit ch c v khng th c tc ng bi chng trnh. RCIF ch reset v 0 khi d liu nhn vo thanh ghi RCREG c c v khi thanh ghi RCREG rng. Thanh ghi RCREG l thanh ghi c b m kp (double-buffered register) v hot ng theo c ch FIFO (First In First Out) cho php nhn 2 byte v byte th 3 tip tc c a vo thanh ghi RSR. Nu sau khi nhn c bit Stop ca byte d liu th 3 m thanh ghi RCREG vn cn y, c hiu bo trn d liu (Overrun Error bit) OERR(RCSTA<1>) s c set, d liu trong thanh ghi RSR s b mt i v qu trnh a d liu t thanh ghi RSR vo thanh ghi RCREG s b gin on. Trong trng hp ny cn ly ht d liu thanh ghi RSREG vo trc khi tip tc nhn byte d liu tip theo. Bit OERR phi c xa bng phn mm v thc hin bng cch clear bit RCEN ri set li. Bit FERR (RCSTA<2>) s c set khi pht hin bit Stop da d liu c nhn vo. Bit d liu th 9 s c a vo bit RX9D (RCSTA<0>). Khi c d liu t thanh ghi RCREG, hai bit FERR v RX9D s nhn cc gi tr mi. Do cn c d liu t thanh ghi RCSTA trc khi c d liu t thanh ghi RCREG trnh b mt d liu. Tm li, khi s dng giao din nhn d liu USART bt ng b cn tin hnh tun t cc bc sau: 1. Thit lp tc baud (a gi tr thch hp vo thanh ghi SPBRG v bit BRGH. 2. Cho php cng giao tip USART bt ng b (clear bit SYNC v set bit SPEN). 3. Nu cn s dng ngt nhn d liu, set bit RCIE.

4. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. 5. Cho php nhn d liu bng cch set bit CREN. 6. Sau khi d liu c nhn, bit RCIF s c set v ngt c kch hot (nu bit RCIE c set). 7. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu tr nh nhn d liu c b li khng. 8. c 8 bit d liu t thanh ghi RCREG. 9. Nu qu trnh truyn nhn c li xy ra, xa li bng cch xa bit CREN. 10. Nu s dng ngt nhn cn set bit GIE v PEIE (thanh ghi INTCON). Cc thanh ghi lin quan n qu trnh nhn d liu bng giao din USART bt ng b: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php to n b cc ngt (bit GIER v PEIE). Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt RCIE. Thanh ghi RCSTA (a ch 18h): xc nh cc trang thi trong qu trnh nhn d liu. Thanh ghi RCREG (a ch 1Ah): cha d liu nhn c. Thanh ghi TXSTA (a ch 98h): cha cc bit iu khin SYNC v BRGH. Thanh ghi SPBRG (a ch 99h): iu khin tc baud. 2.12.1.1.2 USART NG B Giao din USART ng b c kch hot bng cch set bit SYNC. Cng giao tip ni tip vn l hai chn RC7/RX/DT, RC6/TX/CK v c cho php bng cch set bit SPEN. USART cho php hai ch truyn nhn d liu l Master mode v Slave mode. Master mode c kch hot bng cch set bit CSRC (TXSTA<7>), Slave mode c kch hot bng cch clear bit CSRC. im khc bit duy nht gia hai ch ny l Master mode s ly xung clock ng b t b tao xung baud BRG cn Slave mode ly xung clock ng b t bn ngoi qua chn RC6/TX/CK. iu ny cho php Slave mode hot ng ngay c khi vi iu khin ang ch sleep. 2.12.1.2.1 TRUYN D LIU QUA CHUN GIAO TIP USART NG B MASTER MODE Tng t nh giao din USART bt ng b, thnh phn quan trng nht ca hi truyn d liu l thanh ghi dch TSR (Transmit Shift Register). Thanh ghi ny ch c iu khin bi CPU. D liu a vo thanh ghi TSR c cha trong thanh ghi TXREG. C hiu ca khi truyn d liu l bit TXIF (ch th trang thi thanh ghi TXREG), c hiu ny c gn vi mt ngt v bit iu khin ngt ny l TXIE. C hiu ch th trng thi thanh ghi TSR l bit TRMT. Bit TXEN cho php hay khng cho php truyn d liu. Cc bc cn tin hnh khi truyn d liu qua giao din USART ng b Master mode: 1. To xung truyn baud bng cch a cc gi tr cn thit vo thanh ghi RSBRG v bit iu khin mc tc baud BRGH. 2. Cho php cng giao din ni tip ni tip ng b bng cch set bit SYNC, PSEN v CSRC. 3. Set bit TXIE nu cn s dng ngt truyn. 4. Set bit TX9 nu nh dng d liu cn truyn l 9 bit. 5. Set bit TXEN cho php truyn d liu. 6. Nu nh dng d liu l 9 bit, a bit d liu th 9 vo bit TX9D. 7. a 8 bit d liu cn truyn vo thanh ghi TXREG. 8. Nu s dng ngt truyn, cn kim tra li cc bit GIE v PEIE (thanh ghi INTCON). Cc thanh ghi lin quan n qu trnh truyn d liu bng giao din USART ng b Master

mode: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php tt c cc ngt. Thanh ghi PIR1 (a ch 0Ch): cha c hiu TXIF. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt truyn TXIE. Thanh ghi RCSTA (a ch 18h): cha bit cho php cng truyn d liu (hai pin RC6/TX/CK v RC7/RX/DT). Thanh ghi TXREG (a ch 19h): thanh ghi cha d liu cn truyn. Thanh ghi TXSTA (a ch 98h): xc lp cc thng s cho giao din. Thanh ghi SPBRG (a ch 99h): quyt nh tc baud. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.12.1.2.2 NHN D LIU QUA CHUN GIAO TIP USART NG B MASTER MODE Cu trc khi truyn d liu l khng i so vi giao din bt ng b, k c cc c hiu, ngt nhn v cc thao tc trn cc thnh phn . im khc bit duy nht l giao din ny cho php hai ch nhn s liu, l ch nhn 1 word d liu (set bit SCEN) hay nhn mt chui d liu (set bit CREN) cho ti khi ta clear bit CREN. Nu c hai bit u c set, bit iu khin CREN s c u tin. Cc bc cn tin hnh khi nhn d liu bng giao din USART ng b Master mode: 1. Thit lp tc baud (a gi tr thch hp vo thanh ghi SPBRG v bit BRGH). 2. Cho php cng giao tip USART bt ng b (set bit SYNC, SPEN v CSRC). 3. Clear bit CREN v SREN. 4. Nu cn s dng ngt nhn d liu, set bit RCIE. 5. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. 6. Nu ch nhn 1 word d liu, set bit SREN, nu nhn 1 chui word d liu, set bit CREN. 7. Sau khi d liu c nhn, bit RCIF s c set v ngt c kch hot (nu bit RCIE c set). 8. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu tr nh nhn d liu c b li khng. 9. c 8 bit d liu t thanh ghi RCREG. 10. Nu qu trnh truyn nhn c li xy ra, xa li bng cch xa bit CREN. 11. Nu s dng ngt nhn cn set bit GIE v PEIE (thanh ghi INTCON). Cc thanh ghi lin quan n qu trnh nhn d liu bng giao din USART ng b Master mode: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php ton b cc ngt (bit GIER v PEIE). Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt RCIE. Thanh ghi RCSTA (a ch 18h): xc nh cc trang thi trong qu trnh nhn d liu. Thanh ghi RCREG (a ch 1Ah): cha d liu nhn c. Thanh ghi TXSTA (a ch 98h): cha cc bit iu khin SYNC v BRGH. Thanh ghi SPBRG (a ch 99h): iu khin tc baud. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.12.1.2.3 TRUYN D LIU QUA CHUN GIAO TIP USART NG B SLAVE MODE Qu trnh ny khng c s khc bit so vi Master mode khi vi iu khin hot ng ch bnh thng. Tuy nhin khi vi iu khin ang trng thi sleep, s khc bit c th

hin r rng. Nu c hai word d liu c a vo thanh ghi TXREG trc khi lnh sleep c thc thi th qu trnh sau s xy ra: 1. Word d liu u tin s ngay lp tc c a vo thanh ghi TSR truyn i. 2. Word d liu th hai vn nm trong thanh ghi TXREG. 3. C hiu TXIF s khng c set. 4. Sau khi word d liu u tin dch ra khi thanh ghi TSR, thanh ghi TXREG tip tc truyn word th hai vo thanh ghi TSR v c hiu TXIF c set. 5. Nu ngt truyn c cho php hot ng, ngt ny s nh thc vi iu khin v nu ton b cc ngt c cho php hot ng, b m chng trnh s ch ti a ch cha chng trnh ngt (0004h). Cc bc cn tin hnh khi truyn d liu bng giao din USART ng b Slave mode: 1. Set bit SYNC, SPEN v clear bit CSRC. 2. Clear bit CREN v SREN. 3. Nu cn s dng ngt, set bit TXIE. 4. Nu nh dng d liu l 9 bit, set bit TX9. 5. Set bit TXEN. 6. a bit d liu th 9 vo bit TX9D trc (nu nh dng d liu l 9 bit). 7. a 8 bit d liu vo thanh ghi TXREG. 8. Nu ngt truyn c s dng, set bit GIE v PEIE (thanh ghi INTCON). Cc thanh ghi lin quan n qu tr nh truyn d liu bng giao din USART ng b Slave mode: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php tt c cc ngt. Thanh ghi PIR1 (a ch 0Ch): cha c hiu TXIF. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt truyn TXIE. Thanh ghi RCSTA (a ch 18h): cha bit cho php cng truyn d liu (hai pin RC6/TX/CK v RC7/RX/DT). Thanh ghi TXREG (a ch 19h): thanh ghi cha d liu cn truyn. Thanh ghi TXSTA (a ch 98h): xc lp cc thng s cho giao din. Thanh ghi SPBRG (a ch 99h): quyt nh tc baud. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.12.1.2.4 NHN D LIU QUA CHUN GIAO TIP USART NG B SLAVEMODE S khc bit ca Slave mode so vi Master mode ch th hin r rng khi vi iu khin hot ng ch sleep. Ngo i ra ch Slave mode khng quan tm ti bit SREN. Khi bit CREN (cho php nhn chui d liu) c set trc khi lnh sleep c thc thi, 1 word d liu vn c tip tc nhn, sau khi nhn xong bit thanh ghi RSR s chuyn d liu vo thanh ghi RCREG v bit RCIF c set. Nu bit RCIE (cho php ngt nhn) c set trc , ngt s c thc thi v vi iu khin c nh thc, b m chng trnh s ch n a ch 0004h v chng trnh ngt s c thc thi. Cc bc cn tin hnh khi nhn d liu bng giao din USART ng b Slave mode: 1. Cho php cng giao tip USART bt ng b (set bit SYNC, SPEN clear bit CSRC). 2. Nu cn s dng ngt nhn d liu, set bit RCIE. 3. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. 4. Set bit CREN cho php qu trnh nhn d liu bt u. 5. Sau khi d liu c nhn, bit RCIF s c set v ngt c kch hot (nu bit RCIE c set).

6. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu tr nh nhn d liu c b li khng. 7. c 8 bit d liu t thanh ghi RCREG. 8. Nu qu trnh truyn nhn c li xy ra, xa li bng cch xa bit CREN. 9. Nu s dng ngt nhn cn set bit GIE v PEIE (thanh ghi INTCON). Cc thanh ghi lin quan n qu trnh nhn d liu bng giao din USART ng b Slave mode: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php to n b cc ngt (bit GIER v PEIE). Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt RCIE. Thanh ghi RCSTA (a ch 18h): xc nh cc trang thi trong qu trnh nhn d liu. Thanh ghi RCREG (a ch 1Ah): cha d liu nhn c. Thanh ghi TXSTA (a ch 98h): cha cc bit iu khin SYNC v BRGH. Thanh ghi SPBRG (a ch 99h): iu khin tc baud. Chi tit v cc thanh ghi s c trnh by c th ph lc 2.

2.12.2 MSSP MSSP ( Master Synchronous Serial Port) l giao din ng b ni tip dng giao tip vi cc thit b ngoi vi (EEPROM, ghi dch, chuyn i ADC,) hay cc vi iu khin khc. MSSP c th hot ng di hai dng giao tip: SPI (Serial Pheripheral Interface). I2C (Inter-Intergrated Circuit). Cc thanh ghi iu khin giao chun giao tip ny bao gm thanh ghi trng thi SSPSTAT v hai thanh ghi iu khin SSPSON v SSPSON2. Ty theo chun giao tip c s dng (SPI hay I2C) m chc nng cc thanh ghi ny c th hin khc nhau. 2.12.2.1 SPI Chun giao tip SPI cho php truyn nhn ng b. Ta cn s dng 4 pin cho chun giao tip ny: RC5/SDO: ng ra d liu dng ni tip (Serial Data output). RC4/SDI/SDA: ng vo d liu dng ni tip (Serial Data Input). RC3/SCK/SCL: xung ng b ni tip (Serial Clock). RA5/AN4/SS/C2OUT: chn i tng giao tip (Serial Select) khi giao tip ch Slave mode. Cc thanh ghi lin quan n MSSP khi hot ng chun giao tip SPI bao gm: Thanh ghi iu khin SSPCON, thanh ghi ny cho php c v ghi. Thanh ghi trng thi SSPSTAT, thanh ghi ny ch cho php c v ghi 2 bit trn, 6 bit cn li ch cho php c. Thanh ghi ng vai tr l buffer truyn nhn SSPBUF, d liu truyn i hoc nhn c s c a vo tranh ghi ny. SSPBUF khng c cu trc m hai lp (doubled- buffer), do d liu ghi vo thanh ghi SSPBUF s lp tc c ghi vo thanh ghi SSPSR. Thanh ghi dch d liu SSPSR dng dch d liu vo hoc ra. Khi 1 byte d liu c nhn hon chnh, d liu s t thanh ghi SSPSR chuyn qua thanh ghi SSPBUF v c hiu c set, ng thi ngt s xy ra. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. Khi s dng chun giao tip SPI trc tin ta cn thit lp cc ch cho giao din bng cch a cc gi tr thch hp vo hai thanh ghi SSPCON v SSPSTAT. Cc thng s cn thit lp bao gm: Master mode hay Slave mode. i vi Master mode, xung clock ng b s i ra t chn RC3/SCK/SCL. i vi Slave mode, xung clock ng b s c nhn t bn ngoi qua chn RC3/SCK/SCL. Cc ch ca Slave mode. Mc logic ca xung clock khi trang thi tm ngng qu trnh truyn nhn (Idle). Cnh tc ng ca xung clock ng b (cnh ln hay cnh xung). Tc xung clock (khi hot ng Master mode). Thi im xc nh mc logic ca d liu ( gia hay cui thi gian 1 bit d liu c a vo).

Master mode, Slave mode v cc ch ca Slave mode c iu khin bi cc bit SSPM3:SSPM0 (SSPCON<3:0>).( Xem chi tit ph lc 2.) MSSP bao gm mt thanh ghi dch d liu SSPSR v thanh ghi m d liu SSPBUF. Hai thanh ghi ny to thnh b m d liu kp (doubled-buffer). D liu s c dch vo hoc ra qua thanh ghi SSPSR, bit MSB c dch trc. y l mt trong nhng im khc bit gi hai giao din MSSP v USART (USART dch bit LSB trc). Trong qu trnh nhn d liu, khi d liu a vo t chn RC4/SDI/SDA trong thanh ghi SSPSR sn sng ( nhn 8 bit), d liu s c a vo thanh ghi SSPBUF, bit ch th trng thi b m BF (SSPSTAT<0>) s c set bo hiu b m y, ng thi c ngt SSPIF (PIR1<3>) cng c set. Bit BF s t ng reset v 0 khi d liu trong thanh ghi SSPBUF c c vo. B m kp cho php c tip byte tip theo trc khi byte d liu trc c c vo. Tuy nhin ta nn c trc d liu t thanh ghi SSPBUF trc khi nhn byte d liu tip theo. Qu trnh truyn d liu cng hon ton tng t nhng ngc li. D liu cn truyn s c a vo thanh ghi SSPBUF ng thi a vo thanh ghi SSPSR, khi c hiu BF c set. D liu c dch t thanh ghi SSPSR v a ra ngoi qua chn RC5/SDO. Ngt s xy ra khi qu trnh dch d liu hon tt. Tuy nhin d liu trc khi c a ra ngoi phi c cho php bi tn hiu t chn . Chn ny ng vai tr chn i tng giao tip khi SPI ch Slave mode. Khi qu trnh truyn nhn d liu ang din ra, ta khng c php ghi d liu vo thanh ghi SSPBUF. Thao tc ghi d liu ny s set bit WCON (SSPCON<7>). Mt iu cn ch na l thanh ghi SSPSR khng cho php truy xut trc tip m phi thng qua thanh ghi SSPBUF. Cng giao tip ca giao din SPI c iu khin bi bit SSPEN (SSPSON<5>). Bn cnh cn iu khin chiu xut nhp ca PORTC thng qua thanh ghi TRISC sao cho ph hp vi chiu ca giao din SPI. C th nh sau: RC4/SDI/SDA s t ng c iu khin bi khi giao itp SPI. RS5/SDO l ng ra d liu, do cn clear bit TRISC<5>. Khi SPI dng Master mode, cn clear bit TRISC<3> cho php a xung clock ng b ra chn RC3/SCK/SCL. Khi SPI dng Slave mode, cn set bit TRISC<3> cho php nhn xung clock ng b t bn ngoi qua chn RC3/SCK/SCL. Set bit TRISC<4> cho php chn nhn tn hiu iu khin truy xut d liu khi SPI ch Slave mode. S kt ni ca chun giao tip SPI nh sau:

Theo s kt ni ny, khi Master s bt u qu trnh truyn nhn d liu bng cch gi tn hiu xung ng b SCK. D liu s dch t c hai thanh ghi SSPSR a ra ngoi nu c mt cnh ca xung ng b tc ng v ngng dch khi c tc ng ca cnh cn li. C hai khi Master v Slave nn c n nh chung cc qui tc tc ng ca xung clock ng b d liu c th dch chuyn ng thi. 2.12.2.1.1 SPI MASTER MODE. ch Master mode, vi iu khin c quyn n nh thi im trao i d liu (v i tng trao i d liu nu cn) v n iu khin xung clock ng b. D liu s c truyn nhn ngay thi im d liu c a vo thanh ghi SSPBUF. Nu ch cn nhn d liu, ta c th n nh chn SDO l ng vo (set bit TRISC<5>). D liu s c dch vo thanh ghi SSPSR theo mt tc c nh sn cho xung clock ng b. Sau khi nhn c mt byte d liu hon chnh, byte d liu s c a do thanh ghi SSPBUF, bit BF c set v ngt xy ra. Khi lnh SLEEP c thc thi trong qu trnh truyn nhn, trng thi ca qu trnh s c gi nguyn v tip tc sau khi vi iu khin c nh thc. Gin xung ca Master mode v cc tc ng ca cc bit iu khin c trnh by trong hnh v sau:

 ch ny SPI s truyn v nhn d liu khi c xung ng b xut hin chn SCK. Khi truyn nhn xong bit d liu cui cng, c ngt SSPIF s c set. Slave mode hot ng ngay c khi vi iu khin ang ch sleep, v ngt truyn nhn cho php nh thc vi iu khin. Khi ch cn nhn d liu, ta c th n nh RC5/SDO l ng vo (set bit TRISC<5>). Slave mode cho php s tc ng ca chn iu khin (SSPCON<3:0> = 0100). Khi chn mc thp, chn RC5/SDO c cho php xut d liu v khi mc cao, d liu ra chn RC5/SDO b kha, ng thi SPI c reset (b m bit d liu c gn gi tr 0).

Cc thanh ghi lin quan n chun giao tip SPI bao gm: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha bit cho php to n b cc ngt (GIE v PEIE). Thanh ghi PIR1 (a ch 0Ch): cha ngt SSPIE. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt SSPIE. Thanh ghi TRISC (a ch 87h): iu khin xut nhp PORTC. Thanh ghi SSPBUF (a ch 13h): thanh ghi m d liu. Thanh ghi SSPCON (a ch 14h): iu khin chun giao tip SPI. Thanh ghi SSPSTAT (a ch 94h): cha cc bit ch th trng thi chun giao tip SPI. Thanh ghi TRISA (a ch 85h):iu khin xut nhp chn . Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.12.2.2 I2C y l mt dng khc ca MSSP. Chun giao tip I2C cng c hai ch Master, Slave v cng c kt ni vi ngt. I2C s s dng 2 pin truyn nhn d liu: `RC3/SCK/SCL: chn truyn dn xung clock. RC4/SDI/SDA: chn truyn dn d liu.

Cc khi c bn trong s khi ca I2C khng c nhiu khc bit so vi SPI. Tuy nhin I2C cn c thm khi pht hin bit Start v bit Stop ca d liu (Start and Stop bit detect) v khi xc nh a ch (Match detect). Cc thanh ghi lin quan n I2C bao gm: Thanh ghi SSPCON v SSPCON2: iu khin MSSP. Thanh ghi SSPSTAT: thanh ghi cha cc trng thi hot ng ca MSSP. Thanh ghi SSPBUF: buffer truyn nhn ni tip. Thanh ghi SSPSR: thanh ghi dch dng truyn nhn d liu. Thanh ghi SSPADD: thanh ghi cha a ch ca giao din MSSP. Cc thanh ghi SSPCON, SSPCON2 cho php c v ghi. Thanh ghi SSPSTAT ch cho php c v ghi 2 bit u, 6 bit cn li ch cho php c. Thanh ghi SSPBUF cha d liu s c truyn i hoc nhn c v ng vai tr nh mt thanh ghi m cho thanh ghi dch d liu SSPSR. Thanh ghi SSPADD cha a ch ca thit b ngoi vi cn truy xut d liu ca I2C khi hot ng Slave mode. Khi hot ng Master mode, thanh ghi SSPADD cha gi tr to ra tc baud cho xung clock dng truyn nhn d liu. Trong qu trnh nhn d liu, sau khi nhn c 1 byte d liu hon chnh, thanh ghi SSPSR s chuyn d liu vo thanh ghi SSPBUF. Thanh ghi SSPSR khng c v ghi c, qu trnh truy xut thanh ghi ny phi thng qua thanh ghi SSPBUF. Trong qu trnh truyn d liu, d liu cn truyn khi c a vo thanh ghi SSPBUF cng s ng thi a vo thanh ghi SSPSR. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. I2C c nhiu ch hot ng v c iu khin bi cc bit SSPCON<3:0>, bao gm: I2C Master mode, xung clock = fosc/4*(SSPADD+1). I2C Slave mode, 7 bit a ch. I2C Slave mode, 10 bit a ch. I2C Slvae mode, 7 bit a ch, cho php ngt khi pht hin bit Start v bit Stop. I2C Slave mode, 10 bit a ch, cho php ngt khi pht hin bit Start v bit Stop. I2C Firmware Control Master mode. a ch truyn i s bao gm cc bit a ch v mt bit xc nh thao tc (c hay ghi d liu) vi i tng cn truy xut d liu. Khi la chn giao din I2C v khi set bit SSPEN, cc pin SCL v SDA s trng thi cc thu h. Do trong trng hp cn thit ta phi s dng in tr ko ln bn ngoi vi iu khin, bn cnh cn n nh cc gi tr ph hp cho cc bit TRISC<4:3> (bit iu khin xut nhp cc chn SCL v SDA). 2.12.2.2.1 I2C SLAVE MODE. Vic trc tin l phi set cc pin SCL v SDA l input (set bit TRISC<4:3>). I2C ca vi iu khin s c iu khin bi mt vi iu khin hoc mt thit b ngoi vi khc thng qua cc a ch. Khi a ch ny ch n vi iu khin, th ti thi im ny v ti thi im d liu c truyn nhn xong sau , vi iu khin s to ra xung bo hiu kt thc d liu, gi tr trong thanh ghi SSPSR s c a vo thanh ghi SSPBUF. Tuy nhin xung s khng c to ra nu mt trong cc trng hp sau xy ra: Bit BF (SSPSTAT<0>) bo hiu buffer y c set trc khi qu trnh truyn nhn xy ra.

Bit SSPOV (SSPCON<6>) c set trc khi qu trnh truyn nhn xy ra (SSPOV c set trong trng hp khi mt byte khc c nhn vo trong khi d liu trong thanh ghi SSPBUF trc vn cha c ly ra). Trong cc trng hp trn, thanh ghi SSPSR s khng a gi tr vo thanh ghi SSPBUF, nhng bit SSPIF (PIR1<3>)s c set. qu trnh truyn nhn d liu c tip tc, cn c d liu t thanh ghi SSPBUF vo trc, khi bit BF s t ng c xa, cn bit SSPOV phi c xa bng chng trnh. Khi MSSP c kch hot, n s ch tn hiu bt u hot ng. Sau khi nhn c tn hiu bt u hot ng (cnh xung u tin ca pin SDA), d liu 8 bit s c dch vo thanh ghi SSPSR. Cc bit a vo s c ly mu ti cnh ln ca xung clock. Gi tr nhn c t thanh ghi SSPSR s c so snh vi gi tr trong thanh ghi SSPADD ti cnh xung ca xung clock th 8. Nu kt qu so snh bng nhau, tc l I2C Master ch nh i tng giao tip l vi iu khin ang ch Slave mode (ta gi hin tng ny l address match), bit BF v SSPOV s c xa v 0 v gy ra cc tc ng sau: 1. Gi tr trong thanh ghi SSPSR c a vo thanh ghi SSPBUF. 2. Bit BF t ng c set. 3. Mt xung c to ra. 4. C ngt SSPIF c set (ngt c kch hot nu c cho php trc ) ti cnh xung ca xung clock th 9. Khi MSSP ch I2C Slave mode 10 bit a ch, vi iu khin cn phi nhn vo 10 bit a ch so snh. Bit (SSPSTAT<2>) phi c xa v 0 cho php nhn 2 byte a ch. Byte u tin c nh dng l 11110 A9 A8 0 trong A9, A8 l hai bit MSB ca 10 bit a ch. Byte th 2 l 8 bit a ch cn li. Qutrnh nhn dng a ch ca MSSP ch I2C Slave mode 10 bit a ch nh sau: 1. u tin 2 bit MSB ca 10 bit a ch c nhn trc, bit SSPIF, BF v UA (SSPSTAT<1>) c set (byte a ch u tin c nh dng l 11110 A9 A8 0) . 2. Cp nht vo 8 bit a ch thp ca thanh ghi SSPADD, bit UA s c xa bi vi iu khin khi to xung clock pin SCL sau khi qu trnh cp nht hon tt. 3. c gi tr thanh ghi SSPBUF (bit BF s c xa v 0) v xa c ngt SSPIF. 4. Nhn 8 bit a ch cao, bit SSPIF, BF v UA c set. 5. Cp nht 8 bit a ch nhn c vo 8 bit a ch cao ca thanh ghi SSPADD, nu a ch nhn c l ng (address match), xung clock chn SCL c khi to v bit UA c set. 6. c gi tr thanh ghi SSPBUF (bit BF s c xa v 0) v xa c ngt SSPIF. 7. Nhn tn hiu Start. 8. Nhn byte a ch cao (bit SSPIF v BF c set). 9. c gi tr thanh ghi SSPBUF (bit BF c xa v 0) v xa c ngt SSPIF. Trong cc bc 7,8,9 xy ra trong qu trnh truyn d liu ch Slave mode. Xem gin xung ca I2C c c hnh nh c th hn v cc bc tin hnh trong qu trnh nhn dng a ch. Xt qu trnh nhn d liu ch Slave mode, cc bit a ch s c I2C Master a vo trc. Khi bit trong cc bit a ch c gi tr bng 0 (bit ny c nhn dng sau khi cc bit a ch c nhn xong) v a ch c ch nh ng (address match), bit ca thanh ghi SSPSTAT c xa v 0 v ng d liu SDI c a v mc logic thp (xung ). Khi bit SEN (SSPCON<0>) c set, sau khi 1 byte d liu c nhn, xung clock t chn RC3/SCK/SCL s c a xung mc thp, mun khi to li xung clock ta set bit CKP (SSPCON<4>). iu ny s lm cho hin tng trn d liu khng xy ra v bit SEN cho php ta iu khin c xung clock dch d liu thng qua bit CKP (tham kho gin xung bit thm chi tit). Khi hin

tng trn d liu xy ra, bit BF hoc bit SSPOV s c set. Ngt s xy ra khi mt byte d liu c nhn xong, c ngt SSPIF s c set v phi c xa bng chng trnh.

Xt qu trnh truyn d liu, khi bit trong cc bit d liu mang gi tr 1 v a ch c ch nh ng (address match), bit ca thanh ghi SSPSTAT s c set. Cc bit a ch c nhn trc v a vo thanh ghi SSPBUF. Sau xung c to ra, xung clock chn RC3/SCK/SCL c a xung mc thp bt chp trng thi ca bit SEN. Khi I2C Master s khng c a xung clock vo I2C Slave cho n khi d liu thanh ghi SSPSR trng thi wsn sng cho qu trnh truyn d liu (d liu a vo thanh ghi SSPBUF s ng thi c a vo thanh ghi SSPSR). Tip theo cho php xung pin RC3/SCK/SCL bng cch set bit CKP (SSPCON<4>). Tng bit ca byte d liu s c dch ra ngoi ti mi cnh xung ca xung clock. Nh vy d liu s sn sng ng ra khi xung clock mc logic cao, gip cho I2C Master nhn c d liu ti mi cnh ln ca xung clock. Nh vy trong qu trnh truyn d liu bit SEN khng ng vai tr quan trng nh trong qu trnh nhn d liu. Ti cnh ln xung clock th 9, d liu c dch hon ton vo I2C Master, xung s c to ra I2C Master, ng thi pin SDA s c gi mc logic cao. Trong trng hp xung c cht bi I2C Slave, thanh ghi SSPSTAT s c reset. I2C Slave s ch tn hiu ca bit Start tip tc truyn byte d liu tip theo (a byte d liu tip theo vo thanh ghi SSPBUF v set bit CKP. Ngt MSSP xy ra khi mt byte d liu kt thc qu trnh truyn, bit SSPIF c set ti cnh xung ca xung clock th 9 v phi c xa bng chng trnh m bo s c set khi byte d liu tip theo truyn xong.

Qu trnh truyn nhn cc bit a ch cho php I2C Master chn la i tng I2C Slave cn truy xut d liu. Bn cnh I2C cn cung cp thm mt a ch GCA (General Call Address) cho php chn tt c cc I2C Slave. y l mt trong 8 a ch c bit ca protocol I2C. a ch ny c nh dng l mt chui 0 vi =0 v c cho php bng cch set bit GCEN (SSPCON2<7>). Khi a ch nhn vo s c so snh vi thanh ghi SSPADD v vi a ch GCA.

Qu trnh nhn dng a ch GCA cng tng t nh khi nhn dng cc a ch khc v khng c s khc bit r rng khi I2C hot ng ch a ch 7 bit hay 10 bit. 2.12.2.2.2 I2C MASTER MODE I2C Master mode c xc lp bng cch a cc gi tr thch hp vo cc bit SSPM ca thanh ghi SSPCON v set bit SSPEN. ch Master, cc pin SCK v SDA s c iu khin bi phn cng ca MSSP.

I2C Master ng vai tr tch cc trong qu trnh giao tip v iu khin cc I2C Slave thng qua vic ch ng to ra xung giao tip v cc iu kin Start, Stop khi truyn nhn d liu. Mt byte d liu c th c bt u bng iu kin Start, kt thc bng iu kin Stop hoc bt u v kt thc vi cng mt iu kin khi ng lp li (Repeated Start Condition). Xung giao tip ni tip s c to ra t BRG (Baud Rate Generator), gi tr n nh tn s xung clock ni tip c ly t 7 bit thp ca thanh ghi SSPADD. Khi d liu c a vo thanh ghi SSPBUF, bit BF c set v BRG t ng m ngc v 0 v dng li, pin SCL c gi nguyn trng thi trc .Khi d liu tip theo c a vo, BRG s cn mt khong thi

gian TBRG t ng reset li gi tr tip tc qu trnh m ngc. Mi vng lnh (c thi gian TCY ) BRG s gim gi tr 2 ln.

Cc gi tr c th ca tn s xung ni tip do BRG to ra c lit k trong bng sau:

Trong gi tr BRG l gi tr c ly t 7 bit thp ca thanh ghi SSPADD. Do I2C ch Master mode, thanh ghi SSPADD s khng c s dng cha a ch, thay vo chc nng ca SSPADD l thanh ghi cha gi tr ca BRG. to c iu kin Start, trc ht cn a hai pin SCL v SDA ln mc logic cao v bit SEN (SSPCON2<0>) phi c set. Khi BRG s t ng c gi tr 7 bit thp ca thanh ghi SSPADD v bt u m. Sau khong thi gian TBRG, pin SDA c a xung mc logic thp. Trng thi pin SDA mc logic thp v pin SCL mc logic cao chnh l iu kin Start ca I2C Master mode. Khi bit S (SSPSTAT<3>) s c set. Tip theo BRG tip tc ly gi tr t thanh ghi SSPADD tip tc qu trnh m, bit SEN c t ng xa v c ngt SSPIF c set. Trong trng hp pin SCL v SDA trng thi logic thp, hoc l trong qu trnh to iu kin Start, pin SCL c a v trng thi logic thp trc khi pin SDA c a v trang thi logic thp, iu kin Start s khng c hnh thnh, c ngt BCLIF s c set v I2C s trng thi tm ngng hot ng (Idle).

Tn hiu Stop s c a ra pin SDA khi kt thc d liu bng cch set bit PEN (SSPCON2<2>). Sau cnh xung ca xung clock th 9 v vi tc ng ca bit iu khin PEN, pin SDA cng c a xung mc thp, BRG li bt u qu trnh m. Sau mt khong thi gian TBRG, pin SCL c a ln mc logic cao v sau mt khong thi gian TBRG na pin SDA cng c a ln mc cao. Ngay ti thi im bit P (SSPSTAT<4>) c set, ngha l iu kin Stop c to ra. Sau mt khong thi gian TBRG na, bit PEN t ng c xa v c ngt SSPIF c set.

to c diu kin Start lp li lin tc trong qu trnh truyn d liu, trc ht cn set bit RSEN (SSPCON2<1>). Sau khi set bit RSEN, pin SCL c a xung mc logic thp, pin SDA c a ln mc logic cao, BRG ly gi tr t thanh ghi SSPADD vo bt u qu trnh m. Sau khong thi gian TBRG, pin SCL cng c a ln mc logic cao trong khong thi gian TBRG tip theo. Trong khong thi gian TBRG k tip, pin SDA li c a xung mc logic thp trong khi SCL vn c gi mc logic cao. Ngay thi im bit S (SSPSTAT<3>) c set bo hiu iu kin Start c hnh thnh, bit RSEN t ng c xa v c ngt SSPIF s c set sau mt khong thi gian TBRG na. Lc ny a ch ca I2C Slave c th c a vo thanh ghi SSPBUF, sau ta ch vic a tip a ch hoc d liu tip theo vo thanh ghi SSPBUF mi khi nhn c tn hiu t I2C Slave, I2C Master s t ng to tn hiu Start lp li lin tc cho qu trnh truyn d liu lin tc. Cn ch l bt c mt trnh t no sai trong qu trnh t o iu kin Start lp li s lm cho bit BCLIF c set v I2C c a v trng thi Idle.

Xt qu trnh truyn d liu, xung clock s c a ra t pin SCL v d liu c a ra t pin SDA. Byte d liu u tin phi l byte a ch xc nh I2C Slave cn giao tip v bit (trong trng hp ny = 0). u tin cc gi tr a ch s c a vo thanh ghi SSPBUF, bit BF t ng c set ln 1 v b m to xung clock ni tip BRG (Baud Rate Generator) bt u hot ng. Khi tng bit d liu (hoc a ch v bit ) s c dch ra ngoi theo tng cnh xung ca xung clock sau khi cnh xung u tin ca pin SCL c nhn din (iu kin Start), BRG bt u m ngc v 0. Khi tt c cc bit ca byte d liu c c a ra ngoi, b m BRG mang gi tr 0. Sau , ti cnh xung ca xung clock th 8, I2C Master s ngng tc ng ln pin SDA ch i tn hiu t I2C Slave (tn hiu xung ). Ti cnh xung ca xung clock th 9, I2C Master s ly mu tn hiu t pin SDA kim tra xem a ch c I2C Slave nhn dng cha, trng thi c a vo bit ACKSTAT (SSPCON2<6>). Cng ti thi im cnh xung ca xung clock th 9, bit BF c t ng clear, c ngt SSPIF c set v BRG tm ngng hot ng cho ti khi d liu hoc a ch tip theo c a vo thanh ghi SSPBUF, d liu hoc a ch s tip tc c truyn i ti cnh xung ca xung clock tip theo.

Xt qu trnh nhn d liu ch I2C Master mode. Trc tin ta cn set bit cho php nhn d liu RCEN (SSPCON2<3>). Khi BRG bt u qu trnh m, d liu s c dch vo I2C Master qua pin SDA ti cnh xung ca pin SCL. Ti cnh xung ca xung clock th 8, bit c hiu cho php nhn RCEN t ng c xa, d liu trong thanh ghi SSPSR c a vo thanh ghi SSPBUF, c hiu BF c set, c ngt SSPIF c set, BRG ngng m v pin SCL c a v mc logic thp. Khi MSSP trng thi tm ngng hot ng ch i lnh tip theo. Sau khi c gi tr thanh ghi SSPBUF, c hiu BF t ng c xa. Ta cn c th gi tn hiu bng cch set bit ACKEN (SSPCON2<4>).

2.13 CNG GIAO TIP SONG SONG PSP (PARALLEL SLAVE PORT) Ngoi cc cng ni tip v cc giao in ni tip c trnh by phn trn, vi iu khin PIC16F877A cn c h tr mt cng giao tip song song v chun giao tip song song thng qua PORTD v PORTE. Do cng song song ch hot ng ch Slave mode nn vi iu khin khi giao tip qua giao din ny s chu s iu khin ca thit b bn ngoi thng qua cc pin ca PORTE, trong khi d liu s c c hoc ghi theo dng bt ng b thng qua 8 pin ca PORTD Bit iu khin PSP l PSPMODE (TRISE<4>). PSPMODE c set s thit lp chc nng cc pin ca PORTE l cc pin cho php c d liu ( ), cho php ghi d liu ( ) v pin chn vi iu khin ( ) phc v cho vic truyn nhn d liu song song thng qua bus d liu 8 bit ca PORTD. PORTD lc ny ng vai tr l thanh ghi cht d liu 8 bit, ng thi tc ng ca thanh ghi TRISD cng s c b qua do

PORTD lc ny chu s iu khin ca cc thit b bn ngoi. PORTE vn chu s tc ng ca thanh ghi TRISE, do cn xc lp trng thi cc pin PORTE l input bng cch set cc bit TRISE<2:0>. Ngoi ra cn a gi tr thch hp cc bit PCFG3:PCFG0 (thanh ghi ADCON1<3:0>) n nh cc pin ca PORTE l cc pin I/O dng digital (PORTE cn l cc pin chc nng ca khi ADC). Khi cc pin v cng mc thp, d liu t bn ngoi s c ghi ln PORTD. Khi mt trong hai pin trn chuyn ln mc logic cao, c hiu bo d liu trong buffer y BIF (TRISE<7>) c set v c ngt PSPIF (PIR1<7>) c set bo hiu kt thc ghi d liu. Bit BIF ch c xa v 0 khi d liu va nhn c PORTD c c vo. Bit bo hiu d liu nhn c trong buffer b trn IBOV (TRISE<5>) s c set khi vi iu khin nhn tip d liu tip theo trong khi cha c vo d liu nhn c trc . Khi cc pin v cng mc logic thp, bit bo hiu buffer truyn d liu y BOF (TRISE<6>) s c xa ngay lp tc bo hiu PORTD sn sng cho qu trnh c d liu. Khi mt trong hai pin trn chuyn sang mc logic cao, c ngt PSPIF s c set bo hiu qu trnh c d liu hon tt. Bit BOF vn c gi mc logic 0 cho n khi d liu tip theo c a vo PORTD. Cn ch l ngt SSPIF c iu khin bi bit PSPIE (PIE1<7>) v phi c xa bng chng trnh. Cc thanh ghi lin quan n PSP bao gm: Thanh ghi PORTD (a ch 08h): cha d liu cn c hoc ghi. Thanh ghi PORTE (a ch 09h): cha gi tr cc pin PORTE. Thanh ghi TRISE (a ch 89h): cha cc bit iu khin PORTE v PSP. Thanh ghi PIR1 (a ch 0Ch): cha c ngt PSPIF. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt PSP. Thanh ghi ADCON1 (a ch 9Fh): iu khin khi ADC ti PORTE. Chi tit v cc thanh ghi s c trnh by c th ph lc 2. 2.14 TNG QUAN V MT S C TNH CA CPU. 2.14.1 CONFIGURATION BIT y l cc bit dng la chn cc c tnh ca CPU. Cc bit ny c cha trong b nh chng trnh ti a ch 2007h v ch c th c truy xut trong qu trnh lp trnh cho vi iu khin. Chi tit v cc bit ny nh sau:

Bit 13 CP: (Code Protection) 1: tt ch bo v m chng trnh. 0: bt ch bo v m chng trnh. Bit 12, 5, 4: khng quan tm v c mc nh mang gi tr 0. Bit 11 DEBUG (In-circuit debug mode bit) 1:khng cho php, RB7 v RB6 c xem nh cc pin xut nhp bnh thng. 0:cho php, RB7 v RB6 l cc pin c s dng cho qu trnh debug. Bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bit 11: Tt chc nng chng ghi, EECON s iu khin qu tr nh ghi ln ton b nh chng trnh. 10: ch chng t a ch 0000h:00FFh. 01: ch chng ghi t a ch 0000h:07FFh. 00: ch chng ghi t a ch 0000h:0FFFh. Bit 8 CPD Data EEPROM Memory Write Protection bit

1: Tt chc nng bo v m ca EEPROM. 0: Bt chc nng bo v m. Bit 7 LVP Low-Voltage (Single supply) In-Circuit Serial Programming Enable bit 1: Cho php ch np in p thp, pin RB3/PGM c s dng cho ch ny. 0: Khng cho php ch np in p thp, in p cao c a vo t pin, pin RB3 l pin I/O bnh thng. Bit 6 BODEN Brown-out Reset Enable bit 1: cho php BOR (Brown-out Reset) 0: khng cho php BOR. Bit 3 Power-up Timer Enable bit 1: khng cho php PWR. 0: cho php PWR. Bit 2 WDTEN Watchdog Timer Enable bit 1: cho php WDT. 0: khng cho php WDT. Bit 1-0 FOSC1:FOSC0 la chn loi oscillator 11: s dng RC oscillator. 10: s dng HS oscillator. 01: s dng XT oscillator. 00: s dng LP oscillator.

Chi tit v cc c tnh s c cp c th trong cc phn tip theo. 2.14.2 CC C TNH CA OSCILLATOR PIC16F877A c kh nng s dng mt trong 4 loi oscillator, l: LP: (Low Power Crystal). XT: Thch anh bnh thng. HS: (High-Speed Crystal). RC: (Resistor/Capacitor) dao ng do mch RC to ra. i vi cc loi oscillator LP, HS, XT, oscillator c gn vo vi iu khin thng qua cc pin OSC1/CLKI v OSC2/CLKO. i vi cc ng dng khng cn cc loi oscillator tc cao, ta c th s dng mch dao ng RC lm ngun cung cp xung hot ng cho vi vi iu khin. Tn s to ra ph thuc vo cc gi tr in p, gi tr in tr v t in, bn cnh l s nh hng ca cc yu t nh nhit , cht lng ca cc linh kin. Cc linh kin s dng cho mch RC oscillator phi bo m cc gi tr sau: 3 K < REXT < 100 K CEXT >20 pF 2.14.3 CC CH RESET C nhiu ch reset vi iu khin, bao gm: Power-on Reset POR (Reset khi cp ngun hot ng cho vi iu khin). reset trong qu trnh hot ng. t ch sleep. WDT reset (reset do khi WDT to ra trong qu trnh hot ng). WDT wake up t ch sleep. Brown-out reset (BOR).

Ngoi tr reset POR trng thi cc thanh ghi l khng xc nh vWDT wake up khng nh hng n trng thi cc thanh ghi, cc ch reset cn li u a gi tr cc thanh ghi v gi tr ban u c n nh sn. Cc bit v ch th trng thi hot ng, trng thi reset ca vi iu khin v c iu khin bi CPU. reset: Khi pin mc logic thp, vi iu khin s c reset. Tn hiu reset c cung cp bi mt mch ngoi vi vi cc yu cu c th sau: Khng ni pin trc tip ln ngun VDD. R1 phi nh hn 40 K m bo cc c tnh in ca vi iu khin. R2 phi ln hn 1 K hn dng i vo vi iu khin. reset cn c chng nhiu bi mt b lc trnh cc tn hiu nh tc ng ln pin . Power-on reset (POR): y l xung reset do vi iu khin to ra khi pht hin ngun cung cp VDD. Khi hot ng ch bnh thng, vi iu khin cn c m bo cc thng s v dng in, in p hot ng bnh thng. Nhng nu cc tham s ny khng c m bo, xung reset do POR to ra s a vi iu khin v trng thi reset v ch tip tc hot ng khi no cc tham s trn c m bo. Power-up Timer (PWRT): y l b nh thi hot ng da vo mch RC bn trong vi iu khin. Khi PWRT c kch hot, vi iu khin s c a v trng thi reset. PWRT s to ra mt khong thi gian delay (khong 72 ms) VDD tng n gi tr thch hp. Oscillator Start-up Timer (OST): OST cung cp mt khong thi gian delay bng 1024 chu k xung ca oscillator sau khi PWRT ngng tc ng (vi iu khin iu kin hot ng) m bo s n nh ca xung do oscillator pht ra. Tc ng ca OST cn xy ra i vi POR reset v khi vi iu khin c nh thc t ch sleep. OST ch tc ng i vi cc lai oscillator l XT, HS v LP. Brown-out reset (BOR): Nu VDD h xung thp hn gi tr VBOR (khong 4V) v ko di trong khong thi gian ln hn TBOR (khong 100 us), BOR c kch hot v vi iu khin c a v trng thi BOR reset. Nu in p cung cp cho vi iu khin h xung thp hn VBOR trong khong thi gian ngn hn TBOR, vi iu khin s khng c reset. Khi in p cung cp cho vi iu khin hot ng, PWRT c kch hot to ra mt khong thi gian delay (khong 72ms). Nu trong khong thi gian ny in p cung cp cho vi iu khin li tip tc h xung di mc in p VBOR, BOR reset s li c kch hot. Khi vi iu khin in p hot ng. Mt im cn ch l khi BOR reset c cho php, PWRT cng s hot ng bt chp trng thi ca bit PWRT. Tm li vi iu khin hot ng c t khi cp ngun cn tri qua cc bc sau: POR tc ng. PWRT (nu c cho php hot ng) to ra khong thi gian delay TPWRT n nh ngun cung cp. OST (nu c cho php) to ra khong thi g ian delay bng 1024 chu k xung ca oscillator n nh tn s ca oscillator. n thi im ny vi iu khin mi bt u hot ng bnh thng. Thanh ghi iu khin v ch th trng thi ngun cung cp cho vi iu khin l thanh ghi PCON (xem ph lc 2 bit thm chi tit).

2.14.4 NGT (INTERRUPT) PIC16F877A c n 15 ngun to ra hot ng ngt c iu khin bi thanh ghi INTCON (bit GIE). Bn cnh mi ngt cn c mt bit iu khin v c ngt ring. Cc c ngt vn c set bnh thng khi tha mn iu kin ngt xy ra bt chp trng thi ca bit GIE, tuy nhin hot ng ngt vn ph thuc vo bit GIE v cc bit iu khin khc. Bit iu khin ngt RB0/INT v TMR0 nm trong thanh ghi INTCON, thanh ghi ny cn cha bit cho php cc ngt ngoi vi PEIE. Bit iu khin cc ngt nm trong thanh ghi PIE1 v PIE2. C ngt ca cc ngt nm trong thanh ghi PIR1 v PIR2. Trong mt thi im ch c mt chng trnh ngt c thc thi, chng trnh ngt c kt thc bng lnh RETFIE. Khi chng trnh ngt c thc thi, bit GIE t ng c xa, a ch lnh tip theo ca chng trnh chnh c ct vo trong b nh Stack v b m chng trnh s ch n a ch 0004h. Lnh RETFIE c dng thot khi chng trnh ngt v quay tr v chng trnh chnh, ng thi bit GIE cng s c set cho php cc ngt hot ng tr li. Cc c hiu c dng kim tra ngt no ang xy ra v phi c xa bng chng trnh trc khi cho php ngt tip tc hot ng tr li ta c th pht hin c thi im tip theo m ngt xy ra. i vi cc ngt ngoi vi nh ngt t chn INT hay ngt t s thay i trng thi cc pin ca PORTB (PORTB Interrupt on change), vic xc nh ngt no xy ra cn 3 hoc 4 chu k lnh ty thuc vo thi im xy ra ngt. Cn ch l trong qu trnh thc thi ngt, ch c gi tr ca b m chng trnh c ct vo trong Stack, trong khi mt s thanh ghi quan trng s khng c ct v c th b thay i gi tr trong qu trnh thc thi chng trnh ngt. iu ny nn c x l bng chng trnh trnh hin tng trn xy ra.

2.14.4.1 NGT INT Ngt ny da trn s thay i trng thi ca pin RB0/INT. Cnh tc ng gy ra ngt c th l cnh ln hay cnh xung v c iu khin bi bit INTEDG (thanh ghi OPTION_ REG <6>). Khi c cnh tc ng thch hp xut hin ti pin RB0/INT, c ngt INTF c set bt chp trng thi cc bit iu khin GIE v PEIE. Ngt ny c kh nng nh thc vi iu khin t ch sleep nu bit cho php ngt c set trc khi lnh SLEEP c thc thi. 2.14.4.2 NGT DO S THAY I TRNG THI CC PIN TRONG PORTB Cc pin PORTB<7:4> c dng cho ngt ny v c iu khin bi bit RBIE (thanh ghi INTCON<4>). C ngt ca ngt ny l bit RBIF (INTCON<0>). 2.14.5 WATCHDOG TIMER (WDT) Watchdog timer (WDT) l b m c lp dng ngun xung m t b to xung c tch hp sn trong vi iu khin v khng ph thuc vo bt k ngun xung clock ngoi vi no. iu c ngha l WDT vn hot ng ngay c khi xung clock c ly t pin OSC1/CLKI v pin OSC2/CLKO ca vi iu khin ngng hot ng (chng hn nh do tc ng ca lnh sleep). Bit iu khin ca WDT l bit WDTE nm trong b nh chng trnh a ch 2007h (Configuration bit). WDT s t ng reset vi iu khin (Watchdog Timer Reset) khi b m ca WDT b trn (nu WDT c cho php hot ng), ng thi bit t ng c xa. Nu vi iu khin ang ch sleep th WDT s nh thc vi iu khin (Watchdog Timer Wake-up) khi b m b trn. Nh vy WDT c tc dng reset vi iu khin thi im cn thit m khng cn n s tc ng t bn ngoi, chng hn nh trong qu tr nh thc thi lnh, vi iu khin b kt mt ch no m khng thot ra c, khi vi iu khin s t ng c reset khi WDT b trn chng trnh hot ng ng tr li. Tuy nhin khi s dng WDT cng c s phin toi v vi iu khin s thng xuyn c reset sau mt thi gian nht nh, do i cn tnh ton thi gian thch hp xa WDT (dng lnh CLRWDT). V vic n nh thi gian reset c linh ng, WDT

cn c h tr mt b chia tn s prescaler c iu khin bi thanh ghi OPTION_REG (prescaler ny c chia x vi Timer0). Mt im cn ch na l lnh sleep s xa b m WDT v prescaler. Ngoi ra lnh xa CLRWDT ch xa b m ch khng lm thay i i tng tc ng ca prescaler (WDT hay Timer0). Xem li Timer0 v thanh ghi OPTION_REG (ph lc 2) bit thm chi tit. 2.14.6 CH SLEEP y l ch hot ng ca vi iu khin khi lnh SLEEP c thc thi. Khi nu c cho php hot ng, b m ca WDT s b xa nhng WDT vn tip tc hot ng, bit (STATUS<3>) c reset v 0, bit c set, oscillator ngng tc ng v cc PORT gi nguyn trng thi nh trc khi lnh SLEEP c thc thi. Do khi ch SLEEP, dng cung cp cho vi iu khin l rt nh nn ta cn thc hin cc bc sau trc khi vi iu khin thc thi lnh SLEEP: a tt c cc pin v trng thi VDD hoc VSS Cn bo m rng khng c mch ngoi vi no c iu khin bi dng in ca vi iu khin v dng in nh khng kh nng cung cp cho cc mch ngoi vi hot ng. Tm ngng hot ng c khi A/D v khng cho php cc xung clock t bn ngoi tc ng vo vi iu khin. n chc nng ko ln in tr PORTB. Pin phi mc logic cao.

2.14.6.1 NH THC VI IU KHIN Vi iu khin c th c nh thc di tc ng ca mt trong s cc hin tng sau: Tc ng ca reset ngoi vi thng qua pin . Tc ng ca WDT khi b trn. Tc ng t cc ngt ngoi vi t PORTB (PORTB Interrupt on change hoc p in INT). Cc bit v c dng th hin trng thi ca vi iu khin v pht hin ngun tc ng lm reset vi iu khin. Bit c set khi vi iu khin c cp ngun v c reset v 0 khi vi iu khin ch sleep. Bit c reset v 0 khi WDT tc ng do b m b trn. Ngoi ra cn c mt s ngun tc ng khc t cc chc nng ngoi vi bao gm: c hay ghi d liu thng qua PSP (Parallel Slave Port). Ngt Timer1 khi hot ng ch m bt ng b. Ngt CCP khi hot ng ch Capture. Cc hin tng c bit lm reset Timer1 khi hot ng ch m bt ng b dng ngun xung clock bn ngoi). Ngt SSP khi bit Start/Stop c pht hin. SSP hot ng ch Slave mode khi truyn hoc nhn d liu. Tc ng ca USART t cc pin RX hay TX khi hot ng ch Slave mode ng b. Khi chuyn i A/D khi ngun xung clock hot ng dng RC. Hon tt qu trnh ghi vo EEPROM. Ng ra b so snh thay i trng thi. Cc tc ng ngoi vi khc khng c tc dng nh thc vi iu khin v khi ch sleep cc xung clock cung cp cho vi iu khin ngng hot ng. Bn cnh cn cho php cc ngt hot ng trc khi lnh SLEEP c thc thi bo m tc ng ca cc ngt. Vic nh thc vi iu khin t cc ngt vn c thc thi bt chp trng thi ca bit GIE. Nu bit GIE mang gi tr 0, vi iu khin s thc thi lnh tip theo sau lnh SLEEP ca chng trnh (v chng trnh ngt khng c cho php thc thi). Nu bit GIE c set trc khi lnh SLEEP c thc thi, vi iu khin s thc thi lnh tip theo ca chng trnh v sau nhy ti a ch cha chng trnh ngt (0004h). Trong trng hp lnh tip theo khng ng vai tr quan trng trong chng trnh, ta cn t thm lnh NOP sau lnh SLEEP b qua tc ng ca lnh ny, ng thi gip ta d dng hn trong vic kim sot hot ng ca chng trnh ngt. Tuy nhin cng c mt s im cn lu nh sau: Nu ngt xy ra trc khi lnh SLEEP c thc thi, lnh SLEEP s khng c thc thi v thay vo l lnh NOP, ng thi cc tc ng ca lnh SLEEP cng s c b qua. Nu ngt xy ra trong khi hay sau khi lnh SLEEP c thc thi, vi iu khin lp tc c nh thc t ch sleep, v lnh SLEEP s c thc thi ngay sau khi vi iu khin c nh thc. kim tra xem lnh SLEEP c thc thi hay cha, ta kim tra bit . Nu bit vn mang gi tr 1 tc l lnh SLEEP khng c thc thi v thay vo l lnh NOP. Bn cnh ta cn xa WDT chc chn rng WDT c xa trc khi thc thi lnh SLEEP, qua cho php ta xc nh c thi im vi iu khin c nh thc do tc ng ca WDT.

LI KT
Sau 1 thng lm vic khn trng cng vi s nhit tnh ca gio vin hng dn l thy TNG THANH NHN. ti: Thit k bng pha mu led ma trn dng IC ghi dch cd4094 v vi x l Pic 16f877a hon thnh ng thi gian qui nh. Mc d thi gian hn ngn, ti liu tham kho cng cha nhiu, v c nhiu vn ny sinh trong qu tr nh thit k phn cng, lp trnh phn mm, nhng chng em c gng lm vic ht sc mnh cng vi s tn tm gip ca gio vin hng dn nn t c nhng yu cu t ra. Mc d vy th cc thiu st vn xy ra, qua y nhm thc hin chng em cng mong l c s ng gp t pha cc thy, c cng nh l cc bn. Nhng s ng gp t pha cc thy cng nh l cc bn s l nhng kinh nghim qu bu m chng em cn c sau khi ra trng. Qua qu trnh thc hin n,chng em t nh gi c phn no cn hn ch v t nhiu b xung cc kin thc c n hn hp trong thi gian hc ti trng. Chng em xin chn thnh cm n s gip tn tnh, qu bu ca gio vin hng dn, cc gio vin trong khoa v ton th cc bn to nhiu iu kin gip cho nhm thc hin chng em hon thnh tt cc nhim v c giao ng thi gian qui nh. Mt ln na nhm sinh vin thc hin chng em xin chn thnh cm n tt c mi ngi..

TI LIU THAM KHO

-H Trung M Gio trnh Quang in t.i hc Bch khoa Tp.H Ch Minh.

Cc trang web: - WWW.DIENTUVIETNAM.NET - WWW.GOOGLE.COM.VN - WWW.DATASHEET.COM. - WWW.PICVIETNAM.COM