VIETNAM NATIONAL UNIVERSITY, HANOI

College of Technology
FPGA Design Course Part 2: Practice Working with ModelSim
Nguyen Ngoc Mai Tran Van Huan Researchers, SIS Laboratory Coltech (VNU) http://www.coltech.vnu.vn/sis

Topics

1. ModelSim Quick Guide Introduction Getting start with Projects

2. Practice: Lab 1: Design a 2-to-1 Multiplexer

23 October 2013 23-Oct-13

Goals Be familiar with using ModelSim Be able to program some basic digital circuits by VHDL

23 October 2013 23-Oct-13

Section 1: ModelSim Quick Guide

1. Introduction 2. Getting start with Projects

23 October 2013 23-Oct-13

Introduction to ModelSim

(C) Mentor Graphics A Simulator and Debugger HDL Tool Support: VHDL, Verilog, SystemC, Docs (pdf): Users Guide
Reference Manual

23 October 2013 23-Oct-13

Getting start with ModelSim Projects

Create a New project

Add Items to the project

Compile the project

Simulate the design

Analyzing Waveforms
23 October 2013 23-Oct-13

1 Creating a new project

Launch ModelSim Create new folder for each project

Command: mkdir <folder_name> Example: mkdir counter_demo

Select File > New > Project Enter Project Name OK

23-Oct-13 23 October 2013

2 Adding Items to the project

Example: Add counter.vhd file to the project

23-Oct-13 23 October 2013

3 Compiling the project

GUI: Select Compile > Compile All or

23-Oct-13 23 October 2013

4 Simulating the design

10

GUI: Select Simulate > Start Simulation or Double-click on Library.work.counter.only or Command: vsim counter.vhd

23-Oct-13 23 October 2013

4 Simulating the design (cnt.)

11

Add All signals to wave:

GUI: Right-click on Objects window > Add to wave > Signals in Design Command: add wave r /*

Create wave for a signal

Modify/Edit Waveform
Run Simulation

23-Oct-13 23 October 2013

5 Analyzing Waveforms

12

Add cursor

23-Oct-13 23 October 2013

13

Section 2: Practice

A 8-bit wide 2-to-1 Multiplexer See Laboratory Exercise 1.doc

23-Oct-13 23 October 2013

14

Cc bc thit k

Hp knh 8-bit 2 li vo d liu

Hp knh 3-bit 5 li vo d liu

B cng Ripple-Carry Adder

Tng kt
23-Oct-13

Cc bc thit k
Thit k h thng s:
- Xc nh cc li vo-ra - M t trc tip hot ng ca h thng - Phn chia h thng thnh cc mch s n gin - 2 loi mch s: mch t hp v mch dy

15

Thit k mch t hp:

- Bng tr cc li vo-ra (bng chn l) - Lp phng trnh logic - Rt gn phng trnh (pp i s, Karnaugh )

Thit k mch dy:

- Xy dng hnh trng thi - Ti thiu ha trng thi - M t mch (hnh v, ngn ng HDL )
V d: cc mch m, b ghi dch, gim st d liu ni tip, cc mch iu khin dng my trng thi hu hn
(mch m & mch nh l cc mch dy n gin)

- M t mch (hnh v, ngn ng HDL )

V d: cc mch m ha, gii m, hp knh, phn knh, b cng, b so snh

23-Oct-13

16

Cc bc thit k

Hp knh 8-bit 2 li vo d liu

Hp knh 3-bit 5 li vo d liu

B cng Ripple-Carry Adder

Tng kt
23-Oct-13

17

LabEx1 Part1

m <= (NOT (s) AND x) OR (s AND y);

23-Oct-13

18

LabEx1 Part1
1. 2.

library ieee; use ieee.std_logic_1164.all;

entity mux8bit2to1 is port( <> ); end mux8bit2to1; architecture behavior of mux8bit2to1 is begin <> end behavior;

3. 4. 5. 6. 7.

8. 9. 10. 11.

23-Oct-13

19

LabEx1 Part1
1. 2.

architecture behavior of mux8bit2to1 is begin

3.

<>

4.

end behavior;

23-Oct-13

20

LabEx1 Part1
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

library ieee; use ieee.std_logic_1164.all; entity mux8bit2to1 is port( X,Y s M ); end mux8bit2to1;

: : :

in std_logic_vector(7 downto 0); in std_logic; out std_logic_vector(7 downto 0)

20.

architecture behavior of mux8bit2to1 is begin M(7) <= (NOT (s) AND X(7)) OR (s AND M(6) <= (NOT (s) AND X(6)) OR (s AND M(5) <= (NOT (s) AND X(5)) OR (s AND M(4) <= (NOT (s) AND X(4)) OR (s AND M(3) <= (NOT (s) AND X(3)) OR (s AND M(2) <= (NOT (s) AND X(2)) OR (s AND M(1) <= (NOT (s) AND X(1)) OR (s AND M(0) <= (NOT (s) AND X(0)) OR (s AND end behavior;

Y(7)); Y(6)); Y(5)); Y(4)); Y(3)); Y(2)); Y(1)); Y(0));

23-Oct-13

21

Cc bc thit k

Hp knh 8-bit 2 li vo d liu

Hp knh 3-bit 5 li vo d liu

B cng Ripple-Carry Adder

Tng kt
23-Oct-13

22

23-Oct-13

23

LabEx1 Part2

23-Oct-13

24

LabEx1 Part2
1. 2.

library ieee; use ieee.std_logic_1164.all;

3.
4. 5. 6. 7. 8.

9.

entity mux1bit5to1 is port( u,v,w,x,y : s2,s1,s0 : m : ); end mux1bit5to1;

in std_logic; in std_logic; out std_logic

m2

m0

m1

10. 11. 12. 13.

14.
15. 16. 17.

architecture behavior of mux1bit5to1 is signal m2,m1,m0: std_logic; begin m2 <= (NOT (s0) AND u) OR (s0 AND v); m1 <= (NOT (s0) AND w) OR (s0 AND x); m0 <= (NOT (s1) AND m2) OR (s1 AND m1); m <= (NOT (s2) AND m0) OR (s2 AND y); end behavior;
23-Oct-13

25

LabEx1 Part2
s0 s1 s2

U(2) V(2) W(2) X(2) Y(2) U(1) V(1) W(1) X(1) Y(1)

000 001 010 011 100

M(2)

000 001 010 011 100

M(1)

U(0) V(0) W(0) X(0) Y(0)

23-Oct-13

000 001 010 011 100

M(0)

26

LabEx1 Part2
1. 2. 3. 4. 5. 6. 7. 8.

library ieee; use ieee.std_logic_1164.all; entity mux3bit5to1 is port( U,V,W,X,Y : s2,s1,s0 : M : ); end mux3bit5to1;

in std_logic_vector(2 downto 0); in std_logic; out std_logic_vector(2 downto 0)

9.
10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22.

architecture structure of mux3bit5to1 is component mux1bit5to1 port( u,v,w,x,y : in std_logic; s2,s1,s0 : in std_logic; m : out std_logic ); end component; begin mux_2: mux1bit5to1 port map (U(2),V(2),W(2),X(2),Y(2),s2,s1,s0,M(2)); mux_1: mux1bit5to1 port map (U(1),V(1),W(1),X(1),Y(1),s2,s1,s0,M(1)); mux_0: mux1bit5to1 port map (U(0),V(0),W(0),X(0),Y(0),s2,s1,s0,M(0)); end structure;

23-Oct-13

27

Cc bc thit k

Hp knh 8-bit 2 li vo d liu

Hp knh 3-bit 5 li vo d liu

B cng Ripple-Carry Adder

Tng kt
23-Oct-13

28

LabEx2 Part1

23-Oct-13

29

LabEx2 Part1
1. 2.

library ieee; use ieee.std_logic_1164.all; entity full_adder is port( a,b,ci co,s ); end full_adder;

3. 4. 5. 6.

: :

in std_logic; out std_logic

7.
8.

9. 10. 11. 12. 13. 14. 15.

architecture behavior of full_adder is signal ab : std_logic; begin ab <= a xor b; s <= ab xor ci; co <= (NOT (ab) AND b) OR (ab AND ci); end behavior;
23-Oct-13

30

LabEx2 Part1
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

library ieee; use ieee.std_logic_1164.all; entity RCA_4bit is port( A,B : in std_logic_vector(3 downto 0); cin : in std_logic; cout : out std_logic; S : out std_logic_vector(3 downto 0) ); end RCA_4bit;

11. 12. 13.

14.
15. 16. 17. 18. 19.

architecture structure of RCA_4bit is signal c3,c2,c1 : std_logic; component full_adder port( a,b,ci : in std_logic; co,s : out std_logic ); end component; Begin -- <.>

23-Oct-13

31

LabEx2 Part1
19. 20. 21. 22.

begin FA_0: full_adder port map(

23.
24. 25. 26. 27. 28. 29. 30.

a => A(0), b => B(0), ci => cin, co => c1, s => S(0) a => A(1), b => B(1), ci => c1, co => c2, s => S(1) a => A(2), b => B(2), ci => c2, co => c3, s => S(2) a => A(3), b => B(3), ci => c3, co => cout, s => S(3)

); FA_1: full_adder port map (

31.
32. 33. 34. 35. 36. 37. 38.

); FA_2: full_adder port map (

); FA_3: full_adder port map (

39.
40. 41. 42. 43. 44.

); end structure;

23-Oct-13

32

LabEx2 Part2
B cng n bit (n-bit ripple carry adder circuit)

b(n-1) a(n-1) c(n-1)

b(2) a(2) c(2)

b(1) a(1) c(1)

b(0) a(0) C_in

FA

...

FA

FA

FA

C_out S(n-1)

S(2)

S(1)

S(0)

23-Oct-13

33

LabEx2 Part2
1. 2. 3. 4. 5. 6. 7. 8. 9.

library ieee; use ieee.std_logic_1164.all; entity RCA_Nbit is generic( N : integer := 4 ); port( A,B : in std_logic_vector(N-1 downto 0); cin : in std_logic; cout : out std_logic; S : out std_logic_vector(N-1 downto 0) end RCA_Nbit;

);

10.
11. 12. 13. 14. 15. 16.

17.
18. 19. 20. 21. 22.

architecture structure of RCA_Nbit is signal C : std_logic_vector(N downto 0); component full_adder port( a,b,ci : in std_logic; co,s : out std_logic ); end component; begin C(0) <= cin; RCAdder: for i in 0 to N-1 generate FA: full_adder port map (A(i),B(i),C(i),C(i+1),S(i)); end generate; cout <= C(N); end structure;

23-Oct-13

34

LabEx2 Part2
1. 2. 3. 4. 5.

6.
7. 8. 9. 10. 11.

entity RCA_8bit is port( A,B : cin : cout : S : end RCA_8bit;

in std_logic_vector(7 downto 0); in std_logic; out std_logic; out std_logic_vector(7 downto 0)

);

12.
13. 14. 15. 16. 17. 18. 19. 20. 21. 22.

architecture structure of RCA_8bit is component RCA_Nbit generic( N : integer := 4 ); port( A,B : in std_logic_vector(N-1 downto 0); cin : in std_logic; cout : out std_logic; S : out std_logic_vector(N-1 downto 0) end component; begin adder: RCA_Nbit generic map (N => 8) port map( A => A, B => B, cin => cin, cout => cout, S => S ); end structure;

);

23-Oct-13

35

Cc bc thit k

Hp knh 8-bit 2 li vo d liu

Hp knh 3-bit 5 li vo d liu

B cng Ripple-Carry Adder

Tng kt
23-Oct-13

36

Cng c phn mm (ModelSim): to project, vit file m t VHDL, bin dch, m phng Ngn ng VHDL: - cu trc mt file VHDL - C khi nim v entity, port, signal, component, generic - C php khai bo v s dng cc i tng trn - C php vng for generate Thit k cc mch s: mt vi mch T HP n gin (hp knh v b cng)

23-Oct-13

Bui thc hnh 2

37

Thit k mt s phn t nh, b m M phng trn ModelSim Thc thi cc mch t hp v mch dy thit k trn FPGA EP2C35F672C6 ca hng Altera

23-Oct-13

Thc thi cc mch trn FPGA

38

S dng phn mm Quartus ca hng Altera

To project Add cc file ngun VHDL Gn cc port ca entity top-level vi cc chn ca FPGA Bin dch-Tng hp Np chng trnh ln chip

23-Oct-13

39

LabEx0 Part1

Mch gii m 7 on: vi u vo l tn hiu biu din s nh phn 4 bit, u ra l cc m hin th LED 7 on vi Anode chung.
D(0)

D(5)
4

D(1) D(6)

BN (binary number)

Decoder

D (Display code) D(4)

D(2) D(3)

Thc hin np ln FPGA trn kit DE2 sao cho LED7 on HEX0 hin th gi tr s nh phn c cho bi cc cng tc SW3, SW2, SW1, SW0.

23-Oct-13

40

Bng chn l:
BN3 0 0 0 0 0 0 0 0 1 1 BN2 0 0 0 0 1 1 1 1 0 0 BN1 0 0 1 1 0 0 1 1 0 0 BN0 0 1 0 1 0 1 0 1 0 1 D6 1 1 0 0 0 0 0 1 0 0 D5 0 1 1 1 0 0 0 1 0 0 D4 0 1 0 1 1 1 0 1 0 1 D3 0 1 0 0 1 0 0 1 0 0 D2 0 0 1 0 0 0 0 0 0 0 D1 0 0 0 0 0 1 1 0 0 0 D0 0 1 0 0 1 0 0 0 0 0

1
1 1 1 1
23-Oct-13

0
0 1 1 1 1

1
1 0 0 1 1

0
1 0 1 0 1

0
0 1 0 0 0

0
0 0 1 0 0

0
0 0 0 0 0

1
0 0 0 0 1

0
0 1 0 1 1

0
1 1 0 1 1

0
1 0 1 0 0

41

LabEx0 Part1

C th vit 7 phng trnh logic m t mch gii m trn hoc vit on code sau: architecture simple of LED7seg_decoder is

1.

2.
3. 4. 5. 6. 7. 8. 9.

10.
11. 12. 13. 14. 15. 16. 17.

18.
19. 20. 21. 22. 23. 24. 25.

begin process(BN) begin case BN is when "0000" when "0001" when "0010" when "0011" when "0100" when "0101 when "0110" when "0111" when "1000" when "1001" when "1010 when "1011 when "1100 when "1101 when "1110 when "1111 when others end case; end process; end simple;

=> => => => => => => => => => => => => => => => =>

D <="1000000"; D <="1111001"; D <="0100100"; D <="0110000"; D <="0011001"; D <="0010010"; D <="0000010"; D <="1111000"; D <="0000000"; D <="0010000"; D <="0001000"; D <="0000011"; D <="1000110"; D <="0100001"; D <="0000110"; D <="0001110"; D <="1111111";

Combinational process: <optional_label>: process(<sensitivity_list>) -- Declaration(s) begin -- Sequential Statement(s) end process;

Sensitivity list: danh sch cc tn hiu m s thay i ca chng c nh hng ti mch (gy ra thay i trn li ra) Declaration: khai bo cc tn hiu v bin dng trong process Sequential statement: cc cu lnh tun t nh if, case, for loop,

23-Oct-13

42

LabEx0 Part1
To project (ch : tn project, tn file top-level.vhd, tn entity top-level phi ging nhau) File>New project wizard Chn th mc v t tn project

ng dn ti th mc cha project Tn project

23-Oct-13

43

LabEx0 Part1

Nu c file ngun VHDL, c th add vo project:

23-Oct-13

44

LabEx0 Part1

La chn Family CycloneII v tn FPGA l EP2C35F672C6

23-Oct-13

45

LabEx0 Part1

File>New to file VHDL mi Hoc Project>Add/Remove Files In Project add cc file VHDL vo project Processing>Start Complitation bin dch Trn kit DE2, cc chn ca FPGA c kt ni vi cc phn cng (nh cng tc SW, KEY, cc LED ) (xem file DE2_UserManual.pdf) mch s c thit k c th hot ng trn kit DE2, ta cn thc hin gn cc u vo v u ra ca mch vi cc chn tng ng ca FPGA. Trong bi ny cn gn cc port BN ca entity vi cc cng tc SW3, SW2, SW1, SW0 v cc li ra D c gn vi LED 7 on HEX0. Assignments > Assignment Editor thc hin gn chn Ti ca s Assignment Editor, chn Category l Pin (xem hnh slide sau)

23-Oct-13

46

LabEx0 Part1

Double Click vo <<new>> ct To la chn port cn gn sau la chn chn tng ng ca FPGA ct Location bn cnh (xem file DE2_UserManual.pdf)

23-Oct-13

47

LabEx0 Part1

Save file Assignment Editor nh sau:

Bin dch & tng hp li vi file gn chn

23-Oct-13

48

LabEx0 Part1

Tools>Programmer np vo FPGA: nh du vo program/configure ri chn Start

23-Oct-13

49

LabEx3 part1
Yu cu thit k 3 phn t nh: a. Cht D b. Flipflop hot ng theo sn ln c. Flipflop hot ng theo sn xung Qa c gi tr = D khi Clk=1 Khi Clk=0, Qa nh trng thi trc Qb ch nhn gi tr ca D ti thi im c sn ln ca Clk, sau gi tr ny c nh ti khi c sn ln tip theo trn Clk Qc tng t vi Qb nhng hot ng theo sn xung ca Clk
23-Oct-13

50

LabEx3 part1
1. 2.

library ieee; use ieee.std_logic_1164.all;

entity latch is port( D,Clk : in std_logic; Q,notQ : out std_logic ); end latch; architecture behavior of latch is begin process (D,Clk) begin if Clk ='1' then Q <= D; notQ <= not D; end if; end process; end behavior;

3. 4. 5. 6. 7. 8.

9. 10. 11. 12. 13. 14. 15. 16. 17. 18.

23-Oct-13

51

LabEx3 part1
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.

library ieee; use ieee.std_logic_1164.all; entity PE_FlipFlop is port( D,Clk : in std_logic; Q,notQ : out std_logic ); end PE_FlipFlop; architecture behavior of PE_FlipFlop is begin process (Clk) begin if Clk'event and Clk ='1' then -- if rising_edge(Clk) then Q <= D; notQ <= not D; end if; end process; end behavior;

Sequential process: <optional_label>: process(reset, clk) -- Declaration(s) begin if(reset = '1') then -- Asynchronous Sequential Statement(s) elsif(rising_edge(clk)) then -- Synchronous Sequential Statement(s) end if; end process; - Asynchronous Sequential Statement: cc lnh tun t hot ng khng theo clock (khng ng b/d b) - Synchronous Sequential Statement: cc lnh tun t hot ng theo clock (ng b)

23-Oct-13

52

LabEx3 part1
1. 2.

library ieee; use ieee.std_logic_1164.all;

entity NE_FlipFlop is port( D,Clk Q,notQ ); end NE_FlipFlop;

3. 4. 5. 6. 7. 8.

: :

in std_logic; out std_logic

9. 10. 11. 12. 13. 14. 15. 16. 17. 18.

architecture behavior of NE_FlipFlop is begin process (Clk) begin if Clk'event and Clk ='0' then -- if falling_edge(Clk) then Q <= D; notQ <= not D; end if; end process; end behavior;

23-Oct-13

53

LabEx3 part2

Thit k b m 16 bit c cu trc tng t b m 4 bit di y (gm cc flip-flop kiu T):

Cc flip-flop kiu T c dng: sau mi xung clock, nu en mc tch cc, clr khng tch cc gi tr li ra Q s b o so vi trc

en D

D-type flip-flop
clk clr

notQ

23-Oct-13

54

LabEx3 part2
1.

2.
3. 4. 5. 6. 7. 8.

library ieee; use ieee.std_logic_1164.all; entity D_FlipFlop is port( D,Clk,En,Rst Q,notQ : ); end D_FlipFlop; architecture behavior of D_FlipFlop is begin process (Clk) begin if Clk'event and Clk ='1' then -- if rising_edge(Clk) then if Rst = '0' then Q <= '0'; notQ <= '1'; elsif En = '1' then Q <= D; notQ <= not D; end if; end if; end process; end behavior; : in std_logic; out std_logic

9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23.

23-Oct-13

55

LabEx3 part2
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

library ieee; use ieee.std_logic_1164.all; entity T_FlipFlop is port( Clk,T,Rst : Q : ); end T_FlipFlop;

in std_logic; out std_logic

architecture structure of T_FlipFlop is component D_FlipFlop port( D,Clk,En,Rst : in std_logic; Q,notQ : out std_logic ); end component; signal notQ : std_logic; begin comp1: D_Flipflop port map (D => notQ, Clk => Clk, En => T, Rst => Rst, Q => Q, notQ => notQ); end structure;

23-Oct-13

56

LabEx3 part2
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

22.

library ieee; use ieee.std_logic_1164.all; entity Cntr_16bit is port( Clock,Enable,Clear : in std_logic; Count : out std_logic_vector(15 downto 0)); end Cntr_16bit; architecture structure of Cntr_16bit is component T_FlipFlop port( Clk,T,Rst : in std_logic; Q : out std_logic ); end component; signal En,Q : std_logic_vector(15 downto 0); Begin En(0) <= Enable; comp0: T_Flipflop port map (Clk => Clock, T => En(0), Rst => Clear, Q => Q(0)); Count(0) <= Q(0); generate_label: for i in 1 to 15 generate En(i) <= En(i-1) and Q(i-1); comp: T_Flipflop port map (Clk => Clock, T => En(i), Rst => Clear, Q => Q(i)); Count(i) <= Q(i); end generate; end structure;

23-Oct-13

57

LabEx0 Part2

Vi cc bc tng t trn, Part2 yu cu thit k mt mch s thc hin m s ln n cng tc KEY0 trn kit DE2 v hin th kt qu m c bng s nh phn 16 bit trn 4 LED 7 on HEX3, HEX2, HEX1, HEX0. Vic m ny ch c thc hin khi cng tc SW0 v SW1 c t bng 1. Nu SW0=0, b m b xa. Nu SW1=0 th khng m

23-Oct-13