Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-1

LECTURE 310 OPEN-LOOP COMPARATORS

LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop comparators Summary CMOS Analog Circuit Design, 2nd Edition Reference Pages 439-461

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-2

CHARACTERIZATION OF COMPARATORS What is a Comparator? The comparator is a circuit that compares one analog signal with another analog signal or a reference voltage and outputs a binary signal based on the comparison. The comparator is basically a 1-bit analog-to-digital converter:
Reference Voltage 1-Bit ADC Analog Input 1 1-Bit Digital Output Comparator 1-Bit Quantizer Analog Input 2
060808-01

1-Bit Encoder

Analog Input

1-Bit Quantizer

1-Bit Encoder

Comparator symbol:
vP vN
+ -

vO
Fig. 8.1-1

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-3

Noninverting and Inverting Comparators The comparator output is binary with the two-level outputs defined as, V OH = the high output of the comparator V OL = the low level output of the comparator Voltage transfer function of a Noninverting and Inverting Comparator:
vo VOH vP-vN VOL Noninverting Comparator VOH vP-vN VOL Inverting Comparator
Fig. 8.1-2A

vo

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-4

Infinite Gain Comparator Voltage transfer function curve:

vo VOH vP-vN VOL
Fig. 8.1-2

Model:
vP + vP-vN vN
-

f0(vP-vN)

+ vO
-

Comparator VOH for (vP-vN) > 0 f0(vP-vN) = VOL for (vP-vN) < 0

Fig. 8.1-3

V -V OH OL lim Gain = Av = where
V is the input voltage change
V
V  0

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-5

Finite Gain Comparator Voltage transfer curve:

VIL

vo VOH VIH VOL vP-vN

Fig. 8.1-4

where for a noninverting comparator, V IH = smallest input voltage at which the output voltage is VOH V IL = largest input voltage at which the output voltage is VOL Model:
vP + vP-vN vN
-

f1(vP-vN)

+ vO
-

V OH


VOL The voltage gain is Av = V IH


VIL

Comparator VOH for (vP-vN) > VIH f1(vP-vN) = Av(vP-vN) for VIL< (vP-vN)<VIH VOL for (vP-vN) < VIL Fig. 8.1-5

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-6

Input Offset Voltage of a Comparator Voltage transfer curve:

vo VOS VIL VIH VOL VOH vP-vN
Fig. 8.1-6

V OS = the input voltage necessary to make the output equal Model:

vP +vP' VOSv '-v ' P N vN
-v ' N

V OH+VOL when vP = vN. 2

f1(vP'-vN')

+ vO
Fig. 8.1-7

Comparator

Other aspects of the model: ICMR = input common mode voltage range (all transistors remain in saturation) Rin = input differential resistance Ricm = common mode input resistance
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-7

Comparator Noise Noise of a comparator is modeled as if the comparator were biased in the transition region.
vo Rms Noise VOH

Noise leads to an uncertainty in the transition region causing jitter or phase noise.

;;
vP-vN VOL Transition Uncertainty

Fig. 8.1-8

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-8

Input Common Mode Range Because the input is analog and normally differential, the input common mode range of the comparator is also important. Input common mode range (ICMR): ICMR = the voltage range over which the input common-mode signal can vary without influence the differential performance As we have seen before, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region.

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-9

Propagation Delay Time Rising propagation delay time:

vo VOH V +V vo = OH OL 2 VOL vi = vP-vN VIH tpr VIL V +V vi = IH IL 2 tpf t
070509-01

Propagation delay time = tpr
+
tpf = 2

Rising
propagation
delay
time
+
Falling
propagation
delay
time 2

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-10

Linear Frequency Response Dominant Single-Pole Model: Av(0) Av(0) Av(s) = s = s
c+1
+
1 c where Av(0) = dc voltage gain of the comparator 1 c =
c = -3dB frequency of the comparator or the magnitude of the pole Step Response: vo(t) = Av(0) [1 - e-t/
c]V in where V in = the magnitude of the step input. Maximum slope of the step response:
dvo(t) Av(0) -t/
dt =
c e cV in The maximum slope occurs at t = 0 giving,
dvo(t) | Av(0) =
c Vin dt t=0
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-11

Propagation Time Delay The rising propagation time delay for a single-pole comparator is: V OH-V OL   1 -t / c]V  p = A (0) [1 e
t =  ln v in p c 2 V OH
-V OL   1
-
2Av(0)Vin  Define the minimum input voltage to the comparator as, V OH
-VOL   1 V in(min) = A (0)
tp = c ln  V (min) v in   1-
2Vin  Define k as the ratio, Vin, to the minimum input voltage, Vin(min),  2k  V in   
tp = c ln  k = V in(min)  2k-1 Thus, if k = 1, tp = 0.693c. vout Illustration: Obviously, the more overdrive applied to the input, the smaller vin the propagation delay time.
VOH + -

Vin > Vin(min) VOH+VOL 2 Vin = Vin(min) t

Fig. 8.1-10

vout

VOL 0 t t (max) 0 p p

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-12

Dynamic Characteristics - Slew Rate of a Comparator If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by the slew rate. Slew rate comes from the relationship, dv i = C dt where i is the current through a capacitor and v is the voltage across it. If the current becomes limited, then the voltage rate becomes limited. Therefore for a comparator that is slew rate limited we have,
V V OH-
V OL tp =
T = SR = 2SR where SR = slew rate of the comparator. If SR < |maximum slope|, then the comparator is slewing.

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-13

Example 310-1 - Propagation Delay Time of a Comparator Find the propagation delay time of an open loop comparator that has a dominant pole at 103 radians/sec, a dc gain of 104, a slew rate of 1V/s, and a binary output voltage swing of 1V. Assume the applied input voltage is 10mV. Solution The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV input is 100 times larger than vin(min) giving a k of 100. Therefore, we get 
200 1
 2100     = 10-3 ln  tp = 103 ln  2100-1  199 = 5.01s For slew rate considerations, we get 104 Maximum slope = -3 10mV = 105 V/sec. = 0.1V/s. 10 Therefore, the propagation delay time for this case is limited by the linear response and is 5.01s.

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-14

DOMINANT POLE, OPEN-LOOP COMPARATORS Dominant Pole Comparators Any of the self-compensated op amps provide a straight-forward implementation of an open loop comparator without any modification. The previous characterization gives the relationships for: 1.) The static characteristics Gain Input offset Noise 2.) The dynamic characteristics Linear frequency response Slew rate response

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-15

Single-Stage Dominant Pole Comparator

VDD M3 M4

VPBias2

MC3

MC4 CL

vo

vp

MC1 M1 VBias
-

MC2
M2 v n

+ VNBias1 -

M5
060808-02

Gain  gm2rds2 Slew rate = I5/CL Dominant pole = -1/(RoutCL) = -1/(gmrds2CL)

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-16

Folded-Cascode Comparator
VDD VPB1 M4 VPB2 vP vN VNB1 M1 M2 M8 M3 I3 M10 M6 VNB2 M7 M9 M11
060808-03

M5

vOUT CL

Gain  gm2rds2 Slew rate = I3/CL Dominant pole = -1/(RoutCL)  -1/(gmrds2CL) Slightly improved ICMR
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-17

Enhanced-Gain, Folded-Cascode Comparator

VDD M10 VPB1 vP M8 vN M1 M2 M6 -A -A M7 M3 -A M9 vOUT CL M11

VNB1

M4

M5
060808-04

Gain  gm1Rout Rout  [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11) Slew rate = I3/CL Dominant pole = -1/(RoutCL)
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-18

TWO-POLE, OPEN-LOOP COMPARATORS Two-Stage Comparator The two-stage op amp without compensation is an excellent implementation of a high-gain, open-loop comparator.
VDD

M3
vn

M4

M6
vout

M1
vp + VNB1 -

M2

CL
M5 M7
060808-05

Much faster linear response the two poles of the comparator are typically much larger than the dominant pole of the self-compensated type of comparator. Be careful not to close the loop because the amplifier is uncompensated. I7 I6-I7 Slew rate: SR- = CII and SR+ = CII
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-19

Performance of the Two-Stage, Open-Loop Comparator We know the performance should be similar to the uncompensated two-stage op amp. Emphasis on comparator performance: Maximum output voltage   8 I7  V OH = VDD - (VDD-V G6(min)-|VTP|)1
-
1
-

(V -V (min)-|V |)2
 6 DD G6 TP Minimum output voltage V OL = VSS Small-signal voltage gain   gm1  gm6 

 
 Av(0) =
 gds2+gds4  gds6+gds7 Poles -(gds2+gds4) CI Frequency response Av(0) Av(s) =   
s 
s 


-
1 p2
-
1  p1 p1 =
CMOS Analog Circuit Design

Input:

Output: p2 =

-(gds6+gds7) CII

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-20

Example 310-1 - Performance of a Two-Stage Comparator Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, VDD = 2.5V M3 M4 M6 for the two-stage comparator shown. The 15m 15m 94m 1m 1m 1m large signal model parameters are KN = 2 2 vout 110A/V , KP = 50A/V , VTN = |VTP| = 30A M1 M2 CI = 0.2pF 3m 3m CII = 5p 1m 1m 0.7V,
N = 0.04V-1 and
P = 0.05V-1. 95A vin + Assume that the minimum value of VG6 = 30A 0V and that CI = 0.2pF and CII = 5pF. 4.5m 14m 1m 4.5m 1m M5 M8 M7 1m Solution VSS = -2.5V Using the above relations, we find that   8234x10-6  V OH = 2.5 - (2.5-0-0.7) 1
-
1
-
50x10-638(2.5-0-0.7)2
  = 2.2V V OL is -2.5V. The gain can be found as Av (0) = 7696. Therefore, the input resolution is V in(min) = (VOH-V OL/Av (0) = 4.7V/7,696 = 0.611mV Next, we find the poles of the comparator, p1 and p2. p1 = -(gds2 + gds4)/CI = 15x10-6(0.04+0.05)/0.2x10-12 = -6.75x106 (1.074MHz) and
070509-02

p2 = -(gds6 + gds7)/CII) =(95x10-6)(0.04+0.05)/5x10-12 = -1.71x106 (0.272MHz)

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-21

Linear Step Response of the Two-Stage Comparator The step response of a circuit with two real poles (p1
p2) is, p2etp1 p1etp2  vout(t) = Av(0)V 1
+
p -p
-
p -p  1 2 1 2 Normalizing gives, p2 vout(t) m 1 vout(tn ) = Av(0)Vin = 1 - m-1e-tn + m-1e-mtn where m = p1
1 and If p1 = p2 (m =1), then
1
   in

tn = -tp1

vout(tn) = 1 - etp1 + tp1etp1 = 1 - e-tn - tne-tn

m=4

Normalized Output Voltage

0.8 0.6 0.4 0.2 0

m=2

m = 1 m = 0.5

m = 0.25

p2 m= p 1

2 4 6 Normalized Time (tn = -tp1 )

10
Fig. 8.2-2

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-22

Linear Step Response of the Two-Stage Comparator - Continued The above results are valid as long as the slope of the linear response does not exceed the slew rate. Slope at t = 0 is zero Maximum slope occurs at (m
1) ln(m) tn(max) = m-1 and is  -ln(m)   dvout(tn(max)) m  ln(m)      exp
-
exp -m  =  dtn m-1  m-1
m-1
 For the two-stage comparator using NMOS input transistors, the slew rate is I7 SR- = CII I6-I7 0.56(VDD-V G6(min)-|VTP|)2
-
I7 + SR = CII = CII

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-23

Example 310-2 - Step Response of Ex. 310-1 Find the maximum slope of Ex. 310-1 and the time it occurs if the magnitude of the input step is v in(min). If the dc bias current in M7 is 100A, at what value of load capacitance, CL would the transient response become slew limited? If the magnitude of the input step is 100vin(min), what is the new value of CL at which slewing would occur? Solution The poles of the comparator were given in Ex. 310-1 as p1 = -6.75x106 rads/sec. and p2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous expressions, the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p 1| gives t(max) = 0.272s. The slope of the transient response at this time is found as dvout(tn(max)) = -0.338[exp(-1.84) - exp(-0.2531.84)] = 0.159 V/sec dtn Multiplying the above by |p1| gives dvout(t(max))/dt = 1.072V/s. If the slew rate is less than 1.072V/s, the transient response will experience slewing. Therefore, if CL
100A/1.072V/s or 93.3pF, the comparator will slew. If the input is 100vin(min), then we must unnormalize the output slope as follows. vin dvout(t(max)) dvout(t(max)) = = 1001.072V/s = 107.2V/s dt vin(min) dt Therefore, the comparator will slew with a load capacitance greater than 0.933pF.
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-24

Propagation Delay Time (Non-Slew) To find tp, we want to set 0.5(VOH-V OL) equal to vout(tn). However, vout(tn) given as   m 1  -t -mt  vout(tn) = Av(0)Vin 1
-
m-1e n
+
m-1e n  cant be easily solved so approximate the step response as a power series to get      tn2 m2tn2  mtn2Av(0)Vin    m
1


 vout(tn)
Av(0)Vin1
-
m-11-tn+
2
+

+
m-11-mtn+
2
+ 
2 Therefore, set vout(tn) = 0.5(VOH-V OL) V OH-V OL mtpn2Av(0)Vin
2 2 or V in(min) 1 = mVin mk This approximation is particularly good for large values of k. tpn
V OH-V OL mAv(0)Vin =

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-25

Example 310-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew) Find the propagation time delay of Ex. 310-1 if Vin = 10mV, 100mV and 1V. Solution From Ex. 310-1 we know that Vin(min) = 0.611mV and m 1 m=4 = 0.253. For Vin = 10mV, k = 16.366 which gives tpn
0.491. 0.8 m=2 m = 1 m = 0.5 The propagation time delay is m = 0.25 equal to 0.491/6.75x106 or 0.6 72.9nS. This corresponds well with the figure shown where 0.4 the normalized propagation p2 m= p time delay is the time at which 1 0.2 the amplitude is 1/2k or 0.031 which corresponds to tpn of 1 approximately 0.5. Similarly, 2k = 0.0310 0 2 4 6 8 10 for Vin = 100mV and 1V we get 0.52 Normalized Time (tn = tp1 = t/1) a propagation time delay of tp = 0.52 = 77ns Fig. 8.2-2A 6.75x106 23ns and 7.3ns, respectively.
Normalized Output Voltage

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-26

Initial Operating States for the Two-Stage, Open-Loop Comparator What are the initial operating states for the two-stage, open-loop comparator? The following table summarizes the results for the two-stage, open-loop comparator shown.
Conditions
vG1>VG2, i1<ISS and i2>0 vG1>>VG2, i1=ISS and i2=0 vG1<VG2, i1>0 and i2<ISS vG1<<VG2, i1>0 and i2<ISS vG2>VG1, i1>0 and i2<ISS vG2>>VG1, i1>0 and i2<ISS vG2<VG1, i1<ISS and i2>0 vG2<<VG1, i1=ISS and i2=0

Initial State of vo1

VDD-VSD4(sat) < vo1 < VDD VDD vo1=VG2-VGS2,act(ISS/2),
VSS if M5 act. VSS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) VG1-VGS1(ISS/2) ,
VSS if M5 active VDD-VSD4(sat) < vo1 < VDD VDD

Initial State of vout

VSS VSS see equation below tabl see equation below tabl see equation below tabl see equation below tabl VSS VSS

VOH VOH VOH VOH

VDD

VOH = VDD (VDD-VG6(min)-|VTP|)  x1
-
   1
-

6(VDD-VG6(min)-|VTP|)2  8I7

vG1

i3
M3

i4 M4 vo1 i2
M2

M6

i1
M1
+ VBias -

CI
vG2 vout

CII ISS
M5 VSS M7
Fig. 8.2-3

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-27

Trip Point of an Inverter In order to determine the propagation delay time, it is necessary to know when the second stage of the two-stage comparator begins to turn on. Second stage: Trip point: VBias Assume that M6 and M7 are saturated. (We know that the steepest slope occurs for this condition.) Equate i6 to i7 and solve for vin which becomes the trip point.

VDD
+ vin -

M6 i6
i7 M7

vout

VSS

Fig. 8.2-4

vin = VTRP = VDD - |VTP| -

KN(W 7/L7) KP(W 6/L6) (VBias- VSS -VTN)

Example: If W7/L7 = W 6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the circuit above is V TRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-28

Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator Previously we calculated the propagation delay time for a nonslewing comparator. If the comparator slews, then the propagation delay time is found from dvi
vi ii = Ci dti = Ci
ti where Ci is the capacitance to ground at the output of the i-th stage The propagation delay time of the i-th stage is,
Vi ti =
ti = Ci Ii The propagation delay time is found by summing the delays of each stage. tp = t1 + t2 + t3 +

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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-29

Example 310-4 - Propagation Time Delay of a Two-Stage, Open-Loop Comparator VDD = 2.5V For the two-stage comparator shown M6 M3 M4 assume that C I = 0.2pF and C II = 5pF. 4.5m 4.5m 38m 1m 1m Also, assume that vG1 = 0V and that vG2 1m vo1 vout has the waveform shown. If the input voltage is large enough to cause slew to 30A CI = M2 vG1 M1 3m 3m CII = 0.2pF dominate, find the propagation time delay 1m 1m 5pF of the rising and falling output of the vG2 234 A comparator and give the propagation time 30A delay of the comparator. 4.5m 35m
vG2

1m

2.5V 0V -2.5V 0 0.2 0.4 0.6 t(s)

Fig. 8.2-5

M8

4.5m M5 1m VSS = -2.5V

M7

1m

Fig. 8.2-5A

Solution 1.) Total delay = sum of the first and second stage delays, t1 and t2 2.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2s. The last row of table on Slide 310-28 gives vo1 = +2.5V and vout = -2.5V 3.) tf1, requires CI,
Vo1, and I5. CI = 0.2pF, I5 = 30A and
V1 can be calculated by finding the trip point of the output stage.
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Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-30

Example 310-4 - Continued 4.) The trip point of the output stage by setting the current of M6 when saturated equal to 234A. 2342 2 (VSG6-|VTP|)2 = 234A  VSG6 = 0.7 + 5038 = 1.196V Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V Therefore, V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation time delay of the first stage is  1.196V

tfo1 = 0.2pF  30A  = 8 ns 5.) The rising propagation time delay of the second stage requires CII, Vout, and I6. CII is given as 5pF,  V out = 2.5V (assuming the trip point of the circuit connected to the output of the comparator is 0V), and I6 can be found as follows: V G6(guess)
0.5[VG6(I6=234A) + VG6(min)]
6

V G6(min) = VG1 - VGS1(ISS/2) + VDS2
-VGS1(ISS/2) = -0.7 V G6(guess)
0.5(1.304V-1.00V) = 0.152V Therefore VSG6 = 2.348V and I6 = 2 (VSG6-|VTP|)2 =
CMOS Analog Circuit Design

215 1103 = -1.00V

6

3850 2 (2.348 - 0.7)2 = 2,580A

P.E. Allen - 2010

Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-31

Example 310-4 - Continued 6.) The rising propagation time delay for the output can expressed as   2.5V    trout = 5pF   2580A-234A = 5.3 ns Thus the total propagation time delay of the rising output of the comparator is approximately 13.3 ns and most of this delay is attributable to the first stage. 7.) Next consider the change of vG2 from 2.5V to -2.5V at 0.4s. We shall assume that vG2 has been at 2.5V long enough for the conditions of the table on Slide 310-28 to be valid. Therefore, vo1
V SS = -2.5V and vout
V DD. The propagation time delays for the first and second stages are calculated as 3V  1.304V-(-1.00V)   vout   tro1 = 0.2pF   = 15.4 ns 30A
2V 1V 0V -1V -2V vo1

2.5V   tfout = 5pF 234A  = 53.42ns 8.) The total propagation time delay of the falling output is 68.82 ns. Taking the average of the rising and falling propagation time delays gives a propagation time delay for this two-stage, open-loop comparator of about 41.06ns.
    CMOS Analog Circuit Design

VTRP6 = 1.304V

Rising prop. delay time -3V 200ns 300ns

Falling prop. delay time

400ns Time 500ns 600ns
Fig. 8.2-6

P.E. Allen - 2010

Lecture 310 Open-Loop Comparators (3/28/10)

Page 310-32

SUMMARY The two-stage, open-loop comparator has two poles which should as large as possible The transient response of a two-stage, open-loop comparator will be limited by either the bandwidth or the slew rate It is important to know the initial states of a two-stage, open-loop comparator when finding the propagation delay time If the comparator is gainbandwidth limited then the poles should be as large as possible for minimum propagation delay time If the comparator is slew rate limited, then the current sinking and sourcing ability should be as large as possible

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