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IEEE-2013 1. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes IEEE-2012 2. ACCUMULATOR BASED 3-WEIGHT PATTERN GENERATION 3. ALU BASED ADDRESS GENERATION FOR RAMS 4. AN AREA-EFFICIENT CARRY SELECT ADDER DESIGN BY SHARING THE COMMON BOOLEAN LOGIC TERM 5. AN IMPLEMENTATION OF AES ALGORITHM BASED ON FPGA 6. DESIGN OF AN ERROR DETECTION AND DATA RECOVERY ARCHITECTURE FOR MOTION ESTIMATION TESTING APPLICATIONS 7. FPGA IMPLEMENTATION OF BINARY CODED DECIMAL DIGIT ADDERS AND MULTIPLIERS 8. HIGH SPEED SIGNED MULTIPLIER FOR DIGITAL SIGNAL PROCESSING APPLICATIONS 9. IMPLEMENTATION OF BISTCONTROLLER FOR FAULT DETECTION IN CLB OF FPGA 10. IMPROVED TRACE BUFFER OBSERVATION VIA SELECTIVE DATA CAPTURE USING 2-D COMPACTION FOR POST-SILICON DEBUG

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11. LOW-COMPLEXITY RELIABILITY-BASED MESSAGE-PASSING DECODER ARCHITECTURES FOR NON-BINARY LDPC CODES 12. LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER 13. OPTIMIZING MEMORY BIST ADDRESS GENERATOR IMPLEMENTATIONS 14. SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST 15. DESIGN AND IMPLEMENTATION OF CPLD BASED SOLAR POWER SAVING SYSTEM FOR STREET LIGHTS AND AUTOMATIC TRAFFIC CONTROLLER IEEE-2011 16. 16-BIT RISC PROCESSOR DESIGN FOR CONVOLUTION APPLICATION 17. BIST-BASED FAULT DIAGNOSIS FOR READ-ONLY MEMORIES 18. CONFIGURABLE ARCHITECTURE FOR MEMORY BIST 19. DISTRIBUTED ARITHMETIC FOR FIR FILTER IMPLEMENTATION ON FPGA