----------------------------------------------------------//tff.

v
module tff1(clk,t,q,qb);
input clk,t;
output q,qb;
reg q,qb;
initial
begin
q=1'b0;
qb=~q;
end
always @(posedge clk )
begin
if(t)
begin
q=~q;
qb=~q;
end
else
begin
q=0;
qb=~q;
end
end
endmodule
----------------------------------------------------------//rsff.v
module rs1( rs , clk , reset , q ,qb );
input [1:0] rs;
input clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk )
begin
if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
if (s==1'b0 & r==1'b0)
q=1'b0;
else if (s==1'b0 & r==1'b1)
q=1'b0;
else if (s==1'b1 & r==1'b0)
q=1'b1;
else if(s==1'b1 & r==1'b1)
q=1'bz;
end
qb = ~q;
end
endmodule
-----------------------------------------------------------//dff.v
module d_ff( d , clk , q ,qb );

input d, clk ;
output q,qb;
reg q,qb;
initial
begin
q=1'b0;
qb=~q;
end
always @ ( posedge clk )
if (d)
begin
q = d;
qb=~q;
end
else
begin
q = 1'b0;
qb=~q;
end
endmodule
--------------------------------------------------------------//jkff.v
module jk_ff( j,k , clk , reset , q ,qb );
input j,k,clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk )
begin
if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
if (j==1'b0 & k==1'b0)
q=1'b0;
else if (j==1'b0 & k==1'b1)
q=1'b0;
else if (j==1'b1 & k==1'b0)
q=1'b1;
else if(j==1'b1 & k==1'b1)
q=~q;
end
qb = ~q;
end
end
endmodule
--------------------------------------------------------------------//msff.v(while writing you shld write dff prg)
module ms_ff(ms,clk,rst,q,qb);
input m,s,clk,rst;
output q,qb;
wire temp1,temp2,temp3;
assign temp1=~clk;
d_ff f1 (.clk(clk),.rst(rst),.j(m),.k(s),.q(temp2),.qb(temp3));
d_ff f2 (.clk(temp1),.rst(rst),.j(temp2),.k(temp3),.q(q),.qb(qb));
endmodule
----------------------------------------------------------------------

//bincount.v
module bincnt(clk,count,rst);
input clk,rst;
output [3:0] count;
reg [3:0] count;
always@(posedge clk or posedge rst)
begin
if(rst)
count=4'b0000;
else
count=count+4'b0001;
end
endmodule
---------------------------------------------------------------------//binasync.v
module binasync(clk,rst,count);
input clk,rst;
output count;
reg count;
always@(posedge clk or posedge rst)
begin
if(rst)
count=4'b0000;
else
count=count+4'b0001;
end
endmodule