ABSTRACT

Regulators are an essential part of any electrically powered system, which includes the growing family of applications of portable battery operated products. LDO regulators are widely used in present electronic industry, since they are one of the subsystems of the power management unit. LDO is used to protect the sensitive analog blocks from coupled supply noise, thus its Power Supply Rejection Ratio (PSRR) performance must be high. Moreover the low voltage supply and low quiescent current are a requirement, since they determine the battery life. Commonly LDO have a limited operation range of load current due to their stability problems. So, in order to solve the stability problems and increase the PSRR performance of the LDO, with high power efficiency and low quiescent current, a novel technique is presented. The stability is achieved by the following techniques such as pole-splitting and feedforward. LDO regulator will be designed under 180nm technology with an input voltage of 3.3V, output voltage of 2.4V, maximum load current of 10mA, load capacitance 1pF, reference voltage 1.2V, Power Supply Rejection Ration (PSRR) -60dB @10kHz, load regulation 1%, line regulation 1%, quiescent current of 100A-150 A, dropout voltage of 0.1V to 0.15V or less. Few topologies such as LDO regulator with CMOS topology, mixed mode technique and different pass device structures are also implemented and the results are simulated and compared.