--------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 12:39:16 11/14/2013 -- Design Name: -- Module Name: multiplir - Behavioral -- Project

Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity multiplir is Port ( mpcd : in STD_LOGIC_VECTOR (7 downto 0); mlpr : in STD_LOGIC_VECTOR (7 downto 0); result : out STD_LOGIC_VECTOR (15 downto 0); asign : out STD_LOGIC; bsign : out STD_LOGIC; clk : in std_logic ); end multiplir; architecture Behavioral of multiplir is begin process(clk) variable b : std_logic_vector(7 downto 0); variable q : std_logic_vector(7 downto 0); variable as : std_logic; variable ref: std_logic_vector(7 downto 0); variable bs : std_logic; variable ac : std_logic_vector(15 downto 0); variable e : std_logic; begin if(clk'event and clk='1') then ac(7 downto 0) := mlpr; b := mpcd; as := ac(7) xor b(7); ac(7) :=ac(7) xor b(7); ac(14 downto 8) := (others => '0') ; e :='0';

loop1 :for i in 7 downto 0 loop if (ac(0)= '0') then ac(15) := e; ac(14 downto 0) :=ac(15 downto 1); elsif(ac(0)='1') then ref := ac(15 to 8) + b; ac(15 downto 8) := ref; ac(15) := e; ac(14 downto 0) :=ac(15 downto 1); end if; end loop loop1; result <= ac; asign <= as; bsign <= bs; end if; end process; end Behavioral;