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Manual Lite
Manual Lite
Etienne Sicard
<ni2>
14/03/04
1. Introduction
Copyright
Copyright 1997-2004 by INSA, licensed to <ni2>
About <ni2design>
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14/03/04
1. Introduction
Table of Contents
1 2
INSTALLATION ............................................................................................................................................... 7
The MOS device.................................................................................................................................... 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Logic Levels ................................................................................................................................................ 8 The MOS as a switch................................................................................................................................... 8 MOS layout.................................................................................................................................................. 9 Vertical aspect of the MOS........................................................................................................................ 10 Static Mos Characteristics ......................................................................................................................... 11 Dynamic MOS behavior ............................................................................................................................ 11 Analog Simulation ..................................................................................................................................... 12 Layout considerations................................................................................................................................ 13 The MOS Models ...................................................................................................................................... 14 The PMOS Transistor ................................................................................................................................ 16 The Transmission Gate .............................................................................................................................. 17 Features in the full version ........................................................................................................................ 18 The Logic Inverter ..................................................................................................................................... 19 THE CMOS INVERTER .......................................................................................................................... 20 MANUAL LAYOUT OF THE INVERTER............................................................................................ 21 Connection between Devices..................................................................................................................... 21 Useful Editing Tools.................................................................................................................................. 22 Metal-to-poly ............................................................................................................................................. 23 Supply Connections................................................................................................................................... 24 Process steps to build the Inverter ............................................................................................................. 25 Inverter Simulation .................................................................................................................................... 25 Added Features in the Full version ............................................................................................................ 26 Introduction ............................................................................................................................................... 27 The Nand Gate........................................................................................................................................... 27 The AND gate............................................................................................................................................ 29 The XOR Gate ........................................................................................................................................... 29 Multiplexor ................................................................................................................................................ 31 Interconnects.............................................................................................................................................. 32 Added Features in the Full version ............................................................................................................ 33 Unsigned Integer format ............................................................................................................................ 34 Half-Adder Gate ........................................................................................................................................ 34 Full-Adder Gate ......................................................................................................................................... 36 Full-Adder Symbol in DSCH3.................................................................................................................... 36 Comparator ................................................................................................................................................ 37 Micro-controller Models............................................................................................................................ 38 Added Features in the Full version ............................................................................................................ 39
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Basic Gates.......................................................................................................................................... 27
4.1 4.2 4.3 4.4 4.5 4.6 4.7
Arithmetics.......................................................................................................................................... 34
5.1 5.2 5.3 5.4 5.5 5.6 5.7
1. Introduction
Latches ................................................................................................................................................ 40
6.1 6.2 6.3 6.4 Basic Latch ................................................................................................................................................ 40 RS Latch .................................................................................................................................................... 40 Edge Trigged Latch ................................................................................................................................... 43 Added Features in the Full version ............................................................................................................ 45 Main structure............................................................................................................................................ 46 RAM Memory ........................................................................................................................................... 46 Selection Circuits....................................................................................................................................... 49 A Complete 64 bit SRAM ......................................................................................................................... 51 Dynamic RAM Memory............................................................................................................................ 52 EEPROM ................................................................................................................................................... 53 Flash Memories ......................................................................................................................................... 54 Memory Interface ...................................................................................................................................... 56 Added Features in the Full version ............................................................................................................ 56 Resistor ...................................................................................................................................................... 58 Capacitor.................................................................................................................................................... 60 Poly-Poly2 Capacitor................................................................................................................................. 61 Diode-connected MOS .............................................................................................................................. 62 Voltage Reference ..................................................................................................................................... 63 Amplifier ................................................................................................................................................... 64 Simple Differential Amplifier.................................................................................................................... 66 Added Features in the Full version ............................................................................................................ 68 On-Chip Inductors ..................................................................................................................................... 69 Power Amplifier ........................................................................................................................................ 71 Oscillator ................................................................................................................................................... 73 Phase-lock-loop ......................................................................................................................................... 75 Analog to digital and digital to analog converters..................................................................................... 78 Added Features in the Full version ............................................................................................................ 82
Analog Cells........................................................................................................................................ 58
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8
10
10.1 10.2 10.3 10.4 10.5 10.6 10.7
Input/Output Interfacing................................................................................................................ 83
The Bonding Pad ....................................................................................................................................... 83 The Pad ring............................................................................................................................................... 84 The supply rails ......................................................................................................................................... 84 Input Structures.......................................................................................................................................... 85 High voltage MOS..................................................................................................................................... 87 Level shifter ............................................................................................................................................... 88 Added Features in the Full version ............................................................................................................ 90
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11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11
4
1. Introduction
Via 2 ...................................................................................................................................................... 94 Metal 3................................................................................................................................................... 94 Via 3 ...................................................................................................................................................... 94 Metal 4................................................................................................................................................... 94 Via 4 ...................................................................................................................................................... 94 Metal 5................................................................................................................................................... 95 Via 5 ...................................................................................................................................................... 95 Metal 6................................................................................................................................................... 95 Pads........................................................................................................................................................ 95 FILE MENU .............................................................................................................................................. 96 VIEW MENU ............................................................................................................................................ 96 EDIT MENU ............................................................................................................................................. 96 SIMULATE MENU .................................................................................................................................. 97 COMPILE MENU ..................................................................................................................................... 97 ANALYSIS MENU................................................................................................................................... 97 PALETTE .................................................................................................................................................. 97 NAVIGATOR WINDOW ......................................................................................................................... 98 MICROWIND3 SIMULATION MENU................................................................................................... 98 DSCH3 MENUS.................................................................................................................................... 99 EDIT MENU ......................................................................................................................................... 99 INSERT MENU..................................................................................................................................... 99 VIEW MENU ...................................................................................................................................... 100 SIMULATE MENU ............................................................................................................................ 100 SYMBOL PALETTE .......................................................................................................................... 100
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12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15
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1. Introduction
The DSCH3 program is a logic editor and simulator. DSCH3 is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH3 provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures. Some techniques for low power design are described in the manual. DSCH3 also features the symbols, models and assembly support for 8051 and 18f64. DSCH3 also includes an interface to SPICE.
About Microwind3
The MICROWIND3program allows the student to design and simulate an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to view and simulate. MICROWIND3includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, Verilog compiler, tutorial on MOS devices). You can gain access to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately.
The chapters of this manual have been summarized below. Chapter 2 is dedicated to the presentation of the single MOS device, with details on the device modeling, simulation at logic and layout levels.
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1. Introduction
Chapter 3 presents the CMOS Inverter, the 2D and 3D views, the comparative design in micron and deepsubmicron technologies. Chapter 4 concerns the basic logic gates (AND, OR, XOR, complex gates), Chapter 5 the arithmetic functions (Adder, comparator, multiplier, ALU). The latches and memories are detailed in Chapter 6. As for Chapter 7, analog cells are presented, including voltage references, current mirrors, operational amplifiers and phase lock loops. Chapter 8 concerns analog-to-digital, digital to analog converter principles. and radio-frequency circuit. The input/output interfacing principles are illustrated in Chapter 9. The detailed explanation of the design rules is in Chapter 10. The program operation and the details of all commands are given in the help files of the programs.
INSTALLATION
From The web
Connect to page <ni2> Click <ni2> Click <ni2> Test: double-click MICROWIND3.EXE. Click "File ->Load", select "CMOS.msk". Click "Simulate". Click <ni2> Extract all files in the selected directory. Test: double click in DSCH3.EXE. Load "base.sch". Click "Simulate".
C:\Program Files\
Microwind3 Executable (.EXE) Examples (.MSK) Rule files (.RUL) Executable (.EXE) Exemples (.SCH)
Dsch3
HTML
IEEE
HTML
Help on line
Symbols of Dsch3
Help on line
Once installed, two directories are created, one for MICROWIND3, one for DSCH3. In each directory, a subdirectory called html contains help files.
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2.1
Logic Levels Three logic levels 0,1 and X are defined as follows:
Logical value 0 Voltage 0.0V Name VSS Symbol in DSCH3 Symbol in MICROWIND3 (Green in simulation) analog
logic
Undefined
(Red in analog simulation) (Red in logic simulation) (Gray in simulation) (Gray in simulation)
2.2
The MOS as a switch The MOS transistor is basically a switch. When used in logic cell design, it can be on or off. When on, a current can flow between drain and source. When off, no current flow between drain and source. The MOS is turned on or off depending on the gate voltage. In CMOS technology, both n-channel (or nMOS) and pchannel MOS (or pMOS) devices exist. The nMOS and pMOS symbols are reported below. The symbols for the ground voltage source (0 or VSS) and the supply (1 or VDD) are also reported in figure 2-1.
The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In contrary, the p-channel MOS device requires a logic value 0 to be on. When the MSO device is on, the link between the source and
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drain is equivalent to a resistance. The order of range of this on resistance is 100-5K. The off resistance is considered infinite at first order, as its value is several M.
2.3
MOS layout We use MICROWIND3 to draw the MOS layout and simulate its behavior. Go to the directory in which the software has been copied (By default microwind3). Double-click on the MicroWind3 icon. The MICROWIND3 display window includes four main windows: the main menu, the layout display window, the icon menu and the layer palette. The layout window features a grid, scaled in lambda () units. The lambda unit is fixed to half of the minimum available lithography of the technology. The default technology is a CMOS 6-metal layers 0.12m technology, consequently lambda is 0.06m (60nm).
The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. By using the following procedure, you can create a manual design of the n-channel MOS. Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box. Release the button. This creates a box in polysilicon layer as shown in Figure 2-3. The box width should not be inferior to 2 , which is the minimum width of the polysilicon box. Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 2-3. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device.
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2.4
Click on this icon to access process simulation (Command Simulate Process section in 2D). The crosssection is given by a click of the mouse at the first point and the release of the mouse at the second point.
Interlayer oxide Gate Field oxide Lateral drain diffusion Source Drain
In the example of Figure 2-4, three nodes appear in the cross-section of the n-channel MOS device: the gate (red), the left diffusion called source (green) and the right diffusion called drain (green), over a substrate (gray). A thin oxide called the gate oxide isolates the gate. Various steps of oxidation have lead to stacked oxides on the top of the gate. The physical properties of the source and of the drain are exactly the same. Theoretically, the source is the origin of channel impurities. In the case of this nMOS device, the channel impurities are the electrons. Therefore, the source is the diffusion area with the lowest voltage. The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and the drain. The gate controls the current flow from the drain to the source, both ways. A high voltage on the gate attracts electrons below the gate, creates an electron channel and enables current to flow. A low voltage disables the channel.
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2.5
Click on the MOS characteristics icon. The screen shown in Figure 2-5 appears. It represents the Id/Vd static characteristics of the nMOS device.
The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. In Figure 2-5, the MOS width is 1.74m and the length is 0.12m. A high gate voltage (Vg =1.2V) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. You may change the voltage values of Vd, Vg, Vs by using the voltage cursors situated on the right side of the window. A maximum current around 1.5mA is obtained for Vg=1.2V, Vd=1.2V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3. A tutorial on MOS model parameters is proposed later in this chapter.
2.6
Dynamic MOS behavior This paragraph concerns the dynamic simulation of the MOS to exhibit its switching properties. The most convenient way to operate the MOS is to apply a clock to the gate, another to the source and to observe the drain. The summary of available properties that can be added to the layout is reported below.
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Apply a clock to the gate. Click on the Clock icon and then, click on the polysilicon gate. The clock menu appears again. Change the name into Vgate and click on OK to apply a clock with 0.5ns period (0.225ns at 0, 25ps rise, 0.225ns at 1, 25ps fall).