S tay l$p trnh VHDL

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Gii thiu ngn ng VHDL

3.1. Cc cu trc c bn ca ngn ng VHDL. Cc thnh phn chnh xy dng trong ngn ng VHDL c chia ra thnh nm nhm c bn nh sau: - Entity - Architecture - Package - Configuration. - Library. Entity: Trong mt h thng s, thng th ng c thit k theo mt s xp chng cc modul, m mi Modul ny t ng ng vi mt thc th thit k ( c gi l Entity ) trong VHDL. Mi mt Entity bao gm hai phn : - Khai bo thc th ( Entity). - Thn kin trc ( Architecture Bodies ) Mt khai bo Entity c dng m t giao tip bn ngoi ca mt phn t (component), n bao gm cc khai bo cc cng u vo, cc cng u ra ca phn t . Phn thn ca kin trc c dng m t s thc hin bn trong ca thc th . Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny c s dng bi mt vi Entity no . Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t cn dng no ca mt thit k no c dng mt cu trc v a cc th hin ny vo trong cp Entity v Architecture. N cho php ng i thit k c th th nghim thay i cc s thc thi khc nhau trong mt thit k. Mi mt thit k dng VHDL bao gm mt vi n v th vin, m mt trong cc th vin ny c dch sn v ct trong mt th vin thit k.

3.1.1 Khai bo Entity:

Nh trn cp, phn khai bo Entity ch a ra mt ci nhn pha bn ngoi cu mt phn t m khng cung cp thng tin v s thc hin ca phn t nh th no. C php khai bo ca mt Entity nh sau: Entity entity_name is [generic (generic_declaration);] [port (port_declaration);] {entity_declarative_item {constants, types, signals};} end [entity_name]; [] : Du ngoc vung ch ra cc tham s c th la chn. | : Du gch ng hin th mt s la chn trong s cc la chn khc. {} : Khai bo mt hoc nhiu cc i t ng, m cc i t ng ny c th c nh ngha bi ng i dng. a. Khai bo Generic dng khai bo cc hng m chng c th c dng iu khin cu trc v s hot ng ca Entity. C php ca khai bo ny nh sau: generic ( constant_name : type [:=init_value] {;constant_name: type[:=init_value]}); y tn hng constant_name ch ra tn ca mt hng dng generic (hng dng chung). Kiu (Type) c dng ch ra kiu d liu ca hng. init_value : ch ra gi tr khi to cho hng. b. Khai bo cng ( Port ): c dng khai bo cc cng vo, ra ca Entity. C php ca khai bo ny nh sau: Port ( port_name : [mode] type [:= init_value] {; port_name:[mode] type [:=init_value]}); port_name c dng ch ra tn ca mt cng, mode ch ra h ng

vo ra ca tn hiu ti cng . Type ch ra kiu d liu ca mt cng v init_value ch ra gi tr khi to cho cng . Ch ! Vi VHDL khng phn bit ch hoa v ch th ng, chng hn nh : xyz = xYz = XYZ. * C bn mode c s dng trong khai bo cng : - in : ch c th c c, n ch c dng cho cc tn hiu u vo ( ch c php nm bn phi php gn ) - out : Ch c dng gn gi tr, n ch c dng cho cc cng u ra ( N ch c nm bn tri ca php gn ). - inout : C th c dng c v gn gi tr. N c th c nhiu hn mt h ng iu khin ( C th nm bn tri hoc bn phi php gn ). - Buffer : C th c dng c v gn gi tr. ( C th nm bn tri hoc bn phi php gn ). inout l mt cng hai h ng, cn Buffer l mt cng khng c h ng. c. entity_declarative_item : c dng khai bo cc hng, kiu d liu, hoc tn hiu m n c th c s dng trong khi thc hin ca mt Entity. d. V d : * V d v khai bo cc cng vo ra: entity xxx is port ( A : in integer ; B : in integer ; C : out integer ; D : inout integer ; E : buffer integer) ; end xxx; architecture bhv of xxx is

begin process (A,B) begin C <= A ; -- ( Cu lnh ng: A c gn cho C ). A <= B ; -- ( Cu lnh sai: A l mt u vo ). E <= D + 1; -- ( Cu lnh ng: D mode inout v vy n c th c gn v c ) D <= C + 1; -- ( Cu lnh sai : C l cng u ra nn khng th c c cho u vo ). end process; end bhv; * V d v khai bo Entity:
A B

COUT

FULL_ADDER

CIN

SUM

Hnh trn ch ra mt giao din ca mt b cng mt bit. Tn Entity ca phn t ny l FULL_ADDER . N bao gm cc cng u vo A, B v CIN. Cc cng ny c kiu d liu l kiu Bit, cn cc cng u ra SUM v COUT cng mang kiu d liu l kiu BIT. Ngn ng VHDL dng din t giao din ny nh sau: Entity FULL_ADDER is port ( A, B, CIN : in BIT;

SUM, COUT : out BIT ); End FULL_ADDER ; Chng ta c th iu khin cu trc cng nh thi gian ca mt Entity bi vic s dng cc hng generic. V d sau s ch ra vic iu khin ny, trong v d ny hng N c dng ch ra s bt ca mt b cng. Trong qu trnh m phng hoc qu trnh tng hp, gi tr thc t cho mi hng dng chung generic c th b thay i. entity ADDER is generic (N : INTEGER := 4); M : TIME := 10ns); port ( A, B : in BIT_VECTOR (N -1 downto 0 ); CIN :in BIT; SUM : out BIT_VECTOR (N-1 downto 0); COUT : out BIT ); end ADDER; Giao din m t b cng ny nh sau:
A (3) B (3) A (2) B (2) A (1) B (1) A (0) B (0)

COUT

FULL _ ADDER

CIN

SUM (3)

SUM (2)

SUM (1)

SUM (0)

3.1.2. Cc kiu kin trc ( ARCHITECTURES ):

Mt kin trc a ra kt cu bn trong ca mt Entity. Mt Entity c th c nhiu hn mt kin trc, n ch ra quan h gia cc u vo v u ra ca mt Entity m quan h ny c din t theo cc thut ng sau : - Kiu hnh vi hot ng ( Behavioral ).

- Kiu hot ng ca cc lung d liu ( Dataflow ). - Kiu cu trc ( Structure ). Mt kin trc xc nh chc nng ca mt Entity. N bao gm phn khai bo ( Khai bo cc cc tn hiu, hng, khai bo cc kiu, cc phn t, cc phn t, tip theo l cc pht biu(lnh) ng thi ). Khai bo mt kin trc s dng c php sau:

architecture architecture_name of entity_name is { architecture_declarative_part } Begin

{concurrent_statement} --(lnh ng thi) end [ architecture_name ]; 3.1.2.1. Kin trc theo kiu hnh vi hot ng ( Behavioral ): Mt kin trc kiu hnh vi hot ng ch ra cc hot ng m mt h thng ring bit no phi thc hin trong mt ch ng trnh, n ging nh vic din t cc qu trnh hot ng, nh ng khng cung cp chi tit m thit k c thc thi nh th no. Thnh phn ch yu ca vic din t theo kiu hnh vi trong VHDL l process. D i y l v d ch ra kiu din t theo kiu hnh vi ca mt b cng vi tn l FULL_ADDER.

architecture BEHAVIOUR of FULL_ADDER is begin process (A,B,CIN) begin if ( A ='0' and B ='0' and CIN='0' ) then SUM <= '0'; COUT <= '0' ; elsif (A='0' and B='0' and CIN='1') or (A='0' and B='1' and CIN='0') or (A='1' and B='0' and CIN='1') then SUM <= '1';

COUT <= '0' ; elsif (A='0' and B='1' and CIN='1') or (A='1' and B='0' and CIN='1') or (A='1' and B='1' and CIN='0') then SUM <= '0'; COUT <= '1'; elsif (A='1' and B='1' and CIN='1') then SUM <='1'; COUT <='1'; end if; end process; end BEHAVIOURAL;
3.1.2.2. Kin trc theo kiu hot ng ca cc lung d liu: Mt kin trc kiu lung d liu ch ra mt h thng d i dng m t ng thi ca cc lung iu khin v dch chuyn ca d liu. N s dng theo mu thng tin hoc mu hot ng ca lung d liu , hoc mu thi gian ca cc chc nng logic t hp. Chng hn nh cc b cng, b so snh, b gii m, v cc cng logic nguyn thu. V d :

architecture DATAFLOW of FULL_ADDER is signal S : BIT; begin S <= A xor B ; SUM <= S xor CIN after 10 ns; COUT <= (A and B ) or (S and CIN) after 5ns; end DATAFLOW;
3.1.2.3. Kin trc kiu cu trc: Mt kin trc kiu cu trc ch ra s thc thi cu trc theo dng s dng cc khai bo phn t v cc th hin ca phn t . V d d i y ch ra s din t cu trc ca mt b cng FULL_ADDER nh trn gii thiu. Hai kiu phn t c s dng trong v d ny l HALF_ADDER v

OR_GATE.

architecture STRUCTURE of FULL_ADDER is component HALF_ADDER port (L1, L2 : in BIT; CARRY, SUM : out BIT); end component; component OR_GATE port (L1, L2 : in BIT; O: out BIT); end component; HA1: HALF_ADDER port map (A,B,N1,N2); HA2: HALF_ADDER port map (N2,CIN,N3,SUM); OR1 : OR_GATE port map (N1, N3,COUT); end STRUCTURE;
v d ny Entity mc cao nht s cha hai th hin ca HALF_ADDER v mt th hin ca OR_GATE. Th hin HALF_ADDER c th b rng buc vi mt Entity khc, m Entity ny bao gm mt cng XOR v mt cng AND. Giao tip ca mt b cng HALF_ADDER c dng nh sau:
L1
X1

begin

SUM

L2

A1

CARRY

B cng ny gm c hai u vo L1 v L2 , u ra l SUM v CARRY. Kiu BIT l kiu tin nh ngha ca ngn ng VHDL, n c kiu lit k dng ch k t nh '0' v '1'.

3.1.3. Cc kiu ng gi ( Packages ):

Mc ch chnh ca Package l tp hp cc phn t c th b chia s bi

hai hay nhiu n v thit k ( Hay cc phn t c th dng chung c). N c cha cc kiu d liu, cc hng, cc ch ng trnh con c th dng chung gia cc thit k. Mt Package c ch a hai phn chnh: - Phn khai bo Package. - Phn thn Package. 3.1.3.1. Phn khai bo Package. Mt khai bo Package c dng ct gi hng lot cc khai bo dng chung, chng hn nh cc phn t, cc kiu, cc th tc, cc hm. Cc khai bo ny c th nhp vo cc n v thit k khc bi vic s dng mt mnh use. V d :

v d ny tn ca package c khai bo l EXAMPLE_PACK. N c cha cc khai bo kiu, phn t, hng, v hm. L u rng hot ng ca hm INT2BIT_VEC khng xut hin trong khai bo gi, m ch c giao tip ca hm xut hin. Vic nh ngha, hay thn ca hm ch xut hin trong thn ca ng gi ( Body Package ). Gi s rng ng gi ny c dch v to thnh mt th vin thit k v c gi l DESIGN _LIB . Xem xt vic dng mnh use s dng chng d i y:

package EXAMPLE_PACK is type SUMMER is ( MAY, JUN, JUL, AUG, SEP); component D_FLIP_FLOP port (D, CK:in BIT; Q, QBAR: out BIT) end component; constant PIN2PIN_DELAY:TIME:=125ns; function IN2BIT_VEC(INT_VALUE:INTEGER) return BIT_VECTOR; end EXAMPLE_PACK;

library DESIGN_LIB;

use DESIGN_LIB.EXAMPLE_PACK.all Entity RX is.........

Mnh library DESIGN_LIB cho php th vin thit k DESIGN_LIB c php dng trong phn m t ny, iu c ngha l tn DESIGN_LIB c th c s dng. Mnh use tip theo s ly tt c cc khai bo c trong Package EXAMPLE_PACK vo trong khai bo Entity ca RX. C ngha l ta c th chn la cc khai bo t trong mt cc khai bo ca mt ng gi vo trong mt n v thit k khc. V d :

library DESIGN_LIB; use DESIGN_LIB.EXAMPLE_PACK.D_FLIP_FLOP; use DESIGN_LIB.EXAMPLE_PACK.PIN2PIN_DELAY; architecture RX_STRUCTURE of RX is.........

Hai mnh use v d ny nhm to ra khai bo cho D_FLIP_FLOP v khai bo hng cho PIN2PIN_DELAY c php s dng trong thn kin trc. 3.1.3.2. Phn khai bo thn Package. S khc bit gia khai bo Package v thn Package c cng mc ch nh khai bo ca mt Entity v phn thn kin trc Architecture ca chng. package package_name is {package_declarative_item} end [package_name ]; package body package_name is {package_declarative_item} end [package_name] Mt thn package c dng l u cc nh ngha ca mt hm v th tc, m cc hm v th tc ny chng c khai bo trong phn khai bo package t ng ng. V vy phn thn package lun c kt hp vi phn C php khai bo ca Package c khai bo nh sau:

khai bo ca chng, hn na mt phn khai bo package lun c t nht mt phn thn package kt hp vi chng. V d : package EX_PKG is subtype INT8 is integer range 0 to 255; constant zero : INT8:=0; procedure Incrementer (variable Count : inout INT8); end EX_PKG; package body EX_PKG is procedure Incrementer (variable Data : inout INT8) is begin if (Count >= MAX ) then Count:=ZERO; else Count:= Count +1; end if; end Incrementer; end EX_PKG;

3.1.4. nh cu hnh ( Configurations ) :

Mi mt Entity bao gm nhiu kin trc khc nhau. Trong qu trnh thit k, ng i thit k c th mun th nghim vi cc s bin i khc nhau ca thit k bng vic chn la cc kiu kin trc khc nhau. Configuration c th c s dng cung cp mt s thay th nhanh cc th hin ca cc phn t ( Component ) trong mt thit k dng cu trc. C php khai bo ca Configuration ny nh sau:

Configuration configuration_name of entity_name is {configuration_decalarative_part} For block_specification {use_cluse} {configuration_item}

end for;
Vi mt Entity ca b cng FULL_ADDER nh gii thiu phn trn, v d ny ta c th s dng chng trong php nh cu hnh nh sau: configuration FADD_CONFIG of FULL_ADDER is For STRUCTURE for HA1, HA2 : HALF_ADDER use entity burcin.HALF_ADDER(structure); for OR1: OR_GATE use Entity burcin.OR_GATE; end for; end FADD_CONFIG; y tn ca php nh cu hnh l tu , v d ny ta ly tn l FADD_CONFIG, cn vi dng lnh For STRUCTURE ch ra kin trc c nh cu hnh v c s dng vi thc th Entity FULL_ADDER. Gi s rng chng ta dch hai thc th HALF_ADDER v OR_GATE thnh th vin vi tn l burcin v s dng chng trong v d trn.

3.1.5. Cc th vin thit k :

Kt qu ca vic bin dch VHDL l chng c ct gi bn trong cc th vin dng cho b c m phng tip theo, iu ny ging nh thit k c th cha cc n v th vin nh sau: - Cc ng gi (PACKAGES) - Cc thc th Entity - Cc kiu kin trc Architectures - Cc php nh cu hnh Configurations. vic s dng mt phn t c khai bo trong mt thit k khc. Mt th vin

Ch ! VHDL khng h tr cc th vin theo th bc. Bn c th c nhiu th vin nh theo mun nh ng khng c khai bo lng nhau!

 m mt th vin v truy cp chng nh mt Entity c bin dch trong mt thit k VHDL mi, iu u tin cn lm l phi khai bo tn th vin. C php ca chng nh sau: Library library_name : [path/directory_name]; Bn c th truy cp cc n v c bin dch t mt th vin VHDL ti ba mc nh sau: library_name.Package_name.item_name V d: Gi s chng ta to mt ng gi ct mt hng m hng ny c s dng trong nhiu thit k, sau dch n v ct vo trong th vin vi tn l burcin .

Package my_pkg is constant delay: time:=10ns; end my_pkg;

Tip n chng ta gi my_pkg s dng chng trong thit k d i y:

architecture DATAFLOW of FULL_ADDER is signal S : BIT; begin S <= A xor B; SUM <= S xor CIN after burcin.my_pkg.delay; COUT <= (A and B ) or (S and CIN) after 5ns; end DATAFLOW;
3.2. Cc i t ng d liu : Mt i t ng d liu gi mt gi tr ca mt kiu nht nh. Trong VHDL c ba lp i t ng d liu : - Cc hng ( constants ). - Cc bin ( Variables ).

- Cc tn hiu ( Signals ). Lp cu mt i t ng c ch ra bi mt t kho v n c ch ra im bt u ca mt khai bo.

3.2.1. Cc hng ( Constant ):

Mt hng n l mt i t ng m n c khi to ch ra mt gi tr c nh v n khng b thay i. Khai bo hng c php khai bo trong cc ng gi, cc Entity, cc kin trc, cc ch ng trnh con, cc khi, v trong pht biu ca cc qu trnh processes. C php khai bo chng nh sau : Constant constant_name {constant_name}: type [:= value]; V d :

constant YES : BOOLEAN:= TRUE; constant CHAR7: BIT_VECTOR (4 downto 0 ):="00111"; constant MSB: INTEGER:=5; 3.2.2. Cc bin :
Cc bin c dng l u d liu tm thi, chng ch c php khai bo trong pht biu Process hoc cc ch ng trnh con. V d :

variable X,Y : BIT; variable TEMP: BIT_VECTOR (8 downto 0) ; variable DELAY : INTERGER range 0 to 15:=5; 3.2.3. Cc kiu tn hiu ( Signal ):
Tn hiu c dng kt ni cc Entity ca thit k li vi nhau v trao i cc gi tr bin i trong pht biu process. Chng c th c xem nh cc dy dn hay cc bus ni trong mch thc t. Tn hiu c th c khai bo trong cc ng gi ( Package ), trong cc khai bo Entity,

trong khai bo kin trc (Architecture), trong cc khi ( Block ). Vi cc tn hiu c khai bo trong cc package th tn hiu ny c gi l tn hiu ton cc ( Cc thit k c th s dng chng ), cc tn hiu c khai bo trong Entity l tn hiu ton cc trong mt Entity, t ng t vi tn hiu c khai bo trong mt kin trc, n l tn hiu dng chung trong mt kin trc . C php ca chng c dng nh sau : Signal Signal_name {,signal_name}: type [:=value]; V d :

signal BEEP : BIT:= '0'; signal TEMP: STD_LOGIC_VECTOR (8 downto 0); signal COUNT: INTEGER range 0 to 100 :=5;
3.3. Cc kiu d liu: Tt c cc i t ng d liu trong VHDL cn phi c nh ngha vi mt kiu d liu. Mt khai bo kiu phi ch ra tn v di ca kiu . Khai bo kiu d liu chng c php khai bo trong phn khai bo cc ng gi, trong phn khai bo Entity, trong phn khai bo kin trc, trong phn khai bo cc ch ng trnh con v trong phn khai bo cc Process. Cc kiu d liu bao gm cc kiu sau: - Kiu lit k - Kiu nguyn. - Cc kiu d liu tin nh ngha. - Kiu mng. - Kiu bn ghi. - Kiu d liu chun logic. - Kiu d liu c du v khng du. - Cc kiu ph.

3.3.1. Cc kiu lit k ( ENUMERATION ).

Mt kiu lit k c ch ra bi vic lit k cc gi tr cho php ca kiu . Tt c cc gi tr c nh ngha bi ng i dng c th l cc tn nh danh, hoc cc cc kiu ch k t . Tn nh danh thc cht l mt tn do ng i dng t ra, chng hn nh blue, ball, monday. Kiu ch k t l kiu ca cc k t c km theo du ngoc n, chng hn nh 'x', ' 0'... C php khai bo cu chng nh sau: Type type_name is (enumerattion_literal {, enumeration_literal}); Vi type_name l mt tn nh danh v mi enumerattion_literal hoc l mt tn nh danh hoc l mt ch k t. V d : type COLOR is (RED, ORANGE, YELLOW, GREEN, BLUE, PURPLE); type DAY is (MONDAY, TUESDAY,WEDNESDAY,THURDAY,FRIDAY); type STD_LOGIC is ('U','X','0','1','Z','W','L','H','_'); Mi mt nh danh trong mt kiu u c mt v tr nht nh trong kiu, chng c xc nh bi th t xut hin cu chng trong kiu . Trong v d trn, mc nh RED c v tr 0, ORANGE s c v tr 1 ..... Nu chng ta khai bo mt i t ng d liu vi kiu l COLOR v khng nh ngha gi tr khi to th i t ng d liu s c khi to mc nh v tr u tin ca kiu lit k ( V tr khng ), trong tr ng hp ny COLOR s nhn gi tr RED.

3.3.2. Kiu nguyn :

Kiu nguyn l cc kiu s nguyn, chng c dng cho cc php tnh, cc ch s, cc iu khin s vng lp. Trong hu ht cc kiu thc thi trong VHDL c di t - 2,147,483,647 n + 2, 147, 483,647. C php ca

chng c khai bo nh sau: type type_name is range - 2,147,483,647 to + 2, 147, 483,647; V d : type INTEGER is range - 2,147,483,647 to + 2, 147, 483,647; type COUNT is range 0 to 10;

3.3.3. Cc kiu d liu tin nh ngha trong VHDL :

IEEE nh ngha hai gi d liu STANDART v TEXTIO trong th vin STD. Mi mt gi d liu ny c cha mt lot cc kiu v cc php tnh chun . D i y l cc kiu d liu c nh ngha trong gi STANDARD: - BOOLEAN: Mt kiu lit k vi hai gi tr true v False, cc thao tc Logic v cc php ton quan h s tr v gi tr Boolean. - BIT : Mt kiu lit k vi hai gi tr '0' v '1' , cc php tnh logic c th ly v tr v gi tr kiu BIT. - CHARACTER: Kiu lit k ca cc m ASCII. - INTEGER : c dng miu t cc s m v d ng. Di hot ng ca chng c n nh t - 2.147.438.647 n 2.147.438.647. Cc hm ton hc nh cng, tr ,nhn, chia c h tr kiu nguyn. - NATURE: Cc kiu con ca kiu nguyn c dng miu t cc s kiu t nhin ( khng m ). - POSITIVE: cc kiu con ca kiu nguyn c dng miu t cc s d ng. - BIT_VECTOR : c dng miu t mt mng cc gi tr kiu BIT. - STRING : Mt mng cc k t, mt gi tr kiu chui c i km bi du ngoc kp. - REAL: c dng m t cc kiu s thc, di hot ng t1.0E+38 n +1.0E+38.

- Kiu thi gian vt l : M t cc gi tr thi gian c dng trong m phng. C mt vi kiu d liu c nh ngha trong gi STANDARD nh sau:

Type BOOLEAN is ( fase, true); Type BIT is ( '0', '1' ); Type SEVERITY_LEVEL is (note, warning, error, failure ); Type INTEGER is range -2147483648 to 2147483648; Type REAL is Range -1.0E38 to 1.0E38; Type CHARACTER bel,............); 3.3.4. Kiu mng :
Kiu mng l kiu ca nhm cc phn t c cng kiu ging nhau. C hai kiu mng nh sau: - Kiu mng c gn kiu . - Kiu mng khng b gn kiu. Kiu mng b gn kiu l kiu m cc ch s mng ca chng c nh ngha t ng minh. C php ca chng nh sau: type array_type_name is array (discrete_range) of subtype_indication ; y array_type_name l tn ca kiu mng c p kiu, discrete_range kiu ph ca kiu nguyn khc hoc kiu lit k, subtype_indication chnh l kiu ca mi phn t ca mng. Kiu mng khng b gn kiu l kiu m ch s mng ca chng khng b ch ra, nh ng cc kiu ch s ca chng phi c ch ra. C php ca chng c ch ra nh sau: type array_type_name is array (type_name range <>) of

is (nul, soh, stx, eot, enq, ack,

subtype_indication; V d : type A1 is array ( 0 to 31) of INTEGER; type Bit_Vector is arrray (NATURAL range <>) of BIT; type STRING is array (POSITIVE range <>) of CHARACTER; A1 l mt mng gm ba hai phn t m trong mi phn t l mt kiu nguyn. Mt v d khc ch ra kiu Bit_vector v kiu String c to ra trong chun cc gi STANDARD. V d : subtype B1 is BIT_VECTOR ( 3 downto 0); variable B2 : BIT_VECTOR (0 to 10); Di ch s xc nh s phn t trong mng v h ng ca chng ( low to high | high to low ). VHDL cho php khai bo cc mng nhiu chiu c th dng khai bo cc mu RAM v ROM. Xem v d d i y: type Mat is array (0 to 7, 0 to 3) of BIT; constant ROM : MAT : = (( '0', '1', '0', '1'), ('1', '1', '0', '1' ), ('0', '1', '1', '1' ), ('0', '1' , '0', '0' ), ('0', '0' ,'0' , '0'), ('1', '1' , '0', '0' ), ('1', '1' , '1', '1' ), ('1', '1' , '0', '0' ); X := ROM (4,3); Bin X s ly gi tr '0' c t m.

3.3.5. Kiu Record :

Kiu record l mt nhm c nhiu hn mt phn t c cc kiu khc

nhau. Phn t ca Record bao gm cc phn t ca bt c kiu no, n c th l cc kiu mng hoc kiu Record. V d : type DATE_TYPE is ( SUN, MON, TUE , WED , THR , FRI , SAT) ; type HOLIDAY is record YEAR : INTEGER range 1900 to 1999; MONTH : INTEGER range 1 to 12 ; DAY : INTEGER range 1 to 31; DATE : DATE_TYPE; end record ; signal S : HOLIDAY; variable T1: integer range 1900 to 1999; variable T2 : DATE_TYPE; T1: = S .YEAR; T2:= S . DATE; S . DAY <= 30;

3.3.6. Cc kiu STD_LOGIC :

to mu cc ng tn hiu c nhiu hn hai gi tr ( '0' , '1' ), VHDL nh ngha chn khong trong gi chun. Chn gi tr bao gm : type STD_LOGIC is ( 'U' -- khng khi to gi tr 'X' -- Khng xc nh '0' -- Kiu mc thp '1' -- Kiu mc cao 'Z' -- Kiu tr khng cao 'W' -- Khng xc nh mc yu 'L' -- Mc thp yu

'H' -- Mc cao yu '_' -- Khng quan tm n gi tr .); T ng t nh kiu BIT v kiu BIT_VECTOR, VHDL cung cp mt kiu khc gi l STD_LOGIC_VECTOR. s dng cc nh ngha v cc hm trong gi chun logic, cc pht biu sau y cn c phi khai bo nh km theo ch ng trnh . Library IEEE; USE IEEE.STD_LOGIC_1164.all;

3.3.7. Cc kiu d liu khng du v c du .

Cc kiu d liu c du v khng du chng c ch ra trong cc gi chun NUMERIC_BIT v NUMERIC_STD. Cc i t ng vi kiu c du v hai . Vic nh ngha ca cc kiu d liu c ch ra nh sau: khng du chng c hiu nh l cc s nguyn binary khng du v vi kiu c du v chng c dch nh cc nguyn b cc i t ng

type

signed

is

array

(NATURAL

range

<>)

of

BIT/STD_LOGIC;
Cc pht biu d i y bao gm cc khai bo vic s dng ca cc kiu d kiu c du v khng du.

Library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_BIT.all; use IEEE.NUMERIC_STD.all; 3.3.8. Cc kiu con .
VHDL cung cp cc cc kiu con m cc kiu con ny chng c nh ngha trong cc nh cc tp ph trong mt kiu khc. Bt c u c mt khai bo kiu th c th xut hin mt nh ngha kiu con. Kiu

NATURAL v kiu POSITIVE l mt kiu ph hay kiu con ca kiu nguyn v chng c th c dng vi bt k mt hm nguyn no. V d :

subtype INT4 is INTEGER range 0 to 15; subtype BIT_VECTOR6 is BIT_VECTOR (5 downto 0);
3.4. Cc ton t : VHDL cung cp 6 lp ton t , mi mt ton t c mt mc u tin nht nh. Tt c cc ton t trong cng mt lp th c cng mt mc u tin. Mc u tin thp nht . . . . . . . . . . Relational _ operator Logical_operator and or nand nor xor = /= < <= > >= Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cc ton t Cc ton hng

concatenation_operator arithmetic_operator arithmetic_operator arithmetic_operator

& + + * / mod rem Cng kiu Cng kiu Bt k kiu s no Bt k kiu s no Cng kiu Cng kiu integer integer Kiu m integer Bt k kiu s no Cng kiu

Mc u tin cao nht

arithmetic_operator Logical_operator

** abs not

3.4.1. Cc ton t logical .

Kiu ton t logic khng chp nhn cc ton hng l cc kiu tin nh ngha nh kiu BIT, BOOLEAN v cc kiu mng cc bit, cc ton hng cn phi l cng kiu v cng di. V d :

signal A,B : BIT_VECTOR (6 downto 0); signal C,D,E,F,G: BIT; A<= B and C ; -- Khng xy ra v cc ton hng khng cng kiu. D <= (E xor F) and (C xor G); 3.4.2. Cc ton t quan h .
Cc ton t quan h cho ta kt qu c kiu Boolean, cc ton hng cn phi c cng kiu v cng di. V d :

signal A,B : BIT_VECTOR (6 downto 0); signal C: BOOLEAN; C <= B <= A; ( T ng ng nh C <= (B<=A)); 3.4.3. Cc ton t cng .
Cc ton t cng bao gm "+", "-" , v "&" , trong ton t "&" l ton t kt ni chui v cc i t ng l mng cc thanh ghi. Vi s c du v khng du c th c dng vi cc s nguyn v cc kiu BIT_VECTOR. V d :

signal W: BIT_VECTOR (3 downto 0); signal X: INTEGER range 0 to15; signal Y,Z : UNSIGED (3 downto 0); Z <= X + Y + Z; Y <= Z (2 downto 0) & W(1); "ABC" & "xyz" cho kt qu l : "ABCxyz" "1010" & "1" cho kt qu l : "10101"
3.5. Cc kiu ton hng . Trong mt biu thc cc ton t s dng cc ton hng tnh ton cc gi tr ca chng. Cc ton hng trong mt biu thc bao gm : - Kiu ch - Kiu nh danh - Cc tn c nh theo ch s - Tn cc Slice - Tn cc c tnh - Cc biu thc iu kin - Cc li gi hm

- Cc biu thc chuyn i

3.5.1. Kiu ch .
Cc kiu ch c th chia ra thnh hai nhm chnh : - Kiu v h ng . Kiu k t . Kiu BIT . Kiu chun STD_LOGIC . Kiu Boolean . Kiu s thc . Kiu nguyn . Kiu thi gian - Kiu mng . Kiu chui . Kiu BIT_VECTOR . STD_LOGIC_VECTOR

3.5.1.2. Kiu ch k t .
Kiu ch k t ch ra mt gi tr bng vic s dng mt k t n v km theo mt du ngoc n. Nhn chung VHDL khng quan tm n cc tr ng hp ch th ng v ch hoa, xong vi kiu ch k t cn phi phn bit ch th ng v ch hoa. V d : 'a' hon ton khc vi kiu 'A' trong kiu ch k t. Kiu ch k t c th c dng nh ngha bt c kiu no trong cc ng gi chun v gi tr mc nh ca chng l Null. V d : 'A' , 'a' , ......'1' . Kiu ch k t khng phi l kiu bit k t nh '1' hoc kiu nguyn 1, v vy kiu ch l t cn phi c cung cp mt tn kiu no .

3.5.1.3. Kiu chui .

Mt kiu chui k t thc cht l mt mng cc k t . Mt chui cc

k t c nh ngha trong mt du ngoc kp . V d : "A" , " hold time error ", " x " ....

3.5.1.4. Kiu BIT .

Kiu bit l kiu m t hai gi tr ri rc bng vic s dng cc ch k t '0' v '1'. i khi cc kiu Bit ny c dng to ra kiu ch bit mt cch t ng minh dng phn bit chng vi cc kiu k t. V d : '1' , ' 0 ' , bit' ('1')

3.5.1.5. Kiu BIT_VECTOR .

Kiu bit_vector l mt mng cc bit m chng c t trong du ngoc kp . V d : "01001111000" , x"00FFF0" , b"100010101" , o"277756"... Trong v d trn ch 'x' c dng din t cc gi tr s hexa, cn 'b' c dng m t kiu binary, cn 'o' c dng cho h m c s 8.

3.5.1.6. Kiu ch trong ng gi chun STD_LOGIC.

Kiu ch logic chun l mt trong 9 gi tr c nh ngha trong ng gi chun v c a ra d i dng cc ch in hoa v t trong du ngoc n . V d : ' U ' khng trng vi ' u ' 'X','0','1','Z','W','L','H','_'

3.5.1.7. Kiu ch STD_LOGIC_VECTOR.

Mt kiu ch STD_LOGIC_VECTOR thc cht l mt mng bao gm cc phn t ca kiu std_logic v c t trong du ngoc kp. V d : " 10_1Z" , " UUUUU " , signed("1011 ").....

3.5.1.8. Kiu Boolean .

Kiu Boolean c dng m t hai gi tr ri rc, l kiu true v false. V d : true , false , True , TRUE, FALSE ...

3.5.1.9. Kiu s thc .

Kiu s thc l kiu c dng din t cc s thc nm trong khong t -1.0E+38 n +1.0E+38. Mt kiu s hc c th l kiu d ng hoc m nh ng chng phi c du chm thp phn . V d : + 1.0 khng c vit '1' hoc 1 hoc ' 1.0 ' 0.0 khng c vit 0 -1.0 , -1.0E+10.

3.5.1.10. Kiu nguyn .

Mt kiu nguyn c dng din t cc s nguyn nm trong khong t - 2,147,438,647 n + 2,147,438,647. V d : +1 , 862 862.0 , - 257 , + 123_456 , 16 # 00FF #. Trong cc k hiu c dng nh ngha kiu nh sau: s_n # s din t trong c s n ", y n nm trong h 2 n 16. " C

3.5.1.11. Kiu TIME.

Mt kiu vt l duy nht c nh ngha tr c trong ng gi chun, l thi gian time. V d : 10 ns , 100 us , 6.3 ns ..... Ch phn s phi c vit cch phn n v o bi mt khong trng.

3.5.2. Cc kiu nh danh:

Kiu nh danh n thun ch l mt ci tn do ng i dng nh ngha, n c th l tn ca mt hng, mt bin hay mt tn hiu, mt Entity, mt cng, hay mt ch ng trnh con, hay cc khai bo tham bin . Khi khai bo mt tn cn phi khai bo k t u tin phi kiu ch k t, l u du gch d i khng c php ng sau cng, cc t kho ca VHDL khng c dng lm khai bo cc kiu nh danh, chng hn nh entity, port .... V d : xyz = xYZ = XYZ = XyZ

S(3) phn t th ba ca mng S X3.

3.5.3.Kiu INDEX.
Kiu INDEX c s dng ch ra mt phn t no trong mt mng. C php s dng ca khai bo ny nh sau: array_name (expression) Vi array_name l mt tn ca mt hng hay mt bin no nm trong mt mng. Cn expression phi tr v gi tr nm trong di ch s ca mng . V d : type memory is array ( 0 to 7 ) of INTEGER range 0 to 123; variable DATA_ARRAY : memory; variable ADDR : INTEGER range 0 to 7; variable DATA: INTEGER range 0 to 123; DATA:= DATA_ARRAY ( ADDR );

3.5.4. Kiu Slice v ALIAS.

Mt khai bo Slice c dng ch ra mt s phn t ca mng. H ng ca n cn phi ph hp vi h ng mng. Alias c dng to ra mt tn mi cho tt c cc hoc mt s phn t no nm trong mt mng. V d : variable A1: BIT_VECTOR ( 7 downto 0 ); A2: = A1(5 downto 2) ; Alias A3: BIT_VECTOR (0 to 3) is A1(7 downto 4); ( C ngha l A3(0) = A1(7), A3(1) = A1(6), A3(2) = A1(5), A3(3) = A1(4) ) Alias A4: BIT is A1(3);

3.5.5. Kiu thuc tnh ATTRIBUTE:

Ly cc thuc tnh cu mt bin hay mt tn hiu ca mt kiu cho

tr c no v tr v mt kiu gi tr. D i y l cc kiu thuc tnh th ng dng trong ngn ng VHDL: - Left : Tr v ch s ca phn t bn tri cng ca mt kiu d liu. - Right : Tr v ch s ca phn t bn phi cng ca mt kiu d liu. - High : Tr v ch s ca phn t cao nht ca mt kiu d liu. - Low : Tr v ch s ca phn t thp nht ca mt kiu d liu. - Range : c dng ly v di ca ch s. - Reverse_range : Dng xc nh di ch s ng c li. - Length : Tr v s phn t ca kiu BIT_VECTOR. - Event : M t s thay i gi tr ca tn hiu ti thi im m phng. V d : variable A1 : BIT_VECTOR ( 10 downto 0 ); A1' left A1' right A1' high A1' low -- Tr v gi tr l 10. -- Tr v gi tr 0. -- Tr v gi tr l 10. -- Tr v gi tr l 0.

A1' range -- Tr v l 10 downto 0. A1' reverse_range -- Tr v gi tr l 0 to 10. A1' length -- Tr v gi tr l 11.

3.5.6. Kiu tp hp :
Kiu tp hp c th c dng gn gi tr cho mt i t ng thuc kiu mng hoc kiu Record trong khi khi to khai bo hoc trong cc pht biu gn. V d : type color_list ( red, orange, blue, white ); type color_array is array (color_list) of BIT_VECTOR ( 1 downto 0 ); variable X : color_array; X := (" 00 " , " 01 " , " 10 " ," 11 " ); X := ( red => "00" , blue => "01" , orange => "10" , white => "11" );

Trong dng th hai, chng ta nh ngha mt mng m s cc phn t ca chng ( di ch s ) c a ra bi color_list. T color_list chng ta c mt mng gm bn phn t v mng color_array cng s bao gm bn phn t, m mi phn t ny li c nh ngha bi kiu Bit_Vector. Hn na chng ta s dng di ch s ca mng color_list s c di t 0 n 3, v vic nh ngha ca mng ny ch ch ra di ch s ch khng ch ra kiu ca phn t trong mng.

3.5.7. Biu thc gn kiu :

Biu thc gn kiu c dng ch ra kiu ca mt ton hng no . C php ca chng nh sau: type_name' ( expression ); V d : type color1 is (red, orange, blue, white); type color2 is (purple, green, red, black); color2'(red); Nh chng ta thy ton hng red c c trong hai kiu color1 v color2, v vy n cn c phi c gn mt kiu d liu r rng v iu ny c thc hin bi cu lnh th 3.

3.5.8. Php chuyn i kiu d liu.

Php chuyn i kiu cho php chuyn i cc kiu c kiu d liu gn ging nhau. V d : signal X : STD_LOGIC_VECTOR ( 3 downto 0 ); signal Y : STD_ULOGIC_VECTOR ( 3 downto 0 ); Y <= STD_ULOGIC_VECTOR (X); Sau cu lnh th ba Y s nhn kiu STD_ULOGIC_VECTOR. 3.6. Cc pht biu tun t . Pht biu tun t ch ra s thc hin tng b c ca mt qu trnh. Chng thc hin t cu lnh u tin, cu lnh th hai, ... cu lnh cui cng.

Cc pht biu nm trong mt pht biu qu trnh ( Pht biu Process ) c gi l pht biu tun t . Cc pht biu sau y l cc pht biu tun t c nh ngha trong VHDL: - Cc pht biu gn bin Variable. - Cc pht biu gn tn hiu Signal. - Cc pht biu if. - Cc pht biu Case. - Cc pht biu Null. - Cc pht biu xc nhn ASSERTION. - Cc pht biu vng lp Loop. - Cc pht biu NEXT. - Cc pht biu EXIT. - Cc pht biu WAIT. - Cc pht biu Procedure. - Cc pht biu RETURN.

3.6.1. Pht biu gn bin .

Dng thay th gi tr hin thi ca bin vi mt gi tr mi, gi tr mi ny c ch ra bi mt biu thc. Bin c th c khai bo v s dng bn trong mt pht biu qu trnh hay cn c gi l pht biu Process. Mt bin c gn mt gi tr s dng thng qua pht biu gn bin, m pht biu ny c hnh thc nh sau: target_variable : = expression; L u cc bin c khai bo trong mt Process khng th chuyn gi tr ra ngoi Process, iu c ngha l chng ch c cp pht trong Process hoc trong ch ng trnh con. V d v php gn bin trong mt Process.

Biu thc c xc nh gi tr khi pht biu c thc thi v gi tr c tnh ton s c gn cho bin mt cch tc thi.

Bin c to ti thi im sn sinh v duy tr gi tr ca n trong sut thi gian chy ch ng trnh. Do v mt qu trnh khng bao gi c thot ra trong mi trng thi hot ng ca n, ngha l chng c thc thi, hoc trong mt trng thi ch. Nu trng thi ch th chng phi ch cho n khi mt s kin khc chc chn xy ra. Mt qu trnh bt u thc hin ti im khi u ca mt qu trnh m phng, ti thi im ny n c thc thi cho n khi gp mt pht biu wait hoc gp cc thnh phn c khai bo trong danh mc cn c x l khai bo trong Process.

Xem th d v pht biu Process nh sau: V d 1 : process(A) variable EVENT_ON_A : INTEGER : = -1; begin EVENT_ON_A : = EVENT_ON_A +1; end process; V d 2: Subtype INT16 is INTEGER range 0 to 65536; Signal S1, S2 : INT16; Signal GT : BOOLEAN; process (S1, S2) variable A, B : INT6; constant C : INT16 : = 100; Begin A := S1 +1 ; B : = S2*2 - C; GT <= A > B; End Process; Ti lc bt u ca qu trnh m phng. Qu trnh c thc thi mt ln. Bin EVENT_ON_A c gn gi tr -1 sau tng ln 1. Sau , thi im bt k xy ra, s kin trn tn hiu A, qu trnh c hiu lc v pht biu gn bin n c thc thi. N lm cho bin EVENT_ON_A tng ln mt. Ti thi im kt thc ca qu trnh m phng, bin EVENT_ON_A cha tng s s kin xy ra trn tn hiu A. Mt th d khc ca pht biu qu trnh : signal A, Z:INTEGER; ... PZ: process(A); -- PZ l nhn ca qu trnh variable V1,V2 : INTEGER; begin V1:=A-V2; -- statement 1 Z<= -V1; -- statement 2 V2:= Z+V1*2; -- statement 3 end process PZ; Gi s mt s kin xy ra trn tn hiu A ti thi im T1 v bin V2

 c gn gi tr l 10, trong pht biu th 3, sau mt s kin xy ra trn tn hiu A ti thi im T2, gi tr ca V2 c s dng trong pht biu 1 s cng l 10. Mt bin cng c th c khai bo bn ngoi mt qu trnh hoc mt ch ng trnh con. Mt bin c th c c v cp nht bi mt hoc c th nhiu qu trnh, nhng bin ny c gi l shared variable (Bin chia s).

3.6.2. Pht biu gn tn hiu.

Pht biu gn tn hiu s thay th gi tr hin ti ca tn hiu vi mt gi tr mi bi vic s dng mt biu thc. Tn hiu v kt qu ca biu thc cn c cng mt kiu d liu. C php ca chng nh sau: target_signal <= [ Transport] expression [after time_expression] Pht biu gn tn hiu c th xut hin bn trong hoc bn ngoi mt qu trnh. Nu n xy ra bn ngoi ca mt qu trnh, n c xem l mt pht biu gn tn hiu ng thi. Khi pht biu gn tn hiu xut hin bn trong qu trnh, n c xem nh l mt pht biu gn tn hiu c th t v n c thc thi tun t theo th t ca nhng pht biu tun t khc xut hin bn trong qu trnh. V d php gn tn hiu trong mt Process (Vi A,B,C,D l cc tn hiu):

Khi mt pht biu gn tn hiu c thc thi, gi tr ca biu thc c tnh ton v gi tr ny c chun b gn cho tn hiu sau khi delay. L u rng biu thc c nh l ng ti thi im pht biu v khng thc thi ngay m n s thc thi sau mt thi gian gi chm. C hai kiu Delay c cung cp chun b cho vic thc thi tn hiu: - Transport Delay. - Inertial Delay. a. Transport Delay. N t ng t nh s gi chm bn trong ca mt dng in chy qua dy dn. Nu thi gian gi chm ny c xem nh tiu tn vo thc hin cng vic no v tip sau n ( ng thi im ca mt cng vic tr c hon thnh ) cn phi thc hin mt cng vic khc th thi gian thc hin cc cng vic tip theo s c thm vo cui ca cng vic tr c . Cn nu khong thi gian cn thc hin mt cng vic tin nh ( Thi gian thc hin ca mt cng vic tip theo no ng tr c thi im thc hin mt cng vic tr c, th cu lnh Transport s thc hin chn vo v thc hin cng vic tin nh ny ).

Xem v d sau : Gi s ta c mt process v biu nh sau

S

4 3

1 ns

3 ns

4 ns

5 ns

V d : .......... process (.....) Begin S <= transport 1 after 1 ns, 3 after 3 ns, 5 after 5 ns; S <= transport 4 after 4 ns; end process; Nh v d v biu trn ta thy cng vic th t cn thc hin tr c cng vic th 5, nh ng trong phn ch ng trnh th pht biu ca cng vic th 5 li c thc hin tr c cng vic th t . Hnh v d i y m t pht biu Transport, sau 3s n s c bt sng v sng trong khong thi gian ng bng thi gian bt cng tc.

b.Inertial Delay. Inertial Delay ( G chm do qun tnh ), l gi tr mc nh ca VHDL. N c dng cho cc thit b m khng c phn ng cho n khi u vo c php trong mt khong thi gian nht nh. Th ng th vi tn hiu c khong thi gian tc ng khng u v nh hn thi gian gi chm ca cc cng th s b b qua. Vi v d trn, m t hot ng ca n vi gi chm do sc qun tnh ca mch. Nu thi gian tc ng ca cng tc nh hn gi chm ca mch th u ra s khng c tc ng hay n s khng c bt sng. Gi s ta c cu lnh n s c bt sng sau 3 giy, nh ng cng tc ch tc ng trong thi gian hai giy th n s khng c bt sng. Xem hnh v d i y:

Gi s ta c cu lnh bt n sau 3s. Khi bt cng tc trong thi gian 4s sau tt cng tc, th n s c sng sau khi cng tc bt c 3s v sng trong 4s ng bng thi gian bt cng tc. Xem hnh d i y:

c. So snh INERTIAL DELAY v TRANSPORT DELAY.

Inertial Delay S <= A after 20 ns Transport Delay S <= Transport A after 20 ns

A S

A S 10ns 20ns 30ns 40ns 10ns 20ns 30ns 40ns

Nh trn hnh ta thy trong tr ng hp Inertial Delay, tn hiu A c tc ng trong khong 10ns, nh ng cu lnh thc hin u ra S sau 20ns, v vy u ra S s khng c tc ng. Cn trong tr ng hp Transport Delay tn hiu u ra s c sao y tn hiu u vo sau khi bt u s n ln ca tn hiu vo c tc ng ( ng bng khong 20 ns ca cu lnh ).

3.6.3. Cc pht biu IF.

Mt pht biu if c dng chn la nhng pht biu tun t cho vic thc thi da trn gi tr ca biu thc iu kin. Biu thc iu kin y c th l mt biu thc bt k m gi tr ca chng phi l kiu lun l. Dng thng th ng ca pht biu if l: if boolean-expression then sequential-statements {elsif boolean-expression then sequential -statement } {else sequential-statement}

enf if;
V d1: if sum <=100 then --<= is less-than-or-equal-to operator. SUM:=SUM+10; end if; V d 2: signal IN1, IN2, OU : STD_LOGIC; process (IN1, IN2) begin if IN1 = '0' or IN2 = '0' then OU <= '0' ; elsif IN1 = 'X' or IN2 = 'X' then OU <= '1'; else OU <= '1' ; end if;

end process; V d 3:

3.6.4. Pht biu CASE.

Dng ca pht biu case l: case expression is when choices => sequential -statement when choices => sequential -statement -- -- C th c nhiu nhnh {when others => sequential-statement} end case; Pht biu case la chn mt trong nhng nhnh cho vic thc thi da trn gi tr ca biu thc. Gi tr biu thc phi thuc kiu ri rc hoc kiu mng mt chiu. Cc chn la ( Choices ) c th c din t nh mt gi tr n, hoc mt di gi tr bng vic s dng du " | " hoc s dng mnh khc. Tt c cc gi tr c th c ca biu thc phi c th hin trong pht biu case ng mt ln. Cc mnh khc c th c s dng bao qut tt c cc gi tr, v nu c, phi l nhnh cui cng trong pht biu case. -- last branch -- branch 1 -- branch 2

Mi mt chn la phi c cng kiu vi kiu ca biu thc. Mt th d cho pht biu case: V d 1: type WEEK_DAY is (MON, TUE, WED, THU, FRI, SAT, SUN); type DOLLARS is range 0 to 10; variable DAY: WEEK_DAY; variable POCKET_MONEY: DOLLARS; case DAY is when TUE => POCKET_MONEY :=6; -- branch1 when MON | WED => POCKET_MONEY :=2; -- branch2 when FRI to SUN => POCKET_MONEY :=7; -- branch3 when others => POCKET_MONEY :=0; -- branch4 end case; Nhnh 2 c chn nu DAY c gi tr l MON hoc WED. Nhnh 3 bao gm cc gi tr FRI, SAT v SUN. Trong khi nhnh 4 gm cc gi tr cn li, THU. Pht biu case cng l pht biu tun t, tuy nhin n cng c th c pht biu xp lng nhau. V d 2:

3.6.5. Pht biu NULL.

Pht biu null L mt pht biu tun t khng gy ra bt k hnh ng no; H thng s b qua pht biu NULL v tip tc thc thi vi pht biu k tip. Mt th d cho vic s dng pht biu ny l trong pht biu if hoc trong pht biu case. V d : Variable A, B : INTEGER range 0 to 31 ; Case A is when 0 to 12 => B:= A; when others => Null; End Case;

3.6.6. Pht biu xc nhn ASSERTION.

Pht biu xc nhn rt hay dng cho vic kim tra thi gian v cc iu

kin ngoi di. V d : assert (X >3 ) report " Setup violation" severity warning;

3.6.7. Pht biu Loop.

Mt pht biu lp c s dng lp li mt lot cc cu lnh tun t. C php ca pht biu lp l: [loop-label:] iteration-scheme loop sequential-statements end loop [loop-lebel]; C 3 kiu s lp. u tin l s lp c dng: for identifier in range V d 1: V d v For ...Loop FACTORAL:=1; for NUMBER in 2 to N loop FACTORAL :=FACTORAL*NUMBER; enf loop; Trong th d ny, thn ca vng lp thc thi N-1 ln, vi nh danh lp l NUMBER v tng ln 1 sau mi vng lp. i t ng NUMBER c khai bo n trong vng lp ty thuc vo kiu integer, n c gi tr t 2 n N. V vy khai bo khng r rng cho nh danh vng lp l iu cn thit, nh danh vng lp cng khng th c gn cho bt k gi tr no trong vng lp for. Nu mt bin khc c cng tn c to bn ngoi vng lp for, l hai loi bin c gii quyt ring r v bin s dng trong vng lp for s chuyn giao cho nh danh vng lp. Vng ca vng lp FOR cng c th l vng ca mt kiu lit k. V d 2: type HEXA is (0,1,2,3,A,B,C ); . . . . for NUM in HEXA(2) downto HEXA(0) loop

-- Num s ly nhng gi tr trong kiu HEXA t 2 cho n 0. end loop; V d 3: V d v While .... loop

3.6.8. Pht biu Next.

Pht biu next cng l pht biu lin tc cng ch c th s dng bn trong vng lp. C php t ng t nh pht biu exit: next [loop-label][when condition]; Kt qu ca pht biu next s b qua nhng pht biu cn li trong ln lp hin ti ca vng lp v tip tc thc thi vi pht biu u tin trong vng lp k tip. Nu tn ti mt ln v nu nhn vng lp khng r rng th s xy ra hin t ng lp n v cng. i lp vi pht biu exit, n l nguyn nhn ca vng lp b gii hn. V d 1: for j in 10 downto 5 loop if SUM < TOTAL_SUM then SUM:=SUM +2; elsif SUM:= TOTAL_SUM then next; else

null; end if; K:=K+1; end loop; Khi pht biu next c thc thi, qu trnh thc hin s nhy n phn cui ca vng lp (pht biu cui cng K: =K+1) sau gim gi tr ca nh danh vng lp j, v thc hin li t u. V d 2:

3.6.9. Pht biu EXIT.

Pht biu exit l mt pht biu tun t n ch c th s dng bn trong vng lp. N c th lm cho qu trnh thc hin nhy n vng lp trong cng hoc ra khi vng n v tr ca nhn xc nh no khi n gp nhn ny trong vng lp. C php ca mt pht biu exit l: exit [loop-label][when condition]

Nu nhn vng lp khng c ch ra th qu trnh thc hin s lp n vng lp trong cng. Nu mnh WHEN c s dng th vic tn ti vng lp ch xy ra nu iu kin l ng. Ng c li, vic thc

hin s tip tc vi pht biu k tip. V d :

SUM :=1; J:=0 ; L3:loop J:=J+21; SUM:=SUM*10 if (SUM >100) then exit L3; -- Thc hin exit khi L3 nu Sum> 100 enf if; end loop L3;

3.6.10. Pht biu WAIT.

Nh chng ta thy, mt qu trnh m phng c th tr hon (Hay treo s thc hin ca mt pht biu Process hoc mt ch ng trnh con ) cho n khi gp mt iu kin ph hp. C 3 hnh thc c bn ca pht biu wait. wait on sensitivity-list; wait until boolean -expression; wait for time-expression; V d 1: wait on A,B ; wait until A = B; wait for 10 ns; wait on CLOCK for 20 ns ; wait until SUM >100 for 50 ms; S hin din ca sensitivity list trong mt qu trnh trng vi tr ng hp mt trong ba tr ng hp trn ca pht biu wait . Mt pht biu qu trnh c wait on cui ca Process t ng ng vi mt pht biu qu trnh c khai bo sensitivity-list. Xem hnh d i y: Hai process ny l t ng ng nhau.

V d 2 : process -- Khng sensitivity list variable TEMP1, TEMP2:BIT; begin TEMP1:=A and B; TEMP2:=C and D; TEMP1:=TEMP1 or TEMP2; Z<=not TEMP1; wait on A, B, C, D; -- Thay th cho sensitivity-list u Process . End process. V d 3: Hai Process trong v d d i y ch ra hai process c pht biu Wait on. Process bn tri s lm cho Process treo ngay sau khi Start v ch cho n khi c s kin xut hin trn tn hiu SigA. Cn Process bn phi s thc hin ba cu lnh v sau ri vo trng thi ch n khi xut hin s kin trn tn hiu SigB.

3.6.11. Cc li gi ch ng trnh con.

Khi m t thit k theo kiu hot ng hnh vi, cc ch ng trnh con th ng hay c s dng v a ra cch thc s dng thun tin. C hai loi ch ng trnh con hay c s dng l Hm v Th tc.

- Th tc ( Procedure) tr v nhiu gi tr. - Hm ( Function ) tr v mt gi tr n. Cc li gi th tc s gi th tc m n cn c thc hin trong mt qu trnh. Pht biu tr v ( return ) s l im kt thc mt ch ng trnh con, v n ch c s dng trong mt hm hoc mt th tc. i vi hm th n c qui nh vi pht biu tr v trong thn hm, nh ng vi th tc th c th s dng tu trong thn th tc. C php ca pht biu tr v nh sau: return [expression]; y expression s a ra cc gi tr tr v ca hm, pht biu return trong mt hm cn phi c mt biu thc v gi tr tr v ca n, nh ng i vi pht biu tr v trong th tc th khng cn phi c mt ca biu thc. Mt hm c th c nhiu hn mt pht biu tr v, nh ng ch c mt pht biu tr v c s dng bi mt li gi hm.

3.7. Cc pht biu ng thi.

Cc pht biu ng thi c thc hin song song trong cng thi im m phng, chng khng thc hin theo th t m chng c vit ra trong mt kin trc. Cc pht biu ng thi chuyn thng tin thng qua cc ng tn hiu. D i y l cc pht biu ng thi c nh ngha trong VHDL: - Cc pht biu gn ca mt qu trnh (Process). - Cc pht biu gn tn hiu ng thi . - Cc pht biu gn tn hiu iu kin. - Cc pht biu gn tn hiu c chn la. - Cc pht biu Block. - Cc li gi th tc ng thi. - Cc pht biu xc nhn ng thi.

3.7.1. Pht biu Process .

Pht biu process l pht biu bao gm mt tp cc pht biu tun t v pht biu process li chnh l pht biu ng thi. C ngha l tt c cc pht biu Process trong mt thit k c thc hin mt cch ng thi. Tuy nhin ti mt thi im nht nh c a ra ch c mt pht biu tun t c thc hin trong mi process. Mt Process c kt ni vi phn cn li ca thit k bi vic c hoc vit ra cc gi tr t cc tn hiu v cc cng m chng c khai bo pha ngoi Process. C php ca chng c vit nh sau: [label:] process [(sensitivity_list)] {process_declaration_part} begin {sequential_statements} end process [label]; Phn khai bo ca mt process ch ra cc i t ng m vng hot ng ca n ch thuc vng ca mt process v chng c th l cc i t ng sau y: - Khai bo bin . - Khai bo hng . - Khai bo cc kiu. - Khai bo cc kiu con. - Khai bo cc b danh Alias. - Cc mnh USE. Mt sensitivity list ( Tp cc s kin thay i trng thi cn x l trong mt qu trnh ) c cng ngha vi mt Process c cha pht biu wait, m pht biu wait ny l pht biu cui cng trong mt process v chng c dng sau: Wait on sensitivity list ; Mt process c chc nng ging nh mt vng lp v hn m trong n

c cha ton b cc pht biu tun t c ch ra trong vng lp . V vy mt pht biu process cn phi c hoc mt sensitivity list hoc mt pht biu wait on hoc c hai. V d 1: architecture A2 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin pr1 : process (i1, i2, i3, i4) begin and_out <= i1 and i2 and i3 and i4; end process pr1; pr2 : process (i1, i2, i3, i4) begin or_out <= i1 or i2 or i3 or i4 ; end process pr2; end A2 V d 2:

3.7.2. Cc php gn tn hiu ng thi.

Mt dng khc ca vic gn tn hiu ng thi l cc php gn tn hiu ng thi , cc php gn ny c dng bn ngoi ca mt process nh ng phi nm trong mt kin trc ( architecture ). C php ca php gn ny nh sau: target_sinal <= expression [after time_expression ]; T ng t nh cc php gn tn hiu tun t , mnh after s b b qua bi b tng hp. Vi bt k mt tn hiu no nm bn phi ca mt php gn u mang ngha t ng t nh mt phn t trong sensitivity list . Mt thn architecture c th cha s l ng bt k ca nhng pht biu gn tn hiu ng thi. V chng l nhng pht biu ng thi nn th t ca nhng pht biu l khng quan trng. Nhng pht biu gn tn hiu ng thi c thc thi bt c khi no c s kin xy ra trong tn hiu c s dng trong biu thc. V d1 : architecture A1 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin and_out <= i1 and i2 and i3 and i4; or_out <= i1 or i2 or i3 or i4; end A1; V d 2: architecture A2 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin process (i1, i2, i3, i4) begin and_out <= i1 and i2 and i3 and i4;

end process ; process (i1, i2, i3, i4) begin or_out <= i1 or i2 or i3 or i4 ; end process ; end A2 V d 3: architecture A3 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin process begin and_out <= i1 and i2 and i3 and i4; or_out <= i1 or i2 or i3 or i4; wait on i1, i2, i3, i4; end A3; Ba v d trn y l t ng ng nhau.

3.7.3. Cc php gn tn hiu c iu kin v cc php gn tn hiu c chn la. a. Cc php gn tn hiu c iu kin.
Mt php gn tn hiu c iu kin chnh l mt pht biu ng thi v c mt ch gn nht nh, tuy nhin php gn ny c th c nhiu hn mt biu thc cho mt ch. Ngoi tr biu thc cui cng, cc biu thc cn li phi c mt iu kin chc chn, cc iu kin ny c nh gi theo th t. Nu mt iu kin c nh gi l TRUE th biu thc t ng ng c s dng, ng c li cc biu thc cn li s c s dng. Nh rng ch mt biu thc c s dng ti mt thi im . C php ca cu lnh ny nh

sau: target <= {expression [ after time_expression ] when condition else} expression [ after time_expression ]; Mt pht biu gn tn hiu c iu kin c th c m t bi mt pht biu process m process c cha pht biu IF. Bn c th s dng pht biu gn tn hiu c iu kin trong mt process . V d 1: architecture A1 of example is signal a, b, c ,d : integer ; begin a <= b when ( d >10 ) else c when ( d >5 ) else d; end A1; V d 2: architecture A2 of example is signal a, b, c ,d : integer ; begin process (b, c, d) begin if ( d > 10) then a <= b elsif ( d >5 ) then a <=c; else a <= d; end if; end process;

end A2; V d 3: S dng cc pht biu c iu kin.

b. Cc php gn tn hiu c chn la.

Php gn tn hiu c chn la c th ch mt ch gn v cng ch c mt biu thc with. Gi tr ny c kim tra ging nh pht biu Case thng th ng. N s qun l bt c s thay i no xut hin ti cc tn hiu c chn la. C php ca chng nh sau: with choice_expression select target <= {expression [after time_expression] when choices} expression [ after time_expression] when choices; Bt k php gn tn hiu c chn la no u c th c m t t ng ng bi pht biu process c cha pht biu case. Bn khng c s dng pht biu gn tn c chn la trong mt process . V d 1: with SEL select

Z <= a when 0 | 1 | 2, b when 3 to 10, c when others; V d 2 : process ( SEL, a, b, c ) case SEL is when 0 | 1 | 2| => Z <= a; when 3 to 10 => Z <= b; when others => Z <= C; end case; end process ; Hai v d trn y l hon ton t ng ng nhau.

3.7.4. Cc pht biu Block.

Cc block cho php ng i thit k nhm cc phn theo trt t logic ca cc mu ng thi, vi iu kin l cc phn ny khng nm trong l c s dng ca cc mu khc ( cc mu m chng c s dng thay th cc thnh phn khc trong mt thit k ). Cc block c s dng t chc cc pht biu gn ng thi theo th bc. C php ca chng nh sau: label : Block {block_declarative_part} begin {concurrent_statement} end block [label]; Phn khai bo block ch ra cc i t ng thuc min cc b ca block v c th l cc thnh phn sau y: - Khai bo tn hiu. - Khai bo hng. - Khai bo kiu.

- Khai bo cc kiu con. - Thn cc ch ng trnh con - Khai bo b danh ALIAS - Cc mnh use - Khai bo cc thnh phn ( Component). Cc i t ng c khai bo trong mt block ch c php hot ng trong block v cc block vng trong ca n. Khi mt block con khai bo mt i t ng c trng tn vi i t ng trong block cha th khai bo ca block con s nh ngha li i t ng trng tn vi block cha. V d : architecture BHV of example is signal : out 1 : integer; signal : out 2 : bit; begin B1 : block signal S : bit; begin B1-1 : block signal S : integer; begin out 1 <= S ; end block B1-1; end block B1; B2: block begin out 2 <= S ; end block B2; end BHV; Trong v d ny ta thy block B1-1 l block con ca block B1. C B1 v B1-1 u khai bo tn hiu S. Tn hiu S trong B1-1 s l kiu integer v truyn cho tn hiu out 1 cng l kiu integer, mc d S c khai bo trong B1 l kiu Bit. Tn hiu S trong B1 c s dng trong B2 l kiu Bit, trng

vi kiu tn hiu out 2.

3.7.5. Cc li gi th tc ng thi.
Mt li gi th tc ng thi chnh l mt li gi th tc m n c thc thi bn ngoi mt process, n ng c lp trong mt kin trc architecture. Li gi th tc ng thi bao gm : - C cc tham s IN, OUT, INOUT. - C th c nhiu hn mt gi tr tr v - N c xem nh mt pht biu. - N t ng ng vi mt process c cha mt li gi th tc n. Hai v d d i ay l t ng ng nhau. V d 1: architecture ................. begin procedure_any (a,b) ; end..........; V d 2: architecture ................ Begin process begin procedure_ any (a,b); wait on a,b; end process ; end .............;

3.7.6. Cc ch ng trnh con .

Cc ch ng trnh con bao gm cc th tc v cc hm m n c th c gi thc hin cng vic no lp li t cc v tr gi khc nhau

trong VHDL. Trong VHDL cung cp hai kiu ch ng trnh con khc nhau l: - Cc th tc (Procedure). - Cc hm ( Function ). a. Hm v cc c tr ng ca hm. - Chng c gi v thc hin nh mt biu thc. - Lun tr v mt i s. - Tt c cc tham s ca hm u phi l ch mode IN. - Tt c cc tham s ca hm phi thuc lp cc tn hiu hoc cc hng. - Bt buc phi khai bo kiu ca ga tr tr v . - Khng c cha cc pht biu Wait. C php ca hm c khai bo nh sau: function identifier interface_list return type_mark is {subprogram_declarative_item} Begin {sequential_statement} end [identifier]; Cc nh danh identifier ch ra tn ca mt hm, cn interface_list ch ra nh dng tham s ca mt hm. Mi mt tham s c nh nghi theo c php sau: [class] name_list [mode] type_name [:=expression]; y class ca tham s i t ng phi c ch ra l tn hiu hoc hng, cn mode ca i t ng cn phi l mode in. Nu khng c tham s mode c ch ra th c hiu nh l mode IN, cn nu khng c tham s class c ch ra th tham s c hiu nh l mt hng. Xem v d sau: process function c_to_f ( c : real ) return real is variable f : real; begin

f := c*9.0/5.0 + 32.0; return (f); end c_to_f; variable temp : real; begin temp : = c_to_f (5.0) + 20.0; end process; Tham s chuyn vo hm c hiu mc nh l mt hng s, v khng c khai bo ca class. b. Th tc v cc c tr ng ca chng. - Chng c gi nh mt li pht biu. - C th tr v khng hoc mt hoc nhiu i s. - Cc tham s chuyn giao cho th tc c th l mode in, out, v inout. - Cc tham s chuyn giao cho th tc c th l tn hiu, hng, bin. - C th c cha pht biu Wait. C php khai bo th tc nh sau: procedure identifier interface_list is {subprogram_declarative_item} begin {sequential_statement} end [identifier]; Identifier c s dng ch ra tn ca procedure v interface_list ch ra cc tham s hnh thc ca procedure. Mi tham s c s dng theo nh ngha sau: [class] name_list [mode] type_name [:=expression]; Class ca i t ng c xem nh hng, bin , hoc l tn hiu v mode ca i t ng c th l in, out , inout. Nu khng c mode c ch ra th -- temp = 61

tham s c hiu nh mode in, nu khng c class c ch ra th cc tham s mode in c hiu nh l cc hng, cn tham s mode out v inout c hiu nh l cc bin. Cc tham s c th l cc hng, cc bin, hoc cc tn hiu v mode ca chng c th l in, out, hoc inout. Nu lp ca cc tham s khng xc nh r rng th mc nhin n l constant, nu n l mode in, cn n l bin nu mode ca tham s l out hoc inout. Mt v d thn procedure m t hnh vi hot ng ca cc n v logic s hc nh sau : type OP_CODE is ( ADD, SUB, MUL, DIV, LT, LE, EQ); procedure ARITH_UNIT (A, B : in INTEGER ; OP : in OP_CODE ; Z : out INTEGER; ZCOMP : out BOOLEAN ) is begin case OP is when ADD => Z := A+B; when SUB => Z := A-B; when MUL => Z := A*B; when DIV => Z := A/B; when LT => ZCOMP := A<B; when LE => ZCOMP := A<=B; when EQ => ZCOMP := A=B; end case ; end ARITH_UNIT; Ta xem mt v d khc ca thn mt procedure, procedure ny quay vc t c xc nh vi tn l ARRAY_NAME, bt u t bit START_BIT ti bit STOP_BIT, bi mt gi tr ROTATE_BY. Lp i t ng ca tham s ARRAY_NAME c xc nh mt cch t ng minh. Bin FILL_VALUE t ng c khi to v 0 mi khi procedure c gi. Procedure ROTATE_LEFT (signal ARRAY_NAME : inout Bit_vector ;

START_BIT, STOP_BIT : in NATUAL; ROTATE_BY : in POSITIVE ) is Variable FILL_VALUE : BIT; begin assert STOP_BIT > START_BIT report STOP_BIT is not greater than START_BIT severity NOTE; for MACVAR3 in 1 to ROTATE_BY loop FILL_VALUE := ARRAY_NAME (STOP_BIT); for MACVAR1 in STOP_BIT downto (START_BIT + 1) loop ARRAY_NAME (MACVAR1) <= ARRAY_NAME (MACVAR1 1); end loop; ARRAY_NAME (START_BIT) <= FILL_VALUE ; end loop; end procedure ROTATE_LEFT; Cc procedure c gi bi li gi procedure. Mt li gi Procedure c th l mt pht biu tun t hoc mt pht biu ng thi, pht biu ny ph thuc vo ni xut hin li gi th tc hin ti. Nu li gi ny nm bn trong mt pht biu process hoc mt ch ng trnh con khc th n c gi l pht biu gi procedure tun t, ng c li n c gi l pht biu gi procedure gi ng thi. C php ca pht biu gi procedure nh sau : [ label : ] procedure_name ( list_of_actual ); Thc t cc biu thc, cc bin, cc tn hiu hoc cc file, c chuyn vo trong th tc v cc tn cu i t ng v cc tn ny s c dng ly cc gi tr tnh ton t trong th tc. Chng c ch ra mt cch r rng bi vic s dng s kt hp theo tn v kt hp theo v tr . V d:

ARITH_UNIT (D1, D2, ADD, SUM, COMP ); -- S kt hp theo v tr. ARITH_UNIT ( Z => SUM, B=> D2, A=>D1, OP=>ADD, ZCOMP => COMP); -- S kt hp theo tn.

Mt pht biu gi th tc tun t c thc thi tun t cng vi cc pht biu tun t chung quanh n. Mt pht biu gi th tc ng thi c thc thi bt c lc no khi c mt s kin xy ra trn mt trong cc tham s, m cc tham s ny l mt tn hiu ch in hoc inout. Mt li gi th tc ng thi c ngha t ng ng vi mt process c cha mt li gi th tc tun t v mt pht biu wait. Pht biu wait ny s lm cho qu trnh ch cho n khi c mt s kin xut hin trn cc tham s tn hiu ca mode in hoc inout. Sau y l mt v d ca li gi th tc ng thi v pht biu process t ng ng vi n: architecture DUMMY_ARCH of DUMMY is -- Tip n l thn ca th tc procedure INT_2_VEC ( signal D : out BIT_VECTOR ; START_BIT, STOP_BIT : in NATUAL ; signal VALUE : in INTEGER ) is begin -- M t hot ng hnh vi ca th tc end INT_2_VEC; begin -- y l v d ca mt li gi th tc ng thi. INT_2_VEC (D_ARRAY, START, STOP, SIGNAL_VALUE); end DUMMY_ARCH; Pht biu process t ng ng vi li gi mt th tc ng thi nh sau: process

begin INT_2_VEC (D_ARRAY,START,STOP,SIGNAL_VALUE); -- Phn th hin ca cc li gi th tc tun t wait on SIGNAL_VALUE; -- Ch s kin trn SIGNAL_VALUE v xem chng nh mt tn hiu vo. end process;

Mt procedure c th s dng hoc l mt pht biu ng thi hoc l pht biu tun t. Cc li gi ng thi th ng xuyn c dng m t chnh l cc process. V d ca th tc dng c khai bo postpone ( Tr hon ).
postponend procedure INT_2_VEC ( signal D:out BIT_VECTOR ; START_BIT,STOP_BIT NATUAL; signal VALUE :in INTEGER) is begin -- Phn khai bo hot ng ca th tc end INT_2_VEC; : in

Ng ngha ca mt li gi th tc ng thi dng postponed l t ng ng vi nh ngha ca pht biu process t ng ng vi n v c gi l pht biu process b tr hon.
Mt thn process c th c pht biu wait, trong khi mt function th khng c php c. Cc function c s dng tnh ton cc gi tr mt cch tc th. V vy mt function khng cn c pht biu wait trong . Mt function khng th gi mt procedure c pht biu wait trong th tc . Mt process m c cha li gi mt th tc m trong th tc ny c cha

pht biu wait, th process ny khng c khai bo sensitivity list. Hn na t thc t chng ta thy mt process khng th nhn bit cc tn hiu thuc sensitivity list v nu c process ny s ri vo trang thi ch ngay lp tc. Vi mt th tc c cha pht biu wait th bt c bin hay hng no c khai bo trong th tc s gi nguyn gi tr ca chng trong sut thi gian thc hin pht biu wait v tn ti ch khi th tc c kt thc.

3.8. Cc ng gi ( Packages ).
Bn c th ng gi ct cc ch ng trnh con, cc kiu d liu, cc hng ...th ng dng s dng chng trong cc thit k khc. Mt package bao gm hai phn chnh: Phn khai bo v phn thn package, phn khai bo ch ra giao tip cho package . C php ca khai bo package nh sau: package package _name is {package _declarative_item} end [package _name]; Phn package _declarative_item c th l bt k kiu no sau y: - Khai bo kiu. - Khai bo cc kiu con. - Khai bo tn hiu. - Khai bo cc hng. - Khai bo b danh ALIAS. - Khai bo cc thnh phn. - Khai bo cc ch ng trnh con. - Cc mnh USE. Ch ! khai bo tn hiu trong package c mt s vn cn l u trong khi tng hp, bi v mt tn hiu khng th c chia s bi hai Entity. V vy nu mun dng chung khai bo tn hiu bn phi khai bo tn hiu ny l tn hiu ton cc.

Phn thn ca package ch ra hot ng thc t ca mt package. Phn thn ca package phi lun c tn trng vi phn khai bo. C php ca khai bo ny nh sau: package body package _name is {package _body_declarative-item} end [package _name] ; Phn package _body_declarative-item c th bao gm: - Khai bo kiu. - Khai bo cc kiu con. - Khai bo cc hng - Mnh use. - Thn cc ch ng trnh con. V d: library IEEE; use IEEE.NUMERIC_BIT.all; package PKG is subtype MONTH_TYPE is integer range 0 to 12; subtype DAY_TYPE is integer range 0 to 31; subtype BCD4_TYPE is unsigned ( 3 downto 0); subtype BCD5_TYPE is unsigned ( 4 downto 0) ; constant BCD5_1: BCD5_TYPE : = b"0_0001" ; constant BCD5_7: BCD5_TYPE : = b"0_0111" ; function BCD_INC (L : in BCD4_TYPE) return BCD5_TYPE; end PKG; package body PKG is function BCD_INC (L :in BCD4_TYPE) return BCD5_TYPE is variable V,V1, V2 : BCD5_TYPE; begin V1 : = L + BCD5_1; V2 : = L + BCD5_7; case V2(4) is when ' 0 ' => V : = V1; when ' 1 ' => V : = V2; end case;

return (V); end BCD_INC; end PKG;

3.9. M hnh cu trc .

Thng th ng mt h thng s c m t theo tp hp c th bc ca cc thnh phn . Mi thnh phn bao gm mt tp cc cng c th giao tip c vi cc thnh phn khc. Khi m t mt thit k trong VHDL v mt thit k c th bc chnh l mt thit k a ra cc khai bo ca cc thnh phn v cc pht biu th hin thnh phn . Mt n v c s din t hnh vi hot ng chnh l cc pht biu process, cn n v c s din t theo kiu cu trc chnh l cc pht biu th hin ca cc n v thnh phn. C hai loi ny u c th c mt trong mt thn ca mt kin trc ( architecture ).

3.9.1. Cc khai bo thnh phn .

Mt thn kin trc c th s dng cc Entity khc (khng trong cng khai bo ca architecture ), cc Entity ny c m t tch bit v c t trong th vin thit k. s dng chng, ng i ta dng cc khai bo thnh phn v cc pht biu th hin ca chng .Trong m t thit k, mi pht biu khai bo thnh phn phi t ng ng vi mt Entity . Cc pht biu khai bo thnh phn phi ging vi cc pht biu c ch ra trong Entity (cc pht biu giao tip vo ra ca thnh phn ). C php khai bo ca chng nh sau: component component _name [ port ( local_port_declaration ) ] end component ; Trong component _name m t tn ca Entity v port_declaration l khai bo cc cng ca component v phi trng vi phn khai bo ch ra

cu component nm trong phn khai bo ca Entity.

3.9.2. Cc th hin ca component.

Mt component c nh ngha trong mt architecture c th c th hin thng qua vic s dng cc pht biu th hin ca chng. Khi th hin ch c php th hin phn giao tip ca component ( Bao gm tn, kiu , h ng ca cc cng vo ra ca chng ), cc tn hiu bn trong chng khng c th hin. C php th hin component nh sau: instantiation_label : component _name port map ( [ local_port_name =>] expression { [local_port_name =>] expression} ); Mt pht biu th hin component cn phi khai bo phn nhn ca th hin tr c instantiation_label. Hnh v d i y m t phn giao din v phn thc thi bn trong ca mt b cng full_Adder.
A B Cin

Sum

FULL_Adder
Cout

Phn giao din component ca b cng Full_adder.

A B N3 Cout N2 Cin N1 SUM

Phn thc thi bn trong ca component Full_Adder. Nh trn hnh v chng ta thy phn thc thi c ba loi cng khc nhau v chng c mang tn nh sau: OR2_gate, AND2_gate, XOR_gate,

chng c dng xy dng nn b cng. m t v th hin chng trong thit k, ta c th vit ch ng trnh thc thi tng thnh phn ca chng nh sau: library IEEE; use IEEE.STD_LOGIC_1164.all; Entity AND2_gate is port ( I0, I1 : in STD_LOGIC ; O : out STD_LOGIC ); End AND2_gate; Architecture BHV of AND2_gate is Begin O <= I0 and I1; End BHV; library IEEE; use IEEE.STD_LOGIC_1164.all; Entity XOR_gate is port ( I0, I1 : in STD_LOGIC ; O : out STD_LOGIC ); End XOR_gate; Architecture BHV of XOR_gate is Begin O <= I0 xor I1; End BHV; library IEEE; use IEEE.STD_LOGIC_1164.all; Entity OR2_gate is port ( I0, I1 : in STD_LOGIC ; O : out STD_LOGIC ); End OR2_gate; Architecture BHV of OR2_gate is Begin O <= I0 xor I1; End BHV; th hin cc component ny trong mt thit k, ta khai bo chng nh sau: library IEEE;

use IEEE.STD_LOGIC_1164.all; Entity FULL_ADDER is port (A, B, Cin : in STD_LOGIC; Sum, Cout : out STD_LOGIC); End FULL_ADDER; Architecture IMP of FULL_ADDER is component XOR_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component ; component AND2_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component; component OR2_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component; signal N1, N2, N3: STD_LOGIC; begin U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1); U2 :AND2_gate port map ( A, B, N2); U3 :AND2_gate port map ( Cin, N1, N3); U4 :XOR_gate port map ( Cin, N1, Sum); U5 :OR2_gate port map ( N3, N2, Cout); end IMP;

3.9.3. Cc pht biu Generate.

Pht biu generate l mt pht biu ng thi v n c nh ngha

trong phn architecture. N c dng m t cc cu trc ging nhau, hay ti to li cc cu trc khc ging nh bn gc. C php ca chng nh sau: instantiation _label : generation_scheme generate {concurrent_statement} end generate [instantiation _label]; C hai loi l c generation : L c for v l c if. L c for c dng din t cu trc thng th ng, n c dng khai bo mt tham s generate v mt di ri rc ca l c for ( ch ra tham s vng lp v di ri rc trong cc pht biu lp tun t ). Cc gi tr tham s ca generate c th c c nh ng khng c gn hay chuyn ra ngoi pht biu generate. a. S dng l c for: V d : Gi s ta c b cng 4 bit m trong bao gm bn b cng Full_adder nh c m t trn. Xem hnh d i y:
X (3) Y (3) X (2) Y (2) X (1) Y (1) X (0) Y (0)

Cout
FA (3) FA (2) FA (1) FA (0)

'0'

Z (3)

Z (2)

Z (1)

Z (0)

m t b cng 4 bit ny v s dng pht biu generate, s dng m t b cng Full_Adder nh trn ta m t. Ta c th vit chng nh sau:

architecture IMP of FULL_ADDER4 is signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ; signal Cout : STD_LOGIC ; signal TMP : STD_LOGIC_VECTOR ( 4 downto 0 ) ; component FULL_ADDER port ( A, B, Cin : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; begin

end IMP; b. S dng l c if.

X (3) Y (3)

TMP (0) <= ' 0 '; G : for I in 0 to 3 generate FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 )); end generate ; Cout <= TMP (4);

X (2)

Y (2)

X (1)

Y (1)

X (0)

Y (0)

Cout
FA (3) FA (2) FA (1) HA (0)

Z (3)

Z (2)

Z (1)

Z (0)

S b cng bn bit s dng mt b cng Half_ADDER v ba b cng FULL_ADDER

Mt s cu trc c dng khng theo qui lut chun no, vi tr ng hp ny ta c th s dng l c if. Gi s ta m t b cng bn bit nh trn hnh trn v s dng lc IF generate m t b cng ny. Ch ng trnh c vit nh sau: architecture IMP of FULL_ADDER4 is signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ; signal Cout : STD_LOGIC ; signal TMP : STD_LOGIC_VECTOR ( 4 downto 1) ; component FULL_ADDER port ( A, B, Cin : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; component HALF_ADDER port ( A, B : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; begin G0 : for I in 0 to 3 generate G1: if I = 0 generate HA: HALF_ADDER port map ( X (I), Y(I), Z (I), TMP ( I+1 )); end generate ; G2: if I >= 1 and I <= 3 generate FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 end generate ; end generate ; Cout <= TMP ( 4 ); end IMP;

));

3.9.4. Cc thng s ca vic nh cu hnh.

Trong mt Entity c th c mt vi cu trc, v vy cc chi tit cu vic nh cu hnh cho php ng i thit k chn cc Entity v kin trc ca n.

C php khai bo ca chng nh sau: for instantiation _list : component _name use Entity library_name. Entity _name [( architecture _name)] ; Nu ch c mt kin trc architecture th tn architecture c th b b qua. Xem thm mt v d d i y: library IEEE; use IEEE.STD_LOGIC_1164.all; Entity FULL_ADDER is port (A, B, Cin : in STD_LOGIC; Sum, Cout : out STD_LOGIC); End FULL_ADDER; Architecture IMP of FULL_ADDER is component XOR_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component ; component AND2_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component; component OR2_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component; signal N1, N2, N3: STD_LOGIC; for U1 : XOR_gate use entity work.XOR_gate (BHV); for others : XOR_gate use entity work.XOR_gate (BHV); for all : AND2_gate use entity work.AND2_gate (BHV); for U5 : OR2_gate use entity work.OR2_gate (BHV);

begin U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1); U2 :AND2_gate port map ( A, B, N2); U3 :AND2_gate port map ( Cin, N1, N3); U4 :XOR_gate port map ( Cin, N1, Sum); U5 :OR2_gate port map ( N3, N2, Cout); end IMP;

3.10. M hnh mc RT (Register Tranfer) v cc mch logic t hp.

DIN Combinational Logic register DOUT

clock

Mt thit k mc chuyn i thanh ghi bao gm mt tp cc thanh ghi c kt ni vi mch logic t hp nh c ch ra trn hnh v. Mt process khng c cha cc pht biu if trn cc s n chuyn i tn hiu hoc cc pht biu wait trn cc s kin ca tn hiu th c gi l cc process t hp. Tt c cc pht biu tun t ngoi tr pht biu wait , pht biu lp, pht biu if trn s n chuyn i tn hiu c th c s dng m t cc mch logic t hp . Cc mch logc t hp khng c b nh nh cc gi tr. V vy mt bin hoc mt tn hiu cn phi c gn mt gi tr tr c khi c tham chiu. y l mt v d m t mch logic t hp :

process (A, B, Cin) begin Cout <= ( A and B ) or (( A or B) and Cin ); end process ; Ch ! V khng c cc pht biu if, wait, loop nn cc tn hiu vo phi thuc danh sch sensitivity list .

3.11. Cc thit b logic c bn. 3.11.1. Cc b cht.

Cc flip - flop v cc b cht l hai thit b nh mt bit th ng hay c s dng nht trong cc mch s. Mt Flip - Flop chnh l mt thit b nh c khi to bi kch thch ca s n tn hiu, cn b cht l mt thit b nh cm nhn chuyn mc ca tn hiu. Ni chung cc b cht chng c tng hp t cc biu thc iu kin khng hon ton r rng trong vic m t mch logic t hp. Tt c cc tn hiu hoc cc bin m khng c iu khin d i tt c cc iu kin u tr thnh phn t cht. Cc pht biu if and case c ch ra khng hon ton r rng u to ra cc b cht. V d d i y pht biu IF khng gn mt gi tr cho tn hiu Data_out khi S khng bng ' 1', v vy khi tng hp b tng hp s to ra mt b cht.
Signal S, Data_in, Data_out : bit; process (S, Data_in) Begin if ( S = '1' ) then Data_out <= Data_in; end if; end process ; Data_In
SET

Data_out

S
CLR

trnh b cht nhm ta phi gn tt c cc gi tr ti tt c cc tn hiu d i tt c cc iu kin, thm vo pht biu else ca v d tr c th b tng

hp s tng hp nh mt cng AND. xem v d d i y:

Signal S, Data_in, Data_out : bit; process (S, Data_in) Begin if ( S = '1' ) then Data_out <= Data_in; else Data_out <= ' 0 '; end if; end process ; Data_In Data_out S

Chng ta c th ch ra mt b cht vi ng reset khng ng b hoc cc ng preset khng ng b nh sau:

Signal S, RST, Data_in, Data_out : bit; process (S, RST, Data_in) Begin if ( RST = '1' ) then Data_out <= ' 0 '; elsif ( S = ' 1 ' ) then Data_out <= Data_in; end if; end process ; Data_In

SET

Data_out

en
CLR

RST

Thay v ng Data_out c gn bng ' 0 ', chng ta c th gn '1' cho ng Preset khng ng b.

3.11.2. Cc FLIP - FLOP.

Mt process vi cc pht biu if trn s n chuyn tn hiu hoc cc pht biu wait trn s kin ca tn hiu c gi l mt qu trnh thc hin theo nhp ng h. Mt Flip - Flop s oc to ra nu c c mt kch thch bi mt s n tn hiu, hn na nu php gn tn hiu c thc hin trn vic kch thch chuyn mc ca mt tn hiu khc. V d :

Signal CLK, Data_in, Data_out : bit; process (CLK) Begin if ( CLK'event and CLK = '1' ) then Data_out <= Data_in; end if; end process ;

Data_In

SET

Data_out

CLK
CLR

3.11.3. Cc ng tn hiu SET v RESET ng b.

Vic thit lp cc u vo (SET) v reset cc u ra ng b ca Flip Flop cng vi hot ng ca h thng ng h, ngoi cc khong thi gian khc cc tn hiu ny khng c xem xt, iu ny c thc hin bi phn t nh.
Signal CLK, S_RST, Data_in, Data_out : bit; process (CLK) Begin if ( CLK'event and CLK='1' ) then if (S_RST ='1') then Data_out <= ' 0 '; else Data_out <=Data_in; end if; end if; end process ; Data_In ' 0'
S_RST

M UX

D
CLK

SE T

Data_out

CLR

3.11.4. Cc ng tn hiu SET v RESET khng ng b.

Signal CLK, A_RST, Data_in, Data_out : bit; process (CLK, A_RST) Begin if ( A_RST = '0' ) then Data_out <= ' 0 '; elsif ( CLK'event and CLK = ' 1 ' ) then Data_out <= Data_in; end if; end process ; Data_In CLK
SET

Data_out

CLR

A_RST

Cc ng SET v RESET ca Flip - Flop hot ng c lp vi ng Clock.

3.11.5. Cc mch RTL t hp v ng b.

Chng ta c th chia cc pht biu ca mt process RTL thnh vi mch t hp v vi mch ng b. Phn mch ng b dng m t cc mch con m cc hot ng hnh vi ca chng ch c c nh l ng khi c chuyn mc ca tn hiu. Phn mch t hp dng m t cc mch con m hot ng hnh vi ca chng s c nh l ng bt c khi no c s thay i ca tn hiu thuc sensitivity list . Tt c cc tn hiu c tham chiu trong phn mch t hp cn phi thuc trong danh sch sensitivity list . Xem v d sau:
PB CLK FF Q1 FF Q2

PB.Pulse

Entity PULSER is port ( CLK, PB : in bit; PB_PULSER : out bit ); end PULSER; architecture BHV of PULSER is signal Q1, Q2 : bit; begin process ( CLK, Q1, Q2 ) begin if ( CLK'event and CLK = ' 1' ) then Q1 <= PB; Q2 <= Q1;

end if; PB_PULSE <= ( not Q1 ) nor Q2; end process ; end BHV;

3.11.6. Cc thanh ghi.

C rt nhiu kiu thanh ghi m chng c s dng trong mt mch. V d sau y s ch ra mt thanh ghi bn bit m chng c t tr c khng ng b v tr " 1100 ".
Dout (3)
Q S D S D D

Dout (2)
Q

Dout (1)
Q R

Dout (0)
Q R D

CLK ASYNC Din (3) Din (2) Din (1) Din (0)

signal CLK, ASYNC : Bit; signal Din, Dout : Bit_vector ( 3 downto 0 ); process ( CLK, ASYNC ) begin if (ASYNC = '1' ) then Dout <= " 1100 "; elsif ( CLK'event and CLK = '1' ) then Dout <= Din; end if; end process ;

3.11.7. Thanh ghi dch.

Mt thanh ghi c kh nng dch cc bit thng tin hoc sang phi hoc

sang tri c gi l mt thanh ghi dch. Cu hnh logic ca thanh ghi bao gm mt lot cc Flip - Flop c ni tng vi nhau, u ra ca Flip - Flop ny c ni vo u vo ca Flip - Flop kia. Tt c cc Flip - Flop u nhn xung ng h chung nn n c th lm cho d liu dch t trng thi ny sang trng thi tip theo. Xt v d v thanh ghi dch 4 bt sau: signal CLK, Din, Dout : Bit ; process (CLK) variable REG : bit_vector ( 3 down to 0 ); begin if ( CLK'event and CLK = '1' ) then REG : = Din & REG ( 3 downto 1); end if; Dout <= REG (0); end process ; Cu hnh ca chng nh sau:

Din

Dout

FF CLK

FF

FF

FF

3.11.8. Cc b m khng ng b.
B m khng ng b l b m m trng thi ca n thay i khng b iu khin bi cc xung ng b ng h. Cch m t b m ny nh sau:

Count (0) 1 CLK T Q 1 T Q

Count (1) 1 T Q

Count (2) 1 T Q

Count (3)

FF

FF

FF

FF

RESET

signal CLK, RESET : Bit; signal COUNT : Bit_vector ( 3 downto 0 ); process ( CLK, COUNT, RESET ) begin if RESET = '1' then COUNT <= "0000"; else if (CLK' event and CLK = '1' ) then COUNT (0) <= not COUNT (0); end if; if (COUNT(0)' event and COUNT(0) = '1' ) then COUNT (1) <= not COUNT (1); end if; if (COUNT(1)' event and COUNT(1) = '1' ) then COUNT (2) <= not COUNT (2); end if; if (COUNT(2)' event and COUNT(2) = '1' ) then COUNT (3) <= not COUNT (3); end if; end if; end process ;

3.11.9. Cc b m ng b.
Nu tt c cc Flip - Flop ca b m c iu khin bi tn hiu clock chung th chng c gi l b m ng b. Cch vit chng nh sau: signal CLK, RESET, load, Count, Updown : Bit; signal Datain : integer range 0 to 15;

signal Reg : integer range 0 to 15: = 0; process ( CLK, RESET ) begin if RESET = '1' then Reg <= 0; elsif ( CLK'event and CLK = '1' ) then if ( Load = ' 1' ) then Reg <= Datain; else if (Cout = '1' ) then if Updown = '1' then Reg <= ( Reg +1) mod 16; else Reg <= ( Reg -1 ) mod 16; end if; end if; end if; end if; end process ;

3.11.20. Cc b m ba trng thi.

Bn cnh cc s 0 v 1, cn mt tn hiu th ba trong h thng s : l trng thi tr khng cao ( Z ). Trong cc kiu tin nh ngha ca cc ng gi chun khng c kiu no m t gi tr ca tr khng cao, v vy ta cn s dng kiu STD_LOGIC m t b m ny.

Library IEEE; use IEEE.STD_LOGIC_1164. all; architecture IMP of TRI_STATE is Signal Din, Dout, OE : STD_LOGIC; Begin process (OE, Din) Begin if ( OE = '0' ) then Dout <= ' Z '; else Dout <= Din; end if; end process ;

OE

Din

Dout

3.11.21.M t Bus.
Mt h thng Bus c th c xy dng vi cc cng ba trng thi thay v cc cng multiplexers. Ng i thit k phi m bo khng c nhiu hn mt b m trng thi kch hot ti bt k thi im no. Cc b m kt ni cn phi c iu khin v vy ch c b m ba trng thi truy cp ng Bus trong khi cc b m khc duy tr trng thi tr khng cao. Thng th ng cc php gn tn hiu tc th, chng hn nh cc ng Bus trong v d d i y khng c php mc mt kin trc. Tuy nhin cc kiu d liu STD_LOGIC v STD_LOGIC_VECTOR c th c nhiu ng iu khin. library IEEE; use IEEE.STD_LOGIC_1164.all; Entity BUS is port (S : in STD_LOGIC_VECTOR ( 1 downto 0 ); OE : buffer STD_LOGIC_VECTOR ( 3 downto 0 ); R0, R1, R2, R3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); BusLine : out STD_LOGIC_VECTOR ( 7 downto 0 ) );

end BUS ; architecture IMP of BUS is Begin Process (S) Begin Case (S) is when " 00 " => OE <= "0001"; when " 01 " => OE <= "0010"; when " 10 " => OE <= "0100"; when " 11 " => OE <= "1000"; when others => null; end Case; end Process ; BusLine <= R0 when OE (0) = ' 1' else "ZZZZZZZZ"; BusLine <= R0 when OE (1) = ' 1' else "ZZZZZZZZ"; BusLine <= R0 when OE (2) = ' 1' else "ZZZZZZZZ"; BusLine <= R0 when OE (3) = ' 1' else "ZZZZZZZZ"; end IMP;
Bus Line
OE (0) OE (1) OE (2) OE (3)

S (0)

2 to 4

0 1

Decoder
S (1) 2 3

R0

R1

R2

R3

Cu trc ng Bus tm bit