HC VIN CNG NGH BU CHNH VIN THNG KHOA VIN THNG I

N TT NGHIP I HC
ti

FGPA v ng dng trong 3G W-CDMA

Gio vin hng dn : KS. Nguyn Vit m Sinh vin thc hin : L c Thun

nh hng ti
Nhu cu s dng thng tin v tuyn v di ng tc cao ngy cng tng nhanh S thnh cng ca cng ngh k thut mi ph thuc rt nhiu vo kh nng tch hp, hi t FPGA vi kin trc mm do, kh nng cu hnh li d dng, d thit k v kim tra. FPGA l mt la chn tt yu vo thi im hin nay p ng cc yu cu ca thit b
L c Thun Lp D2004VT2

NI DUNG
Tng quan FPGA
ng dng FPGA trong trm gc 3G ng dng FPGA trong b m TCC Kt Lun
L c Thun Lp D2004VT2

Tng quan FPGA

FPGA: Field programmable gate array. c thit k ln u tin bi Rossfreeman. ng dng vo cc lnh vc: Hng khng, v tr, x l s L s kt hp ca hai cng ngh PLDs v ASICs.

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Lp D2004VT2

Tng quan FPGA

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

c xySB dng theo dng tile i xng SB SB Mng li cc khi chuyn mch (SB)
SB SB

SB

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

SB

SB

SB

Logic Logic Cc khi vo ra SB Block

FGPA
Logic Block

Block

SB

Logic Block

SB

Logic Block

SB

SB

Knh dy dn, b nhn

Logic Block
SB

SB

SB

SB

SB

SB

Logic Block

SB

Logic Block

SB

Logic Block

SB

Logic Block

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Lp D2004VT2

Tng quan FPGA

Kin trc Virtex-II
ng h ghp knh DCM DCM

Cung cp cc tnh nng qun l ng h khc IOB nhau. Clock skew

Logic kh cu hnh

Cc cng vo ra kh lp trnh

Bn trong khi CLB Khi la chn RAM logic CLB c bng LUT v cc phn t nh.

Multiplier

L c Thun

Lp D2004VT2

Tng quan FPGA

JHDLBits
ADB
Thit k JHDL

Jbitscng c Cc TechMapper Xilinx ISE

Nets Dimensions Instances Placement Directives

VTsim B nh tuyn
ADB

Thit k JHDL

Lung Bit
(Bitstream)

B trch Jbits
-trch thng tin hnh gc

B sp t
(Placer)

Builder

So snh kt qu

JHDLBits

VTsim

-create Jbits ULPrimitives

JBits

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Lp D2004VT2

FPGA v ng dng trong trm gc 3G

phc tp ca thit b tng theo yu cu ca trm gc

phc tp ca thit b
1G 2G 3G
Nn tng h thng kh lp trnh Nn tng FPGAs
Khi chc nng mc h thng
DLLs High Part.VO Khi RAM B nh phn tn PowerPC RocketIO

Glue Logic
XC 2000-XC 3000

IP Immersion 840 Mbps LVDS TripleDES XCITE Multiplier DCM

XC 4000, Virtex

Virtex-II

Virtex-II Pro

1985
L c Thun

1992

2000

2002

2004
Lp D2004VT2

FPGA v ng dng trong trm gc 3G

Gii hn v hiu sut ca DSP ban u

Kin trc c nh khng linh hot
D liu vo

Reg

Ch c 1-4 khi MAC

Bng thng c nh
Thut ton lp 256 ln Khi MAC

Gii hn thng lng d liu Chia s thi gian lm vic

D liu ra

Tn s xung clock cng cao tc cng ln

Lp D2004VT2

L c Thun

FPGA v ng dng trong trm gc 3G

u im ca FPGA
D liu vo Reg0 Reg1 Reg2 Reg255 C0 C1 C2 C255

Thc hin 256 MAC trong mt chu k clock D liu ra

Kin trc mm do

X l song song v ni tip

L c Thun Lp D2004VT2

FPGA v ng dng trong trm gc 3G

S my pht 3G
Reference)
M nh knh (OVSF) Polyphase RRC and Halfband Filter

Multiply

CRC

CRCTurbo/ M ha xon

B trn

NCO p/2 M trn Polyphase RRC and Halfband Filter

DAC

Reference)

L c Thun

Lp D2004VT2

FPGA v ng dng trong trm gc 3G

S my thu 3G
FPGA Phn mm iu khin nhng
Filtering DownConversion B phn tp anten B d a ngi dng

RFFE

Beam Former

My thu RAKE

Gii m FEC

B x l DSP

Matched Filter

De-spread

Channel estimation maximum ratio combining Equal ratio combining

Acquire Tracking

Chc nng iu khin v giao din h thng

Backplane
LVDS PCI Gigabit Serial

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Lp D2004VT2

FPGA v ng dng trong trm gc 3G

My thu RAKE
Mt s kin trc c xut Tracking Rake fingers Phn chia v iu khin Rake fingers Hiu qu cao trong a knh

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Lp D2004VT2

FPGA v ng dng trong trm gc 3G

Lc tch sng a ngi dng

rtrain (n) Channel trainbaseband model

train train b (n)

Channel basebend model

b1train (n) b1train (n)

Du
w
1

y 1 ( n)
( n)

y 1 ( n) 1(n)

r
r(n)

Ly du 1
Du
w
k

train k

1
Ghp ni

bktrain ( n)

+
train K

y k ( n)
( n)

v D k

y k ( n) k(n)

b1

train bK ( n)

Ly du K
Du
w
K

y K ( n)

Khi ly du
(a)

D
K Khi d

y K (n) K(n) K

(b)

L c Thun

Lp D2004VT2

FPGA v ng dng trong trm gc 3G

Input Buffer rtrain
Local control Local control Local control
PELMS #1 Signature stage PELMS #TMUX1 Signature stage PELMS #N1-TMUX1+1 Signature stage

Local control Local control Local control

PELMS #NMUX1 Signature stage

a ch tng qut

Semiglobal Memory (w) #1

Semiglobal Memory (w) #NMUX1

Output Buffer
Local control Local control

B nh ngoi (SDRAM)

B nh ngoi (SDRAM)

Serial2ParallelFIFO

Parallel2SerialFIFO

Array of PE (detection stage)

Array of PE (signalture stage)

B m bn trong

B m u vo

B m u ra

PEFIR #1 Signature stage

PEFIR #TMUX2 Signature stage

Local control

PEFIR #N2-TMUX2+1 Signature stage

PEFIR #NMUX2 Signature stage

Inter Buffer Inter Buffer

Local control Local control Local control Local control

iu khin ton cc iu khin b nh ngoi

PELMS #1 detection stage

PELMS #TMUX2 detection stage

PELMS #N2-TMUX2+1 detection stage

PELMS #NMUX2 detection stage

Semiglobal Memory (v) #1

Semiglobal Memory (v) #NMEMV

Local control

Local control

PEFIR #1 Signature stage

PEFIR #TMUX1 Signature stage

Local control

PEFIR #N1-TMUX1+1 Signature stage

PEFIR #NMUX1 Signature stage

Inter Buffer r

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Lp D2004VT2

FPGA v ng dng trong trm gc 3G

Phn vng h thng

Phn vng Mips cao

Phn vng MIPs thp Phn vng qun l h thng

L c Thun Lp D2004VT2

FPGA v ng dng trong trm gc 3G

X l tn hiu vi tc cao

Kim tra li ng truyn (FEC)

Chc nng bc cu v iu khin

Giao din thch ng vi cc h thng khc nhau

L c Thun Lp D2004VT2

FPGA v ng dng trong b m TCC

B m ha TCC
Mandatory Pins CLK FD_IN Data_IN Block_Size RSC1-SYSTEMATIC RSC1-PARITYO RSC2-PARITYO RSC1_TAIL RSC2_TAIL RDY RFFD RFD RSC2_SYSTEMATIC RSC1_PARITY1 RSC2_PARITY1 BLOCK_SIZE_VALID EXT_IADDR_CE MEM_DINA MEM_ADDRB MEM0_ENA MEM0_ENB MEM0_WEA MEM0_ADDRA MEM1_ENA MEM1_ENAB MEM1_WEA MEM1_ADDRA Multi-bit Signal Single-bit Signal

RSC1_Systematic

XK

Optional Pins ND FFD_IN ALCR SLCR CE EXT-IADDR EXT-IADDR-RFFD EXT-IADDR-RDY

Tr

RSC1
Systematic(X)

RSC1_Parity 0 RSC1_Parity 1

ZK WK
Puncturing (external to core)

+ +

Parity0(Y0)

Punctu Outpu

RSC2_Systematic

MEM0-DOUTA MEM0-DOUTB MEM1-DOUTA MEM1-DOUTB

Parity1(Y1)

XK ZK WK

B trn

RSC2

RSC2_Parity 0 RSC2_Parity 1

u vo Bit(X)

+
SW 1

Tr

Tr

Tr

L c Thun
X(D)=1 Y (D) =

+
1 D D3
Y (D) =

1 D D2 D3

Lp D2004VT2

FPGA v ng dng trong b m TCC

B gii m TCC
kt hp vi b m ha TCC cung cp mt phng php hiu qu trong truyn dn d liu tin cy trn cc knh d liu nhiu,

L c Thun

Lp D2004VT2

FPGA v ng dng trong b m TCC

L c Thun

Lp D2004VT2

FPGA v ng dng trong b m TCC

L c Thun

Lp D2004VT2

FPGA v ng dng trong b m TCC

L c Thun

Lp D2004VT2

Kt lun
Tm hiu tng quan v FPGA

ng dng FPGA trong trm gc 3G W-CDMA

ng dng FPGA trong b m ha v gii m TCC

FGPA l gii php ti u vo thi im hin nay p ng cc yu cu v thit b, lm cho kh nng trin khai cc thut ton, gii thut mi c a vo thc t.
L c Thun Lp D2004VT2

XIN CHN THNH CM N !

6/12/2008

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