VHDL

- VHDL l ngn ng m t phn cng.

- VHDL vit tt ca VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

- VHDL khng phn bit ch vit hoa v ch thng.

databus Databus DataBus DATABUS

-VHDL l ngn ng nh dng t do.

if (a=b) then If (a=b) then

if ( a =
b) then

Thut ng COMPONENT:
- L khi nim trung tm m t phn cng bng VHDL biu

din cc cp thit k t cng n gin n 1 h thng phc tp.

- M t component bao gm ENTITY v ARCHITECTURE.

- Mt component c th s dng cc component khc.

V d: M VHDL m t component NAND 2 ng vo

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;
ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

LIBRARY

LIBRARY ieee;

USE ieee.std_logic_1164.all;
- LIBRARY: khai bo th vin ieee - USE: s dng cc nh ngha gi (package) std_logic_1164

ENTITY

M t cc tn hiu xut/nhp ca khi component

ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate;

- ENTITY: t tn cho entity (nand_gate) - PORT: khai bo cc chn xut/nhp * Tn port (portname): a, b, z * Kiu port (mode): IN, OUT * Kiu tn hiu (type): STD_LOGIC

* Cc kiu chn PORT I/0

IN: d liu i vo entity qua port v c th c c trong entity.

OUT: d liu xut ra ngoi entity qua chn port.

Port OUT khng th c v li entity.

INOUT: l port 2 chiu, cho php d liu i vo hoc ra.

BUFFER: tng t port OUT, nhng c php c li bi entity.

ARCHITECTURE
M t thit k bn trong ca khi, ch r mi quan h gia cc

ng vo v ng ra.

ARCHITECTURE: t tn cho architecture (model)

C 3 loi m t architecture * M t cu trc (Structural)

* M t lung d liu (Dataflow)

* M t hnh vi (Behavioral)

EX: B gii m 2 sang 4, ng ra tch cc mc 1, ng vo cho php tch cc mc 1. LIBRARY ieee;

USE ieee.std_logic_1164.all; ENTITY dec2x4 IS PORT ( en : IN STD_LOGIC; x : IN STD_LOGIC_VECTOR(1 downto 0); y : OUT STD_LOGIC_VECTOR(3 downto 0)); END dec2x4; ARCHITECTURE flow OF dec2x4 IS SIGNAL temp: STD_LOGIC_VECTOR(3 downto 0); BEGIN WITH x SELECT temp <= 0001 WHEN 00 , 0010 WHEN 01 , 0100 WHEN 10 , 1000 WHEN 11 , 0000 WHEN OTHERS; y <= temp WHEN en = 1 ELSE 0000; END flow;

EX (Cch 2): B gii m 2 sang 4, ng ra tch cc mc 1, ng vo cho php tch cc mc 1.

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2x4 IS PORT ( en : IN STD_LOGIC; x : IN STD_LOGIC_VECTOR(1 downto 0); y : OUT STD_LOGIC_VECTOR(3 downto 0)); END dec2x4; ARCHITECTURE flow2 OF dec2x4 IS SIGNAL en_x: STD_LOGIC_VECTOR (2 downto 0); BEGIN en_x <= en & x; WITH en_x SELECT f <= 0001 WHEN 100 , 0010 WHEN 101 , 0100 WHEN 110 , 1000 WHEN 111 , 0000 WHEN OTHERS; END flow2;;

B gii m led 7 an
PROCESS(bcd)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

BEGIN CASE bcd IS abcdefg WHEN "0000" => segs <= "1111110"; WHEN "0001" => segs <= "0110000";
WHEN "0010" => segs <= "1101101";

ENTITY led IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 downto 0); segs : OUT STD_LOGIC_VECTOR(6
downto 0);

WHEN "0011" => segs <= "1111001"; WHEN "0100" => segs <= "0110011"; WHEN "0101" => segs <= "1011011"; WHEN "0110" => segs <= "1011111";
WHEN "0111" => segs <= "1110000";

END led; ARCHITECTURE Behavioral OF led IS BEGIN PROCESS(bcd)

WHEN "1000" => segs <= "1111111"; WHEN "1001" => segs <= "1111011"; WHEN OTHERS => segs <=

"0000000";-- ALL OFF

END CASE;

END PROCESS; END Behavioral;

MCH CHT

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Dlatch IS PORT (D, Clk : IN STD_LOGIC; Q, Qn : OUT STD_LOGIC); END Dlatch; ARCHITECTURE behavior OF Dlatch IS BEGIN PROCESS (D, Clk) BEGIN IF Clk = 1 THEN Q <= D; Qn <= NOT Q; END IF; END PROCESS; END behavior;

FLIP-FLOP

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Dflipflop IS PORT (D, Clk : IN STD_LOGIC; Q, Qn : OUT STD_LOGIC); END Dflipflop; ARCHITECTURE behavior OF Dflipflop IS BEGIN PROCESS (Clk) BEGIN IF Clkevent AND Clk = 1 THEN Q <= D; Qn <= NOT Q; END IF; END PROCESS; END behavior;

- clkevent pht hin s thay i tn hiu clk t 0 ln 1 hoc t 1 v 0.

- Gi std_logic_1164 c nh ngha 2 hm (function): rising_edge

pht hin cnh ln v falling_edge pht hin cnh xung ca tn

hiu.

FLIP-FLOP

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY DFF IS PORT ( D, Clk, Pr, Cl : IN STD_LOGIC; Q, Qn : OUT STD_LOGIC); END DFF; ARCHITECTURE behavior OF DFF IS BEGIN PROCESS (Clk, Pr, Cl) BEGIN IF Pr = 0 THEN Q <= 1; Qn <= 0; ELSIF Cl = 0 THEN Q <= 0; Qn <= 1; ELSIF Clkevent AND Clk = 0 THEN Q <= D; Qn <= NOT Q; END IF; END PROCESS; END behavior;

MY TRNG THI (FSM)

- My trng thi hu hn c thit k d dng bng pht biu

PROCESS.
- Vic chuyn trng thi c m t trong Process vi danh sch cm nhn (sensitivity list) l clock v tn hiu reset bt ng b. - Ng ra c th c m t bng cc pht biu ng thi (concurrenrt) nm ngoi process.

- C 2 kiu FSM: MOORE v MEALY

Present State Register: thanh ghi trng thi hin ti lu gi 1 trng thi hin ti, s chuyn trng thi khi c xung clock.

Next state function: hm trng thi k tip l mch t hp ph thuc vo

ng vo v trng thi hin ti. Output function: hm ng ra l mch t hp ph thuc vo trng thi hin ti