School of Electric Information, Zhongyuan University of Technology, China.
* Department of Electrical and Computer Engineering, National University of Singapore, Singapore Emailweipingjun@yeah.net AbstractMedian filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 33 filtering windows mathematical model, this paper proposes a fast median filtering algorithm based on field programmable gate array (FPGA) and the scheme design. According to the characteristics of parallel structures and its suitable for pipeline design of FPGA. VHDL and schematic design are used in this paper to design the implement circuit. Quartus II is used for timing simulation. The results show that it can filter the impulse noise in real time and improves the quality of image. Key words image processing; fast median filtering; FPGA; VHDL; schematic; Quartus II . INTRODUCTION It is well know that images may be contaminated with noise in the process of collection, processing and transmission. Therefore, image denoising is an important part of image processing [1]. As a spatial filtering technique, median filter algorithm, compared with other filtering algorithms such as the mean filter, can effectively eliminate impulse noise, salt and pepper noise, and keep the image's edge information, which makes the image not to become too vague. Images preprocessing algorithm need to process very large amount of data. Software implementation will be time consuming. For some systems requiring real-time processing, implementation speed is often considered as a key factor, so the image preprocessing algorithm is suitable to be implemented in hardware. Field programmable gate array (FPGA) is suitable for pipelining and parallel data processing. Whats more, although the median filtering algorithm processes large amount of data, but it does not require to stores a lot of intermediate data, and has the following properties: simple in computing and reproducible, thus it is suitable to be implemented using FPGA . In this paper, we make some improvements to the conventional median filtering algorithm by adding a comparison threshold to further enhance the median filter characteristics of preserving image detail [2]. . THE PRINCIPLE OF FAST MEDIAN FILTERING ALGORITHM The core of median filtering algorithm is sorting. Sorting algorithm directly determines the efficiency of obtaining intermediate values, and then determines the overall performance of the filtering. Traditional median filtering algorithm uses bubble sort method, the time of processing is long, and it consumes large amounts of hardware resources. According to the rich hardware resources of FPGA and the advantages of parallel processing, this paper uses a fast parallel median filtering algorithm [3]. This algorithm improves the traditional sorting methods using parallel processing and pipeline design, avoids the extensive comparative operations. This design not only decreases large amount of operations, it also occupies fewer hardware resources of FPGA. Therefore, the processing speed is faster than traditional median filter algorithm. The algorithm details are described as follows: Denote the pixel data of 3x3 two-dimensional lCSP2010 Proceedings
window as follows: P0, P1, P2, P3, P4, P5, P6, P7, P8. Window of pixels is arranged as shown in Table 1. Table 1 3*3 window of pixels arrangement Column 1 Column 2 Column 3 Row 1 P0 P1 P2 Row 2 P3 P4 P5 Row 3 P6 P7 P8 There are three steps to realize the algorithm. Denote max as to operation of obtaining the maximum value, med as to operation of obtaining the median value and min as to operation of obtaining the minimum value. First step: sorts the pixel data of each row to obtain the maximum, median and minimum values. The ordering process can be processed in parallel. Denote the maximum, median and minimum values of the first row of pixels as Max_Rowl=max [P0, P1, P2], Med_Rowl=med [P0, P1, P2] and Min_Rowl = min [P0, P1, P2]. The second and the third rows are ordered similarly. After 3 times comparison of per row (a total of 9 times comparison), the maximum value group, the median value group and the minimum value group are obtained and shown as follows: Maximum group: Max = [Max_Rowl, Max_Row2, Max_Row3] Median Group: Med = [Med_Row1, Med_Row2, Med_Row3] Minimum group: Min = [Min_Rowl, Min_Row2, Min_Row3] Second step: Process the data obtained from the three groups in parallel. Denote the minimum value of the maximum group as Max_min (min(Max)), the intermediate values of the median group as Med_med (med(Med)), the maximum value of the minimum group as Min_max (max(Min)). It needs 7 comparisons to obtain the three values. Third step: Find the median value Final_med from the remaining three values Max_min, Med_med and Min_max,which, which will be the final median results to be obtained. This step needs to go through three times comparisons. The median value is obtained after 19 comparisons of the 3x3 window data. To sort the nine pixels data of the 3x3 window, the value should be the fifth number, which is characterized by up to 4 numbers larger than it, up to 4 smaller than it. This algorithm discards the data does not meet this requirements by logic. This algorithm does not be affected if there are same numbers. The traditional bubble method needs to do a total of 9 * (9-1) / 2 = 36 times comparisons to sort the 9 data. From the above analysis, the fast median filtering algorithm does not order all the nine pixels, but using concise comparison operation to obtain the output of the median value of 9 pixel values. At the same time, the fast median filtering algorithm use parallel sorting, makes full use of the hardware resources of FPGA. The times of comparisons reduce to 19, while the time of comparison is reduced to 3 clock cycles. So fast median filtering algorithm significantly improves the processing speed, greatly improved the efficiency of image processing [4]. . IMPLEMENTATION OF FAST MEDIAN FILTERING WITH FPGA FPGA is a kind of programmable logic devices based on the structure of lookup table. It brings great convenience to the electronic design, which also has been widely used in real-time image processing. FPGA has a large number of flexible logic cells, has the characteristics of online programming and high-speed parallel structural so that it can replace discrete components, small and medium-scale logic circuits and is becoming the mainstream of electronic design and development [5]. The flow chart of the fast median filtering algorithm is shown in Figure 1. This paper uses two methods, VHDL text and schematic to implement the circuit design. 427 Fig.1 The flow chart of the fast median filtering algorithm A. VHDL text method VHDL language is a high-level circuit design language, and has the properties of powerful and flexible. It can describe multi-level design. The inner layers are refinement of the outer layers. Circuit-level descriptions are generated at last. The source codes of comparator COM_P for the comparison of three data are as follows: IF (a<=b AND a<c AND b<c) THEN min<=a; med<=b; max<=c; ELSIF (a<b AND a<=c AND c<b) THEN min<=a; med<=c; max<=b; ELSIF (b<a AND b<c AND a<=c) THEN min<=b; med<=a; max<=c; ELSIF (b<a AND b<=c AND c<a) THEN min<=b; med<=c; max<=a; ELSIF (c<a AND c<b AND a<=b) THEN min<=c; med<=a; max<=b; ELSIF (c<a AND c<=b AND b<a) THEN min<=c; med<=b; max<=a; ELSIF (a=b AND a=c) THEN min<=a; med<=b; max<=c; END IF; Then we use components to achieve the pipe line design for the six data comparator: u11:cmp_3 PORT MAP (clk=>clock, a=>p0, b=>p1, c=>p2, min=>s0, med=>s1, max=>s2); u12:cmp_3 PORT MAP (clk=>clock, a=>p3, b=>p4, c=>p5, min=>s3, med=>s4, max=>s5); u13:cmp_3 PORT MAP (clk=>clock, a=>p6, b=>p7, c=>p8, min=>s6, med=>s7, max=>s8); u21:cmp_3 PORT MAP (clk=>clock, a=>s0, b=>s3, c=>s6, max=>k0); u22:cmp_3 PORT MAP (clk=>clock, a=>s1, b=>s4, c=>s7, med=>k1); u23:cmp_3 PORT MAP (clk=>clock, a=>s2, b=>s5, c=>s8, min=>k2); u33:cmp_3 PORT MAP (clk=>clock, a=>k0, b=>k1, c=>k2, med=>median); As the time of operations carried out by the comparator is too many, in order to avoid possible occurrence of logical confusion, some registers among all levels of three-point comparator can be added [6]. Compilation and simulation can be obtained using the Quartus II. The results are shown in Figure 2. Fig.2 The circuit timing simulation waveforms of VHDL source code method B. Schematic method At first, we build a three-point comparator, which is the basis for processing the following image data. According to the feature of rich resources of internal registers in FPGA, the design uses pipelining method to implement three-point comparator. The schematic of the three-element comparator is shown in Figure 3. Fig.3 The schematic of three points comparator module Fast median filtering algorithm module consists of seven three-point comparator modules. The top-level hardware diagram is shown in Figure 4. 428 According to the characteristic of the common 3 3 template mathematical model of median filter, this paper proposes a fast algorithm to obtain the median value, where the comparison operations are finished with FPGA look-up table. As the logical processing time delay achieved by look-up table is fixed, processing can be implemented with high speed. The system has the following properties: fulling use of the FPGA's parallel features, simpling system hardware structure, high integration, high reliability, fixed timing delay and predictable, therefore, this design is real-time and reliability. Fig.4 The top-level hardware diagram of fast median filtering algorithm module We use Quartus II to compile and simulate the hardware circuit, the result is shown in Figure 5. REFERENCES [1] Dong Hanlei, Xu Liping, Gao Yingmin, Image denoising based on Bior wavelet transform and median filtering, Communication technology, vol.42, no.11, pp.171,2009. [2]Li Feifei, Liu Weining, The improvement and fast implementation of median filtering algorithm with FPGA, Computer Engineering, July, vol.35, no.14, pp.175, 2009. [3]Wang Wei, Yang Bing, The Design and Implementation of Fast Median Filtering Algorithm based on FPGA, Electronic components applications, Jan. vol.10, no.1, pp.57, 2008. Fig.5 The circuit simulation charts of Schematic method Analysis of the two simulation diagrams shown in Figure 2 and Figure 5 shows that both the two methods of design of fast median filtering algorithm implement the requirement of obtaining the median value. Therefore, it can remove impulse noises very effectively, especially the salt and pepper noise, and almost does not affect the edge. [4]Wang Jingcun, Zhang Jie, Digital Image Processing baesd on FPGA, Master thesis of Wuhan University of Technology, May, 2009. [5] XU Dapeng, Li Congshan, The Design of Digital Image Median Filter Based on FPGA, Electron Devices, Dec. vol.29, no.4, pp.1114, 2006. [6] Pan Song, Huang Jiye, EDA Technology Practical Course (The Third Edition), Beijing: Publishing House of Science, 2006. . CONCLUSION 429