]<gj]<]<j<^]<]

? ? ? ?
K

KKK

K
K

KKKKKK


]<gj]<]<j<^]<]

W
K

K
K

 IntroductionJ

(Binary Number System) K

K(Digital Electronic Circuits)

K(Decimal Number System)

K(Hexadecimal Numbering System)

(Octal Number System)

K
K
W

KK

KK
KK
KK

KK
(Digit)

(Symbol)(Number)

({{{{, ... , {)

()()

()()
()()()
K

 Decimal Numbering SystemJ

()K

()
K{{{{{{{{{

()(Positional Weight)

E F()
()( = )

E
F
E
FEF( = )

K( = )

( ) + ( ) + ( ) = + + =

EF
W =
........

() =

()
K(Subscript)

........

(Decimal Point)

Binary Numbering SystemJ

()()

.()
.....

.....

W()

W()

= ( ) + ( ) + ( ) + ( ) + ( )
= + + + + = ()

()
K()

(Binary Digit)(Bit) W(Bit)

E
FK

()(-bits)()

K(-bits)

 W(Number of Binary Combinations)

K(bits)
W

N = 2 n

= N W
(bits)= n

W()

N= =
N = =

N = =

W()
W()

K
W(Bit)
()()

()

K()

(LSB)(Least Significant Bit)

K(MSB) (Most Significant Bit)

(Bit)WEByte)

()

E F()

(Byte)

byte = bits

WK

Decimal-to-Binary Conversion J


()(Sum of Weights Method)
(Repeated Divisionby Method)
K

J J
()

.()
K

(MSB)(LSB)

=
=
=
=

(MSB)
() = ()

(LSB)

K()WEJ F

=
=
=
=
=

(LSB)

(MSB)

() = ()

K()WEJ F
W

=
=
=
=
=
=
=

(LSB)

(MSB)

() = ()

J J

(Decimal Fractions)K()
K()

()

()()

(Carried Digits)K ()

K(LSB)(MSB)K
W

(LSB) (MSB)

K()WEJ F

W()W

=
=
=
=
=
=

(LSB)

(MSB)

W()

() = ()

=
=

() = ()
() = ()

W
W

Binary-to-Decimal Conversion J
()

K, , , ,

()(Bit)
K

W

KWEJ F

()W

:
:

= + + + + + +
= + + + = ()

(Bits )
(Binary Point)

(Decimal Point)

-.

K()WEJ F
-

() = - + - + - = + + = ()

 Binary Arithmetic J

KK

Binary Addition J J

+
+
+
+

=
=
=
=

carry EF =

W(Binary Digits)

()() + =
WK
K, WEJ F

WW

+
EF

K, WEJ F

+
EF

Binary Subtraction J J
W

KJ
KJ

EF
=

=
=
=

() ()

W
K()()()()()
K()()()

F()()()()
K()()()E

K()()WEJ F

()()
()
()()
()

One's and Two's Complements of Binary Numbers

K

K
()()()()

()K W

W
+Z

K
K()

()

(LSB)W

()

W()

Representation of Signed NumbersJ

()()

K
(Sign Bit)
.(Magnitude)

W

.('s Complement) ('s Complement) (Sign-Magnitude)
(Sign-Magnitude System) J J

(Bit)

(+)K
W

(Sign Bit)

(Magnitude Bits)

W ( -)

K() (+)
('s Complement System) J J

()
K

(+)

()

('s Complement)J J

K
K
W(+)(-)

(+)

(-)

K
Arithmetic Operations with Signed NumbersJ

KEJ F

KWEJ F

WW

( ) = + =

(H)

(H)
(H)

WWEJ F

() ()

WW

= + (-) =

(Discard carry)

(H)

( )
(H)

KWEJ F

() ()

WW

 (+) = = -

( )

( )
( )

(Discard carry)

The Octal Numbering SystemJ

()()

()

Octal-to-Decimal Conversion J J

()

K(... )

()K

W
:

() = ( ) + ( ) + ( ) + ( )
= ( ) + ( ) + ( ) + ( )
= + + + = ()
DecimaltoOctal Conversion J J

()
K()()

J J J

()
()

()
.()
K

{Most Significant Digit} {Least Significant Digit} (LSD)

W(MSD)

=
=
=

(LSD)

(MSD)

() = ()

K()WEJ F

=
=
=
=

(LSD)

(MSD)

() = ()

J J J

()K()

()

()()

K
( Carried Digits)K

(MSD)
(LSD)

=
=
=
=
=
=

(MSD)

(LSD)
W()
() = ()

 K()WEJ F
K() W

=
=

(LSD)
(MSD)

() = ()

W()

=
() = ()
() = ()

W
W

 Octal-to-Decimal Conversion

J J

()

K, , , ,

(Digit)

K

K

K()WEJ F
W
:

() = ( ) + ( ) + ( )
= ( ) + ( ) + ( )
= + + = ()

(Octal Point)

-.

K()WEJ F

: - -

() = ( ) + ( ) + ( ) + ( -) + ( -)
= ( ) + ( ) + ( ) + ( ) + ( )
= + + + + = ()

Octal-to-Binary Conversion J J

 (Digit)
K
(-bits)
KEJ F

KEJ F

K
K()WEJ F
() =

= ()

K()WEJ F
() =

= ()

K
Binary-to-Octal Conversion J J

J
K

K
K()WEJ F

() = ()

Arithmetic Operations in Octal System

J J

Octal Addition J J J

()

()()()

K
() ()

()()
(, , , , , , )()

K (, , ..... , )(, , ...... , )

EJ F

K()

()()

()()()

()()
F
KE

KEJ F

K() ()WEJ F

WW

() + () = ()

()()()
K

 K()()WEJ F
W

+

()()

K(Carry)

Subtraction in Octal SystemJ J J

()
()
K

() ()

WWEJ F

WW

() () = ()

K
() ()WWEJ F

() () = ()

()()
()
K()()

J
()
Hexadecimal Numbering System

(,A,B,C,D,E,F) ()
K(, , , , , )(A,B,C,D,E,F)
HexadecimaltoDecimal ConversionJ J

...

)( )

W()(

: - -
:

() = ( ) + ( ) + ( ) + ( -) + ( -)
= ( ) + ( ) + ( ) + ( ) + ( )
= + + + + = ()

K
K ()

Decimal-to-Hexadecimal Conversion J J

()

.()()()

J J J
()()
()

K()
K

W(MSD)(LSD)

=
=

(LSD)
(MSD)

() = ()

K()WEJ F

=
=
=

(LSD)

(MSD)

() = (A)

J J J

()K()

()

()()
K

(MSD)(LSD)K

=
() = (.C)

 K()WEJ F
WW

=
=
=

(LSD)

(MSD)

() = ()

W()

=
=
=
=
=
=

(MSD)

E
B
(LSD)

W()
() = (EB)

() = (EB)

Hexadecimal-to-Decimal Conversion J J

K()
WK

K(FB)WEJ F
:
: F

(FB) = (F ) + ( ) + (B )
= ( ) + ( ) + ( )
= + + = ()

K(A.C)WEJ F
W

: - -
: A

(A.C) = (A ) + ( ) + ( ) + (C -) + ( -)
= ( ) + ( ) + ( ) + ( ) + ( )
= + + + + = ()
Hexadecimal-to-Binary ConversionJ J

(,,,A,B,C,D,E,F)

(A,B,C,D,E,F)
K()
(-bits)
WEJ F

K(A)WEJ F

(A)

= ()

A
B
C
D
E
F

KEJ F

K(B.D)WEJ F
(B.D) =

= ()
Binary-to-Hexadecimal Conversion J J

K
K()WEJ F

() = (BD.A)
K()WEJ F

() = (AB.)
Hexadecimal-to-Octal Conversion J J

K(ABE.D)WEJ F

WW

(ABE.D) = ()

K
(ABE.D) = ()
Octal-to-Hexadecimal Conversion J J

K()WEJ F

WW

() = ()

K
() = ()

J J

Arithmetic Operations in Hexadecimal System

K
Hexadecimal AdditionJ J J

(F)(,F)

()()

(B)()(A)()
K(F)

()(F)

()(F)
K

EJ F

F
F

E
E
F

D
D
E
F

C
C
D
E
F

B
B
C
D
E
F

A
A
B
C
D
E
F

A
B
C
D
E
F

A
B
C
D
E
F

A
B
C
D
E
F

A
B
C
D
E
F

A
B
C
D
E
F

A
B
C
D
E

A
B
C
D

A
B
C

A
B

A
B
C
D
E

A
B A
C B A
D C B A

E
F

D
E
F

C
D
E
F

B
C
D
E
F

B
C
D
E
F

KEJ F

WWEJ F

(AB) + (A)

KW

(AB) + (A) = ()
Hexadecimal SubtractionJ J J

()

WWEJ F

(FABD) (EFCE)

W
E
F
E

A
B
C
E

D
E
D

a)

b)

e) {

WE
c)

f) {

a)

b)

e) {

d) {

g) {

WE
c)

f) {

d) {

WE

a) +

b) { + {

c) +

d) { + {

a)

WE
b)

c)

a)

d)

b)

a)

WE

b)

c)

WE
c)

E
a) H

b)

c) H

W(-bits)
d)

E
a) H

b)

c) H

W(-bits)
d)

 KEFE

WE

a)

b)

c)

WE

a)

b)

c)

WE

a)

b)

c)

WE

a)

b)

c)

a)

d)

WE

b)

e) { f) {

a)
e) {

c)

d) {

g) {

b)
f) {

a)

b)

e) {

f) {

WE
c)

d) {

g) {

WE
c) {

d) {

g) {

WE

a) {

b) {

d) {

e) {

c) {

WE
a) () + ()

b) () + ()

c) () + ()

d) () + ()

 WE
a) () ()

b) () ()

c) () ()

d) () ()

WE

a)

b)

e)

f) {

d)

g) {

h) {

WE

a) F

b) D

e) F.

f) B.E

a)

c)

c) F

g) {

d) F.C

c) A

e) {

WE

a) {

b) {

d) {

e) {

e) .D

h) {

WE

b) C

a) A

d) ABCD

b) E

f) .F

a)
e) {

b)

c) {

f) {

WE

c)

d) B.C

WE

c) {

d) {

f) {

WE
a) () + ()

b) (C) + (A)

c) (B) + ()

d) (D) + (E)

f) (CB) + (AF)

g) (EFD) + (BB)


]<gj]<]<j<^]<]

--

K
K

K
K

K
K

- -

Introduction J

J J
J

? ?
K

K(INVERTER)NOTORAND

Logic Signal LevelsJ

J

(LOW)()(HIGH)

()()
()(TRUE)
K(FALSE)
(Positive Logic)
() K(Negative Logic)
()()

K()
- -

AND Gate ANDJ

AND

ANDK(Logic Functions)
(Logical Multiplication)
A, BEJ F

()(Two Binary Variables)

K(Closed)()(Open)

(A)

(B)

(L)

Voltage Source

KANDEJ F

()"L"

K(OFF)()(ON)
EJ F

(L)K (L)

K(Truth Table)
A
B
L

KEJ F EJ F
- -

AND(Standard)EJ F
EJ FKANDYA, B
KAND

KANDEJ FKANDEJ F

()(bits)

AND
()A, B
K()()

N = 2n

N W
Kn

N = 2 2 = 4
N = 2 3 = 8
N = 2 4 = 16

WEJ F

KAND
AND

EJ FANDW
K
- -

A
B
C
Y

KANDEJ F

N = 2 n = 2 5 = 32

(Boolean Algebra)
(Boolean Expression)
WANDK
Y = AB

EAND FA AND BYW

W

Y = AB

KA AND BY

K(LOW)(HIGH)
(Pulses)
AND
K

()A, BEJ F

At()Yt
- -

()YB()
K

A
B

K(Timing Diagram)

t t t

t t

KANDEJ F
OR Gate OR J

K OR

OR
(Logical Addition)
A, BANDKEJ F

() (Open) ()

Voltage Source

K(Closed)

(A)

(B)

KOREJ F
EJ F

K(L)

- -

KEJ FEJ F

A, BOREJ F

KOREJ FKY

KOREJ FKOREJ F

()EJ F

()()
Y=A+B

WORK()

K(OR+)A OR BYW
OR

AND
K

t()A, BEJ F

At()Y
K()YB()
- -

B
t

KOREJ F

NOT Gate (INVERTER) EF NOT J

(Inversion)NOT

()K(Complementation)
K()()()

EJ FK NOT

KEJ F

KNOTEJ FKNOTEJ F

Y= A

barAnot AYW

KE A FA barY

NAND Gate NAND J

- -

AND(NOT AND)(NAND)
J F AND

ANDE
KNANDEJ FK

A
Y

KNANDEJ FKNANDEJ F

()()

() ()
NANDKAND
NOT,

WNANDOR, AND
Y = AB

NAND

K()()NAND

t()A, BEJ F

At()Y

()Y()B()
K

- -

B
t

KNANDEJ F

NOR Gate NOR J

OR(NOT OR)(NOR)
OR(NOT gate)
NORKNOREJ F
KEJ F

KNOREJ FKNOREJ F

()(Y)

() ()
K()

NANDNOR

KNOT, OR, AND

WNOR

Y= A+B
- -

A, B
NOREJ F
K(Y)NOR

KNOREJ F
Exclusive-OR Gate EF OR J
XOR-gate??OR

XORK EJ F
K

A
B

KXOREJ FKXOREJ F
(Y)( )XOR
()()A, B()
K()

ORXOR

()
XORA = B =

() ()

K
- -

Y = AB + AB

W
W

Y=AB

XORKBA
EJ FAND, OR, NOT

KXOR

A
B

KAND, OR, NOTXOREJ F

XOREJ F

A
B

t t

t t t

KXOREJ F

- -

Exclusive-NOR Gate EF NOR J

XNOR-gateNOR
KEJ FXOR

(Y)EJ F XNOR
()A = B = A = B = A, B()

()()

()
K

KXNOREJ FKXNOREJ F

Y = AB + AB

Y=A~B
XNORK ~

EJ FAND, OR, NOT

KXNOR

A
B

KAND, OR, NOTXNOREJ F

- -

A, BXNOREJ F

K(Y)XNOR

A
B

t t t

KXNOREJ F
Rules of Boolean Algebra J
EJ F
K

.
.
.
.
.

A
A
A
A
A

+ =A
=
+ A=A
A=A
=A

. A + =
. A = A
. A + A =
. A A =
. A + AB = A

KEJ F

A + = A :()

A=K()()A()OR
KA()A=KA()

K(A + = A)()OR
()ORA + = :()

OR()K()()A
- -

K ()
K(A + = ) ()()OR

()ANDA = :()

K ()A

()()AND

K(A = )

()ANDA = A:()
ANDA=(A)A
()ANDA=()

()AND
K()
K(A = A)
AORA + A = A:()
A = + = A = K
K + =

AW
A + A = 1 :()

A=K() A OR
K1 + 1 = 1 + 0 = 1A = K 0 + 0 = 0 + 1 = 1

ANDAA A = A:()

= A = = A = K
KAAND

A ANDA A A = 0 :()

A A()
K()AND()()

K
A = A :()

()()()A =
K

- -

W()():()
A + AB = A ( + B)
= A ( )
=A

The Boolean Expression for a Logic CircuitJ

K

WKEJ F
K AB A, B ANDK

K AC A ,C ANDK

K AB + AC AB, AC ORK
W

Y = AB + AC
A
B

B
A

AB

AC

KEJ F

KEJ FWEJ F

B+C

D( A + B )

B+C

- -

KEJ FEJ F
W

Y = D ( A + B ) + ( B + C)

Implementation of a Logic Circuit Using a Boolean Expression

WK

Y = AB(CD + EF)

(CD + EF) A, B
E,FAND C, D (CD + EF)
AND
KORANDAND
W
AND
NOT

OR

Y = A B (CD + EF)

AND

( CD + EF)

CD, EF

K
D

W AB(CD + EF)
K D NOTK

K CD, EF ANDK

K (CD + EF) ORK

KYANDK
- -

KEJ F
A
B

C
D

E
F

K AB(CD + EF) EJ F

Implementation of a Logic Circuit via a Truth Table

EJ FK
WK

Y = K
A = , B = , C = Y =

() AB C

()()
K ABC

KEJ F
- -

WORY = K

Y = AB C + ABC

ABC
ABC AND A, B, C

ORAND A, B, C
KY

NOTW

OR ABC ABC
AND A, C
ABC + ABC

KEJ F

A
B
C

K AB C + AB C EJ F

KEJ F WEJ F

- -

KEJ F
W
WOREFY =
Y = A BC + ABC + ABC

KEJ F

B
C

K A B C + ABC + AB C EJ F

Converting a Boolean Expression to a Truth Table

( = )K(or )
K( = )

(Y)()
K()

WWEJ F
Y = A B C + AB C + ABC + ABC

- -

(A, B, C) W
KEJ F
W

AB C = 000, ABC = 010, ABC = 110, ABC = 111

(Y)()
K(Y)()

A
B
C
Y

K Y = A B C + AB C + AB C + ABC EJ F

Simplification of Boolean Expressions Using Boolean algebra

E F

WWEJ F

Y = AB + A(A + C) + B(A + C)

WW
Y = AB + AA + AC + AB + BC

- -

WEFAAA
Y = AB + A + AC + AB + BC

WAB + AB = ABA + A = A
Y = AB + A + AC + BC

WA

Y = A(B + 1 + C) + BC

WA + =

Y = A + BC
Y = A + BC

WA = A

EJ F

EEFF
KEEFF
A
B
Y

B
C

EF

E F

KEJ FEJ F

KA, B, C

- -

WEJ F
K
Y = AB C + ABC + ABC + ABC

WW

Y = ( AB C + ABC) + ( ABC + ABC)

= AB( C + C) + BC( A + A )

W
Y = AB 1 + BC 1

Y = AB + BC

KEJ F

A
B
C
A
Y

B
Y
C

EF

E F

KEJ FEJ F

- -

A,BANDXE

KJ

A,BORXE
KJ

A,BNANDX E
KJ
A

J
- -

A,BNORX E

KJ

A,BXORX E
KJ

A,BXNORX E
KJ

KJ E
A
B
C

- -

WE

a) AB + AB
c) AB(C + D )

b) AB + AB + ABC
d) A + B[C + D(B + C )]

KE

A B

a) (A + B)C
c) A(AC + AB)

a) (A + B)(A + C)
b) (A + A )(AB + ABC )

WE

b) (A + B)( B + C)
d) A(A + AB)

WE
b) AB + ABC + ABCD + ABC DE
d) AB + (A + B)C + AB

- -


]<gj]<]<j<^]<]

W
K

KNORNAND

KNORNAND
K
K

- -

IntroductionJ

K


K

K()

KNORNAND

K(Kmap)K (Karnaugh-Map)

Demorgan's TheoremsJ

K
ORAND

W(bars)

A+B=AB

A B = A + B

ANDOR
ANDNOREJ F
K

KEJ F

K(negative AND)AND

--

A+B

AB

KANDOREJ F

+B
A

B
A

KEJ F
ORAND
ORNANDEJ F
EF
ORKEJ F

K(negative OR)
A

AB

A+B

KORANDEJ F

B
A

+B
A

KEJ F
--

K

K

WWEJ F

Y = (A + B + C) (A + B + C )

W
Y = (A + B + C) (A + B + C)
= (A + B + C ) + (A + B + C )
= A BC + A BC= ABC+ A BC

W WEJ F
Y = (A + B) + CD

Y = (A + B) + CD
= (A + B).CD
= (A.B)(C + D)
= A B(C + D)

NOR , NANDJ

The Universal Property of NAND and NOR Gates

AND

NORNANDKOR

K
(Universal Gates)
KNORANDNAND

NORNOR
KNANDORAND

--

NAND gate as a Universal Logic Element NANDJ J

ANDNAND

NANDKNOROR
KNANDEFJ

KEFJ NANDAND
NOR KEFJ NAND OR
KEFJ
A

EF

AB

AB = AB

AB

E F

A
A .B = A + B

A+B

EF
A

A .B = A + B
A+B

A
B

EF

KNANDEJ F
--

A+B

NOR Gate as a Universal Logic Element NORJ J

ORAND
NOR NAND

NOREJ FKNAND
KNANDORNOT

EF

A+B
A

A+B = A+B

A+B

E F
A

A + B = A .B

AB

EF

A + B = A .B
A

EF

KNOREJ F

--

A
B

AB

NORNANDJ

Design of Combinational Logic Circuits using NAND and NOR Gates

NORNAND

(Negative-OR)ORNAND

K(Negative - AND)ANDNOR
K (Logic diagram) ANDOR
NAND Logic NANDJ J

OR NAND NAND
W
A B = A + B

Negative-OR

NAND

KEJ F

AB

Y = AB + CD

C
D

CD

KNANDEJ F

W(Y)
Y = (AB)(CD)

W
Y = AB + CD

W(bars)
Y = AB + CD

ANDAB+CD (Y)

NAND(Y).OR
--

KORNANDANDEJ F
NANDEFJ (Y)

KOR

EFJ E-F
EFJ

(NAND-NAND-NAND)(AND-AND-OR)
A

AB

Y = AB + CD

C
D

EF

CD

Y = AB + CD

E F

KEJ FAND-AND-OR EJ F
NANDEJ F
KJ OR
A

AB

C
D
E
F

ABC

DE

DEF

KJ OR EJ F

WEJ F(Y)
F = [(AB)C] [(DE )F]
= [(A + B)C] [( D + E )F]
= ( A + B )C + ( D + E ) F
= ( A + B )C + ( D + E ) F

--

NANDJ OR
K(Y)EJ F

A+B

( A + B )C

Y = ( A + B )C + ( D + E )F

D+E

( D + E )F

KJ OR EJ F EJ F

WNANDWEJ F

(a ) Y = ABC + DE

(b) Y = ABC + D + E

KEJ FW

A
B

ABC

Y = ABC + DE

C
D
E

DE

ABC
Y = ABC + D + E

C
D
E

E F

E F

KEJ F EJ F
NOR Logic NORJ J

J ANDNORNOR

A + B = A B
NOR

Negative-AND

KEJ F
--

A+B

(A + B) (C + D)

C
D

C+D

KNOREJ F

W
Y = (A + B) + (C + D)

Y = (A + B) (C + D)

Y = (A + B) (C + D)

ANDOR(A + B)(C + D)
ANDOR
KJ ANDEFJ KEFJ

A+B

(A + B) (C + D)

C
D

C+ D

A+B
(A + B) (C + D)

C
D

E F

E F

KJ ANDEJ FEJ F

NOREJ F
W(Y)KJ AND

--

Y = [(A + B) + C] + [(D + E ) + F]

= [ AB + C] + [ D E + F]

= ( AB + C)( D E + F)

A+B

( A + B) + C

D+E

( D + E) + F

KNOREJ F

KEJ FNORJ AND

AB

AB + C

C
Y = ( A B + C) (D E + F)

D
E
F

DE

DE + F

KEJ FEJ F

--

WNORWEJ F
Y = AB C + (D + E )

KEJ FW

A
B

A + B + C = AB C

Y = A B C + ( D + E)

C
D

KNOREJ F

Karnaugh MapJ
K-
K

KK

(cells) (array)

(Quine - McClusky)
K
--

K
K 2 4 = 16 2 3 = 8

Simplification using Karnaugh-map J

KEF

( A, B )(A B)EJ F
K({{{)EF

AB

AB

AB
AB

AB

AB

AB

AB

KEJ F
K
EJ F(Input Labels)
A
K

B K
A
K
B

K AB

--

KE = FEJ F

EFEFJ EFJ

KEF

CD

CD

CD

AB

BC

BC

BC

BC

CD

AB

AB

EF

AB

E F

KEJ F

KEFJ

--

OR ()

KEFJ

KEFJ

KEFJ

--

A A B B

AB

AB

Y=AB+AB

EF

E F

E F
B

A A B B
Y

EFEFEF
KEJ F


()K

()() ()

()
K

KEABFE A B F
K()()( AB, A B )

K A + A = 1 EComplements)

KEFJ
--

EFJ
K(adjacent cells)

EFJ ()

B B
AB , A B K
WA
Y = A B + AB EF
Y = A (B + B)
= A 1= A

EFJ

K(A)(Y)
KEFJ

EFJ WEJ F
K

W
KEFJ

EFJ ()

()KEFJ

EFEFJ

A , A K

K A B C , C BC

KEFJ

OR AND

--

ORAND
KEFJ

EF
A A B B

BC

CC

BC

BC

BC

Y = AB + B C
A B
B C

E F
EF

KEJ F

EF('s)

EJ FK
K

E'sF
K

F
--

KE

AB

AC

CD

CD

CD

CD

AB

AB

AB

AB

AB

AB

AD
AB C

AB

AD

+ ABCD + A B C D + A B CD
Y = AB C + AD + AB D + A B

EF

CD
AB

AB

Y=

CD

AB

EF

EF

EF

CD

CD

CD

CD
BD

AB

AB

AB

CD

AB

A B

Y = AB C D + ABC D + ABC D + ABCD

+ AB C D + ABCD + A B CD + ABCD
Y = B+D

E F

A B C D + A B C D + A B CD + A B C D
+ A B C D + A B C D + AB C D + A B C D

BC

Y = AC + B C + D

AB

+ A B C D + A B CD + A B C D

+ ABCD + ABC D + AB C D + ABC D

EF
EF

C D CD

CD

Y = A B C D + A B CD + A B C D + AB C D

Y = A B C D + A B C D + A B CD + A B C D
+ A B C D + A BC D + AB C D + AB C D

CD

CD

EF

EF

+ ABC D + ABC D + ABCD + AB C D

+ AB C D + ABCD + ABCD EF

Y = C D + AB + BD

EF

EF

KEJ F
--

EFJ WJ
K

KEFJ
(Y)

KEFJ ()

Y = A BCD + A BCD + ABCD + ABCD + A BCD + ABCD

EFJ
K(Y)

--

AD

CD

CD

CD

CD

AB

AB

AB

CD

KJ EFJ

EFJ

K('s)
K AD
C C
B B

WK CD A A B B
Y = AD + CD

Binary Adders and Subtractors J

K
The Half-Adder Circuit J J

EJ F

.[Carry (C)][Sum(S)] A , B

--

+=

+=

+=

+ = or

KEJ F
K(XOR) (S )

EFJ KAND(c)
K C, S
A, B

K
A
A

S(sum)

HA

C(carry)

S
C
EF
EF

KEJ F
EFJ

S,CKEHalf AdderF HA

S = AB + A B
C = AB

The Full-Adder Circuit J J

(-bits)

(carry)
--

(bits)

(bits)

A,B

KEInput carryFCin

KEJ F.(Sum

) (Carry)

Cin

++=

++=

++=

+ + = or

++=

+ + = or
+ + = or
+ + = or

KEJ F
A, B, C

C, S K
E 2 3 = 8 F
K
W S , C

S = A BC in + ABC in + A BC in + ABC in
C = ABC in + A BC in + ABC in + ABC in

--

WS

S = A BC in + ABC in + A BC in + ABC in
= (AB + A B)C in + (A B + AB)C in

XNOR A B + AB XOR AB + A B

S = (A B)C in + (A B)C in

Cin (A B) XOR

WS

S = (A B) C in = A B C in

A, B XOR
S
K Cin

W C

C = ABC in + A BC in + ABC in + ABC in

= (AB + A B)C in + AB(C in + C in )
= (A B)C in + AB ( C in + C in = 1)

KEFJ CS

FAEFJ
K (Full Adder)

--

A
B

Cin

S(sum)

Cin

FA

C(carry)

EF

E F

KEJ F

EFJ
OR OR

KEJ F

Cin

HA
S

HA

KEJ F

Half Subtractor Circuit J J

K K
K

(bit)

K(difference)(bit)

--

K (Borrowed)()
K

(-bits)

A K
()

A B KB, A (A B)KB
.(Difference bit) = , = , = W

K () A<B

()
K = ()K

(D)

K(B)

( B 0 )(D)KEJ F
W

D = AB + A B
B 0 = AB

KEJ F
(S)(D)

A
(C)( B 0 ) XOR
K B A AND ( B 0 )

EFJ EFJ

K(Half Subtractor) HS
--

A
A

D(difference)

HS

B(borrow)

K EJ F

The Full-Subtractor Circuit J J

(-bits)

K K ()
K
( B i n ) (B)(A) A, B, B in

KEJ FK D, B 0

Bin

KEJ F
0's,1's
K A B B in 0's,1's K

K
B in = 0

() B 0 = 1() A = 0, B = 0, B in = 1
K D = 1 = A
--

() A = 0, B = 1, B in = 1
K D = 0 = A = B 0 = 1

K D = 0 B 0 = 0 A B Bin = A = 1, B = 0, B in = 1

() A = 1, B = 1, B in = 1
K D = 1 = A= B 0 = 1

D = ABB in + ABBin + AB Bin + ABBin

(S)

D = (A B) Bin = A B Bin

W(B)

B 0 = ABB in + ABBin + ABB in + ABBin

= B in ( AB + AB) + AB( Bin + B in )

B 0 = B in (A B) + AB ( Bin + B in = 1)

EFJ (B), (D)

(Full Subtractor)FSEFJ

EFJ
OR
KEJ FOR

--

A
B

Bin

Bin

FS

EF

E F

KEJ F

Bin

HS
D

HS
B

KEJ F

--

WE
b) AB(CD + EF)

a) AB(C + D )
c) (A + B + C + D ) + ABCD

d) (A + B + C + D) (AB C D)

WNANDE
a) ABCD + DE
b) ABC + AB + D
c) AB C + D + E
d) ABC + ABC + ABC + ABC

WNORE
a) (A + B + C) (A + B)
b) ABC + (D + E )
d) (A + B) + ( C + D)

c) (AB + C) (DE + F)

WE

--

WE
a) F1 = AB C D + ABCD + ABCD + ABC D + ABC D + ABCD
b) F2 = ABCD + ABC D + AB C D + ABC D + ABCD + ABCD + ABCD
c) F3 = ABC D + ABC D + ABC D + ABC D + AB C D

d) F4 = AB C D + + AB C D + ABC D + ABC D + ABCD + ABCD + AB C D + ABCD

( or )EJ FE
W

a) A = , B = , Cin =

b) A = , B = , Cin =

c) A = , B = , Cin =

d) A = , B = , Cin =

W E
a) S = , Cout =
c) S = , Cout =

b) S = , Cout =
d) S = , Cout =

( or )EJ FE
a) A = , B = , Bin =
c) A = , B = , Bin =

b) A = , B = , Bin =
d) A = , B = , Bin =

--


]<gj]<]<j<^]<]

K
K

KJ
K

--

IntroductionJ

(Combinational Logic Circuits)

(Sequential Logic Circuits)

(Memory)
K

(Flip-Flop Circuit)

()
()()K()

K()()

.(Bistable Multivibrator)
K(Digital Integrated Circuits)NORNAND
(Timers)

(Shift Registers)(Counters)
K

LatchesJ

--

K(Bistable Multivibrator)(Latch)
S-REJ F

(Set Input)""S

(Reset Input)""R

K Q Q

SET
INPUT

Q output

RESET
INPUT

Q output

KS-REJ F

Q =, Q =(Set Condition)

.Q =, Q = (Reset Condition)
()S

QEFQ =

E F Q = RK Q =

()S,R Q =
(unpredictable)

NORS-R

KEJ F

KS-REJ F
--

F()NOR
E

EJ F

K(Active High Inputs)

S
R

(Mode of Operation)
EF
No Change

Latch RESETS

Latch SETS

Invalid condition

KS-REJ F

W
S,R() -
EF(Q)

Q()()R -

EFQ = ()
KQ =

()()S -
EFQ = ()()Q
KQ =

S,R() -
NOR

--

EJ FNAND

EJ F ()NAND
K(Active Low Inputs)

KS-REJ F

(Mode of Operation)

Invalid condition

Latch SETS

Latch RESETS
EF
No Change

KS-REJ F
W

Q() -
KEF

R = S = -
Q = ()
K
--

R = S = -
Q = ()
K

() -
KNAND

(Logic Symbol)EJ F

EFEF

KEJ F

S = 0, R = 0 K(Q) S, R
K

KEJ F S, R WJ

KQ = Q(Q)
W

S
R

KEJ F
--

Clocked S-R FlipFlop S-RJ

S R S-R
(Q)

K
EF

S-R

(CK)(Clock Pulse)
K

S-REJ F

K(CK)

CK

CK

EFEF
KS-REJ F

EFJ

(Positive Edge Trigger) S-R

EFJ ()()
(Negative Edge Trigger)

K()()

NANDS-REJ F

K NAND
--

(Q)S,R
K

CK

KS-REJ F
WS-REJ F
()S,RCK J
K

()(S = ,R = )R J
.(Reset)()()

()(S = ,R = )S J
.(Set)Q = ()

S = , R =

S
R
CK

(Mode of Operation)
EF
Q

X
No Change

Latch RESETS

Latch SETS

?
Invalid condition
Z()()

XZ

QZ

KS-REJ F
--

] S-R
[()()
K()()

EJ FS-R (Q)WJ

KEJ FS,R,CK
KQ =

CK

KS-REJ F
W
KQ = (Q)S = , R = -

K(Reset)Q = S = , R = -

K(Set)Q = ()Q S = , R = -
.(Reset)Q = S = , R = -

K(Set)Q =S = , R = -

KQ = ()S = , R = -

--

D-Type Flip-FlopD J
(Single Bit)D
S-RK()

KEJ FD

CK
Q

KDEJ F

DD

CK()DKCK

R = S = [Set]()
KQ = EJ FS-R

CK()D

R = S = [Reset]()

()(Set)KQ = EJ F
K()()

KEJ F(Positive Edge Trigger)

D
CK

(Mode of Operation)

(SET)

(RESET)

(stores a )
(stores a )

Z()()

--

KD EJ F
K (D)(Q)

(D)DEJ F

EJ FK
(CK)
KNANDD

CK

CK

KDEJ FKNANDDEJ F

EJ FDEQFWJ
Q = KEJ FEDF
K

W
CK

D
Q

KDEJ F
()()(D)(Q)

--

J-K Flip FlopJ-KJ

J,K KJ-K
S-R

S-RJ-KK
J-K.(Reset)(Set)

KS-R

KJ-KEJ F

S-R
K()J,K

Q
CK

J
CK

KJ-KEJ F
SREJ F

K Q Q

J-KEJ F
()J,K

J = , K = ()(Reset)
J = , K = J-K(Set)

(Toggle)J-KK

Q()J,K
KCK

--

J
K CK

(Mode of Operation)
EF
Q

No Change

(RESET)

(SET)

Q0

Toggle
Z()()

QZ

KJ-KEJ F
EJ FJ-K (Q)WJ

KEJ FCKJ-K

KQ =
W

CK

J
K

KJ-KEJ F
Q ()J,K -
K()

KJ = K = -

KQ = (Reset)J = , K = -
--

KQ = (Set)J = , K = -
QJ,K (Set) -
K()

T-Type Flip-Flop T J
J-KT

EJ FJ,K

(Toggle)TKTT
K

CK()(T)

CK
KEJ FCK

CK
K

KTEJ F
KEJ FT

T
CK

(Mode of Operation)
EF

Q
No Change

Q0

Toggle
Z()()

QZ

KTEJ F
--

EJ F(T)QWJ
EJ FCKT

KQ =
W

CK

KTEJ F

T = Q
T = Q = QT =

K()()Q

Master-Slave Flip-FlopJ

K(Edge Triggered)

(Master-Slave)(Pulse Triggered)
(Complete Clock Pulse)

J S-REFJ

(Master)(Slave)(Master)S-R

(Slave) (CK)

K( CK )

--

Master
S

Slave
Y

CK

CK
Y

KJ S-REFJ

EFJ CK CK
(CK) (Master)

(Slave)
K( CK )

WS,RQ Q

(Master)(CK)(High)W

(Reset) (Set) (Enabled)

KS,R

(slave) (CK)(Low)W

KYQ(Enabled)

S-REFJ

K S-R
KJ

(CK)

K(Low)(High)

J S-REFJ
tt(CK)

KS,R

--

(Enabled) (Master)t
(Set) S = , R = (CK)(High)
K( Y = 0 )Y =

(Low)(Disabled)t

(Enabled)(Slave)CK
Q Y, Y K CK (High)

KQ = (Set )
F

KE CK = 1 Q = 1, Q = 0 Y = 1, Y = 0

S
R
CK

Q
Q

(Mode of Operation)
EF

( RESET)

(SET)

KJ S-REFJ

--

CK

S (SET)

R (RESET)

Master
Enable

Master
Enable

Master
Enable

Master
Enable

(Master)

CK

Slave
Enabl

Slave
Enable

Slave
Enable

(Slave)

Y (Slave Set)
Y (Slave Re set )

KS-REFJ
(High)t

Y = 0, Y = 1 S = , R = CK
.(Reset)
CK (Low)t

(Reset)K
KQ =

Y(Low)S,Rt

StK(Y = )

KY = (High)
--

t
KQ = QY =

D CK

(Mode of Operation)
(SET)

(RESET)

(stores a )
(stores a )

E F
D
Clock in

CK
R

CK
CK

EF

KJ DEJ F

EFJ DEFJ

D S-RK
KQCK

EFJ J-KEFJ

EFJ K

(Q) J-K
KS-R

--

Master

Slave

Q
CK

CK

KJ J-KEFJ

J
K CK
Q

(Mode of Operation)
EF
( RESET)
(SET)

Q0

(Toggle)

KJ J-KEFJ

--

ME

ME

ME

ME

ME

ME

ME

ME

ME

ME

CK
ME = Master Enabled

J
K

(Master)

CK

SE

SE

SE

SE

SE

SE

SE

SE

SE

SE = Slave Enabled

Y
(Slave)

Y
Q

KJ J-KEFJ

(PRE ) (PRESET)K
EJ F (CLR ) (CLEAR)

K CLR PRE
S-R
Q = (SET)
Q = (RESET)

(RESET)
K Q
(PRE ) K
(CLEAR)
PRE = 0 ()Q
--

()Q (CLR )
S-R EJ FK CLR = 0

QE F PRE = 0 CLR = 1

PRE = 1 KCK, S, R()

()QEF CLR = 0
KCK, S, R
PRE

CK
R

CLR

K CLR PRE S-REJ F

PRE CLR CK S

X
X

X
X

R
X

(Mode of Operation)
(SET)

( RESET)

KS-R CLR PRE EJ F

--

Timer Circuits J

K
(Clock Signal)

(Positive Edge)(Sharp)K

K(Negative Edge)

J-K, S-R,D-Type

.(Set and Reset States)(bi)(Bistable Multivibrator)

(Astable Multivibrator)

(Mono)(Monostable Multivibrator)
K(Fixed Duration)(Rectangular Pulse)(Triggered)
Astable Multivibrator CircuitJ J

(Free running)

EJ F

K (Schmitt-trigger)(Inverter)

EFDischarge

()
C

EF Charge

+V

KEJ F
--

.(High)(Not) (Low)()

(R) (C)
(High)R,C

(Low)K

(Low)
K

K(High)

Monostable Multivibrator CircuitJ J

K EFJ

NOR(Low)Q(Low)(Trigger)

(Low) (High)
K

K(Low) NOR (High)

NOR (Low)(High)
Q(High)
NORQKEFJ
K (Low)

+V

Input
Trigger (T)
C

Output
Pulse (Q)

E F

Input
Trigger (T)
Output
Pulse (Q)

EF

KEJ F
--

NOR
K
(resistorcapacitor network)

RC

KQ(Low)(High)

The Timer Circuit J J

EJ F(IC)
K 5K

+VCC
EF

Discharge Threshold
EF
EF

Control Voltage
EF

Ground
EF

Trigger
EF

Output
EF

Reset
EF

KEJ F

(Monostable mode)(Astable mode)

(Modulator)(Frequency Divider)
K

Timer as an Astable Multivibrator

J J J

--

EFJ
K(Free running)(Astable)
CEFJ
K()EF+Vcc

+V

Timer
K

RA

/ VCC
+

Comparator
(A)

RB

/ VCC

RL
Inverting
Buffer/Driver

Output

Q
S-R
Flip-Flop
Inverter
S

EF

Comparator
(B)
+

K
Discharge Transistor

EF

KEFJ

--

EF

/ VCC
Voltage
Across "C"

/ VCC
(+VCC)
Output
()

tp

tn

KCEFJ
T](High)S-R
(Low)K[
KOFF(Discharge Transistor)

(C)OFF

TKRB, RA+Vcc
1
3

2
3

VCC (High) A VCC

()KQ = (RESET)

KON(High)(Low)

K CON

1
3
Q = (SET)S-R(High)

B VCC T
KCOFFK
RB, RACEFJ
1
3

2
3

(Positive time) tpK VCC RB VCC

W

t p = 0.7(R A + R B )C
--

W(Negative time) tn

t n = 0 .7 R B C

WtntpEFT

T = t p + tn

= 0.7(R A + 2R B )C

f =

1
1
=
T 0 .7 ( R A + 2 R B ) C

W
f=

1.43
( R A + 2 R B )C

J J J

Timer as a Monostable Multivibrator

EFJ

EFJ .(one-shot)

K(Input - trigger)

KRA,C(Pw)

(RESET)S-REFJ T
S-R(Low)KQ = (Low)
(inverted and buffered)

K(Low)V()

(High)S-R(Low)

K ON
--

()(Trigger)T
1
3

VCC B K
KQ = (SET)S-R(High)B
()S-R (High)

KOFF(High)

+V

Timer
K

RA

/ VCC
+

RL

Comparator
(A)

K
Trigger
Input

/ VCC
+

Inverting
Buffer/Driver
Q
S-R
Flip-Flop

Inverter

Output

Comparator
(B)

Discharge Transistor

KEFJ

--

T T
Trigger / VCC
Input
V

/ VCC

Voltage
Across "C"

Output

KCEFJ

+VCCRAC
(High)KEFJ
2
3
()(RESET)S-R

(High)A(T)K VCC

CON(Low)
K

(Leading edge)

RAC(Trailing edge)
WK

Pw = 1.1R A C

--

Shift RegistersJ

(bit)

Shift ) (Shift Left)(Buffer Register)

(Parallel Data)(Serial Data)(Right

K(Shift Registers)

Buffer RegistersJ J

(Digital word)

EFJ K(bits)

D (-stages)
K(Positive edge-triggered)

(-bit word to be stored)

D

CLR

CLR

CLR

CLR

CK
CLR

(parallel data outputs)

E F

KDEFJ

--

Clock

Input data

Output data

Q
Q

EF

KEFJ EFJ

D(-bits)

Q,Q, Q,QD,D,D,
K(CK)

EFJ

Q,Q, Q,Q
KK

J
(Clear-input)K(Parallel-in, Parallel-out Registers)
KEF(active-low)

--

Shift RegistersJ J
(Shift)(move)

WKEJ FK

(Serial-in, Serial-out Shift Registers) -

K(SISO)

(Serial-in, Parallel-out Shift Registers) -

.(SIPO)

(Parallel-in, Serial-out Shift Registers) J

K(PISO)

Serial-in, serial-out (SISO) Shift Registers

Shift Right
Serial-In

Serial-Out

Shift Left
Serial-In

Rotate Right

Rotate Left

EF

Serial-in, parallel-out (SIPO) Shift Registers

Serial-In

Parallel-in, Serial-out Shift (PISO) Registers

Parallel Data In

Serial-Out
Parallel Data Out

EF

KEFJ

--

J J J

Serial-in, Serial-out (SISO) Shift registers

K EJ F

E
F
K

Clock

Input

st

nd

rd

th

KEJ F

( st Clock pulse)

(nd Clock pulse)K

()

KK()
()

()

--

Serial
Data
Input

FF

FF

Q
1

FF

FF

Serial
Data Out

CK

Clock
Input
SISO Shift Right

E F
Serial
Data
Input

Serial
Data Out
Q

CK

Clock
Input

FF

Q
1

CK

FF

FF

CK

FF

SISO Shift Left

EF

SISO Rotate Left

SISO Rotate Right

EF

KEJ F
(-bits)EFJ

(FF)DKD
(Q)(FF)D(Q)
--

(Q)(FF)
(FF)

(Clock input)

(-bit) (Positive edge)

K
EFJ

EFJ .(SISO Shift-Right Shift Register)

D

K(SISO Shift- Left Shift Register)

EFJ EFJ

(SISO Rotate-Left) (SISO Rotate-Right)

KEFJ

J J J

Serial-in, parallel out (SIPO) Shift registers

EJ F
K

(-bits)

F(Serial data input)

KE

--

Serial
Data
Input

FF

FF
D

CK

CK

FF

Q
1

FF
Q

CK

CK

Clock
Input

Q
1

Parallel data outputs

KJ EJ F

(-bits)
K

K(-bits)(Q,Q,Q,Q)

J J J

Parallel-in, Serial-out (PISO) Shift registers

EJ F

KD
(Low) SHIFT / LOAD K SHIFT / LOAD

(Enabled)AND
K Inverter
K(D,D,D,D)

(Clock pulse)
.(Q,Q,Q,Q)

--

(SHIFT / LOAD) control

Parallel data inputs

(1 for shift , 0 for load )

D
1

FF

FF
D
CK

FF
Q
1

CK

FF
Q

CK

Serial
Out
3

CK

Clock
Input

KJ EJ F
AND(High) SHIFT / LOAD
QK(Enabled)

(FF)Q(FF)D
K(FF)Q
(-bit)
.(clock inputF

Shift Register Sequencer (Ring Counter)EFJ J J

EFJ

KEDQFFF(FF)

QLow SRART K
E CLR = 0 FLow Q,Q,Q( PRE = 0 )High
KEFJ

--

PRE

Q
1

0
PRE

D
1

CK

Q
1

CK

FF

Clock

CK

CLR

CLR

PRE

FF

EF

KEFJ

Clock
START

Q
1
Q

EF

KEFJ

--

CLR

FF

START

CK

CLR

FF

PRE

Clock
Pulses

Four flip-flops will have

Four output states.

Repeat Sequence

KEJ F
()
()
KEJ F

Johnson CounterJ J J

EFJ

K(D)E Q 3 F

QEJ FEFJ
(High) Q 3 (Low)
(High inputs)D

K(High)

(Low) Q 3 E F(High)Q
K(Low) D

K(Low)(Low inputs)
Q 3 EF(Low)Q

K(High)D(High)

--

PRE

Q
1

D
1

CK

PRE

Q
1

CK

PRE

CK

PRE

FF

Clock

CLR

FF

CK
Q

CLR

CLR

CLR

FF

FF

EF

Clock
START

Q
1

EF

KEJ F

--

Clock
Pulses

Q Q3

Four flip-flops will have

eight output states.

Repeat Sequence
KEJ F

F
KEEJ F

EFJ

KEJ F( flip-flops = )

--

CountersJ

(binary bits)K

K(clock input)

K(Synchronous Counters ) (Asynchronous Counters)

K(Master Clock)

Asynchronous Binary-Up Counters J J

K EFJ

K J-K
K

(High)J,K
K (Negative edge)(Toggle)

(Q)

(-bit word)Q,Q,Q,QKEFJ

FFKEJ F
K(MSB)(Q)FF(LSB)(Q)

- -

FF
J
Clock
Input

Q
1

CK

CK

CK

FF

FF

FF

Q
1

CK
K

EF

EF

KEJ F
(Clock input)(FF)
(Toggle)Q
KEFJ Q

K"""" """"Q
QFFQ

QQ
K(Toggle)Q
KQQ

--

Cycle Repeats

Binary Count

KEJ F
The Maximum Count (N) of a Counter
EJ F
[()]

][
()]
K[
()
W

N = 2 n 1

(N = maximum count before cycle repeats) = N

(n = number of flip-flops in the counter circuit) = n

--

WEFJ
N = 2n 1
= 24 1
= 16 1
= 1510 (11112 )
The Modulus (MOD) of a counter

(MOD)(Modulus of a counter)

MODEFJ K
()()
WMODKEJ F

MOD = n
MOD = modulus of the counter
n
= number of flip-flops in the counter circuit

WEFJ

MOD = 2 n
= 24
= 16
The Frequency Division of a counter

EFJ

(frequency divider)

EFJ
--

KQ

WK

Division Factor = n EF

N = number of flip-flops in the counter circuit

The Propagation Delay Time (tp) of a counter

(Ripple counter)
K

E F

( Flip-Flops ns) 40ns 10ns (tp)

(counting speed)K
K

1 10 9
f=
n tp

f = upper clock pulse frequency limit

n = number of flip-flops in the counter circuit
tp= propagation delay time of each flip-flop in nanoseconds

Asynchronous Binary Down CountersJ J

K""
EFJ K ""
--

Q KJ-K
KQ

KEFJ Q

Q,Q,Q,Q
(RESET)

Q LowQK
FF,FF,FFK

High J,KKHigh

K(Toggle)

Q
1

HIGH

FF

FF
Q

J
Clock
Input

CK
K

Q
1

CK
Q
1

CK
Q

FF

FF

CK
Q

E F

Clock
Input

EF

KEJ F
""QFF

"""" Q 0 ""
--

""""QFF
"""" Q1 K"""" Q1

KFF

Binary Count

Cycle Repeats

KEJ F
() = Q,Q,Q,Q

KEJ F
K
FFEFJ

Q,Q,QQ

K

--

LJ J

Asynchronous Binary Up/Down Counters

Q
K Q

LEJ F

K UP / DOWN AND-OR

Q
HIGH
FF
Q

J
Clock
Input

CK
K

Q
1

FF
Q
1
J

CK
Q

FF
Q

FF
Q

CK

CK
Q
1

UP/DOWN control

KEJ F

ANDHigh UP / DOWN
Q(Enabled)

Low UP / DOWN

(Enabled)(Disabled)
Q

--

Asynchronous Decade (MOD ) Counters J J

EFJ

K(MOD-)

HIGH
FF

FF
J
Clock
Input

Q
CK

Q
1

CK
K

CLR

FF

FF
Q

CK
K

CLR

CK
K

CLR

CLR

Q
1

E F

Clock
Input

CLR

EF

KEJ F

--

EFEF
EFJ

KEJ F

E CLR FNAND E
KQQK
HighQ,QE
F
K (CLEAR)Low NAND
(inactive) CLR EFJ

KHighQ,QK
(CLEAR)QQ
EJ FK CLR

Cycle Repeats

Binary Count

KEJ F

--

(MOD-)
(

1
)Q
10
.(Clock input)

(Digital Voltmeter) (Digital clocks)

K(Frequency Counter)

Synchronous Binary Counters J J

ANDJ-KEFJ
(MOD-) (-bit)

E F
K
(Triggered)
K

Q
1

HIGH

Clock
Input

FF

FF
Q

Q
1

FF
J

CK

CK

CK

FF
J

CK
K

KEJ F

FFJ,K
(Toggle) High
Low
KLowHighHigh

--

FFJ,K
FFQLowQ KFF
QHighQ(No change)

K(Toggle)

AND(A) FFJ,K

High AND(A)Q = Q = HighKQ,Q

KFF(Enable)

AND(B)FFJ,K
AND(B)HighQ,Q,QKQ,Q,Q

KFFHigh

Synchronous Counters Advantages J J

(Ripple counters)

KEFJ EFJ

(Propagation-delay time)
K

K E

--

tp = Single (flip-flop) tp + Single (AND-gate) tp

--

S-R(Q)E
(negative edge trigger)

KQ=K
CK

D(Q)E

K(positive edge trigger)

KQ=

CK

JK(Q)E
K(negative edge trigger)
KQ=

--

CK

T(Q)E
(negative edge trigger)
KQ=K

CK

(f) E
KC = {fRB = kRA = k

E
KC = {fRA = k

--


]<gj]<]<j<^]<]

- -

K
K
K
K

- -

IntroductionJ
K

(fuseprogrammable)

K (Customer)

(fusible links)

(The Programmable Logic Array (PLA))

(The Programmable Array Logic (PAL))

(The Programmable Logic Sequencer (PLS))

(Erasable Programmable Logic Device (EPLD))

(F)
(FPLA, FPAL, .)
K(Field Programmable Logic Devices)
Basic Programmable Logic Devices J
PLDJ EJ F
K(-input/-output)
(noninverting Buffer)
K(Inverting Buffer)

A,B High AND

ANDEJ F

(Product Lines)
K( A B, AB, AB and AB)
(fusible link)OR

.PLDJ ()EJ F

- -

Inputs
A

Fusible
Link

AB

AB

Q3

Q2

Q1

Q0

AB
AB

Outputs

KPLDEJ F

High Out

AND

AND

AND

AND

KEJ FANDEJ F

- -

EJ F

PLDs J K
EJ FEJ FK

Inputs
A

AB

AB

AB

AB

Q3

Q2

Q1

Q0

Outputs

KPLDEJ F

AND
K

OR K
K(fusible link)(s)
- -

sOR, AND

KPLD

(Q,Q,Q,Q)A,BEJ F
KEJ FPLD

Inputs
A

AB

AB

AB
AB

Q 0 = A B + AB

Q1 = AB
Q 2 = AB + AB

Q 3 = AB

KPLDEJ F

- -

Q OR (blowing fuses)

OR KAB = High
KAB = AB = High Q

KAB = HighQOR

High Q
KAB = AB =

AB

AB

AB

AB

KEJ FEJ F

PLD

XOR (Programmable Output Polarity fuse)

EJ F
K(blown)(Intact)

Low XOR

XOR K

K High
KEJ F

- -

Polarity
Fuse

Output

KPLDEJ F

Polarity FuseEF

XOR's Operation

Intact EF

Will not invert EF

Blown EF

Will invert EF

KEJ F

The Programmable Logic Array (PLA) J

(-bit outputs)(-bit inputs) PLD

K () ()

K(PLA)

PLA EJ FPLA

OR AND
K
- -

O O O

KPLA
EJ F

The Programmable Array Logic (PAL) J

ANDEPLAF
PLA
K OR

K
K
OR ANDPAL

KEJ FEF
- -

I I

OR

AND

KPALEJ F

PLA

- -

The Programmable Logic Sequencer (PLS)J

(PLS)

K
K(Input and output registers)
J

Erasable Programmable Logic Device (EPLD)

(PLDs)

K(blowing their internal fuses)

K
PLD
K

(erase)

- -

Q,Q,Q,QA, BPLD E
K

Q,Q E
K

KPLA E

- -

J
J

J
J J

J J

J
J J

J J
J

J
J J

J J

J J

J
J
J J
J J
J J J

J J J
J J

J J

J J

J J
J J J

J J J

J
J J

J J

J J J

J J J

J J

J J

J J

J J

J J

J J

J J J

J J J

J
ANDJ
OR J
EF NOT J
NAND J
NOR J
EF OR J
EF NOR J
J
J
J
J
J
J

W

J
J
NOR , NANDJ
NANDJ J

NORJ J

NAND
J
NOR
NANDJ J

NORJ J
J
J
J
J J
J J
J J
J J

W

J
J
S-RJ
D J
J-KJ
T J
J
J
J J
J J

J J

J J J

J J J

J
J J

J J

J J J
J J J
J J J
EFJ J J

J J J

J
J J

J J
LJ J
J J
J J
J J

J
J
J

J
J

EF

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