AIM :- PROGRAM TO IMPLEMENT A D- FLIP FLOP(2)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dff1 is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end dff1; architecture Behavioral of dff1 is begin process(clk) begin if(clk'event and clk='1')then q<=d; end if; end process; end Behavioral;

FIG (7.1) SHOWING RTL SCHEMATIC OF A D- FLIP FLOP(2)

FIG(7.2) SHOWING INTERNAL TECHNOLOGY SCHEME OF FIG(7.1)