Cc bc lm vic vi Keil C

Cc bc thc hin.
Bn xem hnh minh ha cho d dng

__________________

 c th hiu c nhng vn ti vit th yu cu bn phi c kin thc cn bn v C nh hm con, s

dng con tr, cc kiu d liu(int, float, double,char, unsigned char,..)
Ti xin i vo bi th nht. Ni v cu trc cho chng trnh C:
1/Phn u tin l lit k cc header file m cc bn dng bng t kha
Code:

#include"tn header file"

hoc
Code:

#include< tn header file>

Khi bn vit theo cch th nht th trnh bin dch s tm kim file .h hoc .c ny trong th mc hin ti cha
d n ca bn, nu khng c th s tm kim trong th mc Inc trong th mc ci t KeilC.
Vit theo cch th hai th trnh bin dch s tm lun trong th mc /INC lun.
c th s dng ng cc file .h cho cc vi iu khin ca mnh th bn nn m th mc /inc trong th mc
ny c cc th mc con nh tn ca hng sn xut. V d nh ca Atmel th bn tm trong th mc /Atmel
th s thy c file reg51.h ,.. Bn m tng file nn m khm ph s c nhiu iu hay y.
2/nh ngha cc macro cho chng trnh sng sa. Vic nh ngha ny c dng bng t kha #define
V d: bn nh ngha led1 l P1_0 tc l led1 c ni vi chn 0 ca Port 1.
Code:

#define led1 P1_0

3/ Cc hm ngt nh ngt timer0, timer1, ngt ni tip, ngt ngoi. Ti s ni chi tit ci ny sau. Cn by
gi ti ch gii thiu s s thi.
V d bn dng ngt ni tip l ngt 4 trong bng vector ngt th hm s c dng nh sau:
Code:

void inter_4(void) interrupt 4 using 2{

// lm g th lm y
}

C php cc ngt khc cng tng t ch thay s 4 bng s th t ca ngt trong bng vector ngt.
4/ Cc hm con nh Delay, khi to,.. nh:
Code:

void delay( unsigned char time){

//code vit y
}

5/ Chng trnh chnh:

Code:

void main(void){
// vit m y
}

i tng ca chng trnh l vi iu khin nn hm main khng c gi tr tr v v khng c tham s a

vo. V thc cht cng chng cn bin ton cc v ta ch cn vit 1 file thi. nn ti khng a bin ton cc
vo y.
Kt lun, chng trnh ca chng ta s c dng nh sau:
Code:

// lit k header file

#inlucde"tn header file"
....................
// cc marco
#define led1 P1_0
...........
// cc hm ngt
void inter_1 interrupt 1 using 3{
}
..........
// cc hm bnh thng
void delay( unsigned char time){
///
}
..............
// chng trnh chnh
void main(void){
}

Hm tr delay()

ng l ra ti phi gii thiu cho cc bn cc header file trc nhng ti qun mang theo mong cc bn
thng cm. Ti xin gii thiu dng delay trc .
C l vic lp trnh cho vi iu khin mt hm khng th thiu l tr: nh tr khi bn nhy led chng hn(
v d n gin nht), ...
Vic gy tr trong Keil C c th c nhiu cch khc nhau:
Hm delay c tham s l thi gian cn gy tr tnh theo ms
1/Dng vng lp while, for
dng kiu no th cng n gin ch l vng lp m thi. Trong vng lp ny chng ta s chng lm g c nn
vi iu khin s b mt thi gian trong cc vng lp ny.
Vi tn s thch anh 11.0582 MHz th mi vng lp khi cc bn debug s thy l chng ta mt thi gian thc
khong 8.28 us. Do c th gy tr 1ms th cc bn cn dng xp x 121 vng lp kiu ny.
Do hm s nh sau:
Code:

void delay(usigned char time){

while(time--){
unsigned char temp = 121;
while(temp--); // chng lm g c
};
}

Vic chuyn i gia vng for vi while trong trng hp ny rt n gin thi. Nhng khi bn li phi
khai bo thm mt bin m nh th s tn b nh. Chng trnh trn l ti u nht ri.
2/Dng timer0,timer1,..
Ci ny ti xin phn tch sau cng vi vic gii thiu cc #include. c th h thng ht c. Cho n c
logic. Ch nu ti a ra lun cc bn mi hc s khng hiu l n u ra.

Tip tc vi hm delay() theo cch dng b nh thi.

Cc bn c bi trn cng thy c l chng ta lp trnh vi cc thanh ghi tng t nh trong ASM m
thi.
TMOD l thanh ghi 8 bt dng thit lp b nh thi , cc bn xem li thanh ghi ny.
Dng b nh thi c 3 ch : ch 0, ch 1, ch 2. Chng ta s s dng ch khi ng b nh
thi bng phn mm tc TMOD.3 v TMOD.7 =0
Vic xc nh ch no ph thuc vo gi tr ca 2 bit TM1 v TM0 ca tng timer( cc bn xem nh ngha
tng bt trong thanh ghi TMOD)
TM1=0 , TM0 =0 ch 0
TM1=0, TM0 =1 ch 1O
TM1=1, TM0 =1 ch 2
Ch 1 l ch 16 bt khng t np li, cch s dng bng cch np gi tr cho cc thanh ghi TH1,TL1(
vi Timer1), hoc TL0,TH0( vi Timer0). Khi khi ng timer bng cch setb TR1 hoc TR0 th n s m
tTHTL -> 0xFFFF khi t 0xFFFF->0x0000 th c TF1 hoc TF0 s bt ln sau chng b xa thnh 0. Chng
ta dng c ny bit khi no chuyn qua 0x0000.
Ch 0 l ch 13 bt tng t nh ch 1 nhng gi tr ch tng n 0x1FFF.
Ch 2, ch 8 bt t np li, ch cn thit lp cho ch
Tip theo l chng ta tnh thi gian ca mi ln tng b nh thi. Tn s ca b nh thi bng 1/12 tn s
ca thch anh, do vi tn s 11,0592MHz th chu k my bng 1.085us.
Do vy vi ch 1 ti a chng ta s gy tr c l 65536*1.085 = 71106.56 us = 71.10656 ms.
Ch 2 max = 256 *1.085 =277.76 us
Ch 0 bn t tnh.
T bn tnh ton nha. Chng ta mun tr nhiu th chng ta thm vng lp vo.
--------------------------Ti ch cn gy tr 1ms = 1000 us>277.76 nn dng timer0( 16 bit) ch 0 th bn tnh ton gi tr np
cho timer0 nh sau:
thi gian tr = (65536 - gi tr np vo TH,TL+ 1) * 1.085.
Sau i gi tr ra s hex. Cc bn dng Calculator ca windows i.
=> TH0 = FC, TL0 = 67
Vy chng trnh s nh sau:
Code:

void delay(unsigned char time){

while(time--){
TMOD = 0x01; // dng timer0 ch 1( 16 bit)
TH0 = 0xFC;// np gi tr cho timer
TL0 = 0x67;
TR0 = 1; // khi ng b nh thi
while( TF0); // ch khi no c TF1 =1
TF0 = 0 ; // xa c trn
TR0 = 0; // dng b nh thi
};

Cc bn thy th no, rt l n gin ng khng

Chc thnh cng.

C l ngi dng Keil C ln u tin gp tr ngi khi dng #include l khng bit lit k cc header file
no cn thit cho ng dng ca mnh.
c th bit c header file no dng cho vi iu khin ca mnh th cc bn m th mc ci Keil C ra, tm
n th mc C51/INC bn s thy mt lot cc th mc ca cc hng nh Atmel,Dalas,.. Ti xin ly v d
mt file regx51.h trong th mc /Atmel. Bn m file ln s thy u ca n nh sau:
/
Code:

*-------------------------------------------------------------------------AT89X51.H
Header file for the low voltage Flash Atmel AT89C51 and AT89LV51.
Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
--------------------------------------------------------------------------*/

Chng t file ny dng cho con AT89C51 v AT89LV51 ri. Khi bn s thm header file ny vo chng
trnh ca mnh.
Cn lm th no mnh lm vic vi cc thnh ghi, cc port nh trong ASM by gi. Cu tr li trong file
ny:
Code:

#ifndef __AT89X51_H__
#define __AT89X51_H__
/*-----------------------------------------------Byte Registers ; nh ngha cc thnh ghi cc a ch trong RAM
------------------------------------------------*/
sfr P0
= 0x80;
sfr SP
= 0x81;
sfr DPL
= 0x82;
sfr DPH
= 0x83;
sfr PCON
= 0x87;
sfr TCON
= 0x88;
sfr TMOD
= 0x89;
sfr TL0
= 0x8A;
sfr TL1
= 0x8B;
sfr TH0
= 0x8C;
sfr TH1
= 0x8D;
sfr P1
= 0x90;
sfr SCON
= 0x98;
sfr SBUF
= 0x99;
sfr P2
= 0xA0;
sfr IE
= 0xA8;
sfr P3
= 0xB0;
sfr IP
= 0xB8;
sfr PSW
= 0xD0;
sfr ACC
= 0xE0;
sfr B
= 0xF0;
/*-----------------------------------------------P0 Bit Registers ; nh ngha cc cng ca Port 0 v port ny l thanh ghi 8 bt nh
c a ch trc tip
------------------------------------------------*/
sbit P0_0 = 0x80;
sbit P0_1 = 0x81;

sbit
sbit
sbit
sbit
sbit
sbit

P0_2
P0_3
P0_4
P0_5
P0_6
P0_7

=
=
=
=
=
=

0x82;
0x83;
0x84;
0x85;
0x86;
0x87;

/*-----------------------------------------------PCON Bit Values

------------------------------------------------*/
#define IDL_
0x01
#define STOP_
#define PD_

0x02
0x02

#define GF0_
#define GF1_

0x04
0x08

#define SMOD_

0x80

/* Alternate definition */

/*-----------------------------------------------TCON Bit Registers

------------------------------------------------*/
sbit IT0 = 0x88;
sbit IE0 = 0x89;
sbit IT1 = 0x8A;
sbit IE1 = 0x8B;
sbit TR0 = 0x8C;
sbit TF0 = 0x8D;
sbit TR1 = 0x8E;
sbit TF1 = 0x8F;
/*-----------------------------------------------TMOD Bit Values
------------------------------------------------*/
#define T0_M0_
0x01
#define T0_M1_
0x02
#define T0_CT_
0x04
#define T0_GATE_ 0x08
#define T1_M0_
0x10
#define T1_M1_
0x20
#define T1_CT_
0x40
#define T1_GATE_ 0x80
#define T1_MASK_ 0xF0
#define T0_MASK_ 0x0F
/*-----------------------------------------------P1 Bit Registers
------------------------------------------------*/
sbit P1_0 = 0x90;
sbit P1_1 = 0x91;
sbit P1_2 = 0x92;
sbit P1_3 = 0x93;
sbit P1_4 = 0x94;
sbit P1_5 = 0x95;
sbit P1_6 = 0x96;
sbit P1_7 = 0x97;
/*-----------------------------------------------SCON Bit Registers
------------------------------------------------*/
sbit RI
= 0x98;

sbit
sbit
sbit
sbit
sbit
sbit
sbit

TI
RB8
TB8
REN
SM2
SM1
SM0

=
=
=
=
=
=
=

0x99;
0x9A;
0x9B;
0x9C;
0x9D;
0x9E;
0x9F;

/*-----------------------------------------------P2 Bit Registers

------------------------------------------------*/
sbit P2_0 = 0xA0;
sbit P2_1 = 0xA1;
sbit P2_2 = 0xA2;
sbit P2_3 = 0xA3;
sbit P2_4 = 0xA4;
sbit P2_5 = 0xA5;
sbit P2_6 = 0xA6;
sbit P2_7 = 0xA7;
/*-----------------------------------------------IE Bit Registers
------------------------------------------------*/
sbit EX0 = 0xA8;
/* 1=Enable External interrupt 0 */
sbit ET0 = 0xA9;
/* 1=Enable Timer 0 interrupt */
sbit EX1 = 0xAA;
/* 1=Enable External interrupt 1 */
sbit ET1 = 0xAB;
/* 1=Enable Timer 1 interrupt */
sbit ES
= 0xAC;
/* 1=Enable Serial port interrupt */
sbit ET2 = 0xAD;
/* 1=Enable Timer 2 interrupt */
sbit EA

= 0xAF;

/* 0=Disable all interrupts */

/*-----------------------------------------------P3 Bit Registers (Mnemonics & Ports)

------------------------------------------------*/
sbit P3_0 = 0xB0;
sbit P3_1 = 0xB1;
sbit P3_2 = 0xB2;
sbit P3_3 = 0xB3;
sbit P3_4 = 0xB4;
sbit P3_5 = 0xB5;
sbit P3_6 = 0xB6;
sbit P3_7 = 0xB7;
sbit
sbit
sbit
sbit
sbit
sbit
sbit
sbit

RXD
TXD
INT0
INT1
T0
T1
WR
RD

=
=
=
=
=
=
=
=

0xB0;
0xB1;
0xB2;
0xB3;
0xB4;
0xB5;
0xB6;
0xB7;

/*
/*
/*
/*
/*
/*
/*
/*

Serial data input */

Serial data output */
External interrupt 0 */
External interrupt 1 */
Timer 0 external input */
Timer 1 external input */
External data memory write strobe */
External data memory read strobe */

/*-----------------------------------------------IP Bit Registers

------------------------------------------------*/
sbit PX0 = 0xB8;
sbit PT0 = 0xB9;
sbit PX1 = 0xBA;
sbit PT1 = 0xBB;
sbit PS
= 0xBC;
sbit PT2 = 0xBD;

/*-----------------------------------------------PSW Bit Registers

------------------------------------------------*/
sbit P
= 0xD0;
sbit FL
= 0xD1;
sbit OV
= 0xD2;
sbit RS0 = 0xD3;
sbit RS1 = 0xD4;
sbit F0
= 0xD5;
sbit AC
= 0xD6;
sbit CY
= 0xD7;
/*-----------------------------------------------Interrupt Vectors:
Interrupt Address = (Number * 8) + 3
------------------------------------------------*/
#define IE0_VECTOR
0 /* 0x03 External Interrupt 0 */
#define TF0_VECTOR
1 /* 0x0B Timer 0 */
#define IE1_VECTOR
2 /* 0x13 External Interrupt 1 */
#define TF1_VECTOR
3 /* 0x1B Timer 1 */
#define SIO_VECTOR
4 /* 0x23 Serial port */
#endif

Cc bn nhn trn thy l cc thanh ghi, cc port qu l ging nh vi ASM phi khng. Do vy vic lp trnh
cc bn s lm vic trc tip vi cc cc a ch ca Ram m c nh ngha trn

Gii thiu cc hm ngt.

Cho cc bn, hm nay ti xin gii thiu cho cc bn mt hm na l cc hm ngt.

Trong 8051 c 5 nguyn nhn sinh ra ngt: ngt ngoi 0, timer0, ngt ngoi 1, timer1, ngt ni tip.
Cc bn li m file regx51.h ra phn cui ca file nh sau:
Code:

/*-----------------------------------------------Interrupt Vectors:
Interrupt Address = (Number * 8) + 3
------------------------------------------------*/
#define IE0_VECTOR
0 /* 0x03 External Interrupt 0 */
#define TF0_VECTOR
1 /* 0x0B Timer 0 */
#define IE1_VECTOR
2 /* 0x13 External Interrupt 1 */
#define TF1_VECTOR
3 /* 0x1B Timer 1 */
#define SIO_VECTOR
4 /* 0x23 Serial port */

a ch ca ngt trong bng vector ngt = 8 * s th t ngt + 3,

s th t ngt = 0,1,2,3,4 nh k hiu trong file . Nh vy a ch trong RAM t 0x03 n 0x30 l dnh cho
bng vector ngt.
C php ca hm thc hin ngt nh sau, hm ny khng c tham s, khng c kiu tr v nn l dng
Code:

void tnham(void)

C php chnh nh sau:

Code:

void inter0(void) interrupt 0 using 1{

}

// ngt ngoi 0, dng bank 1

Tng t vi cc ngt khc. Bn thay s 0 bng s th t cc ngt tng ng cc ngt tng ng.
Code:

void inter1(void) interrupt 1 using 1{

}
void inter2(void) interrupt 2 using 1{
}

Tip tc vi 2 ngt cn li
Cc bn lu l vdk nhy n bng vector ngt th bn phi enable ngt .
V d: bn mun ngt ni tip th phi cho nh sau:
Cc bn xem l thanh ghi IE trong file regx51.h, thanh ghi ny nh c a ch bit
Code:

EA = 1;// cho php dng ngt

ES = 1;// dng ngt ni tip

Mai ti s vit tip. Bn FPT cha mc ADSL cho nn vit bi hi chm, mong thng cm, i vi ngy na
khi mc ri mnh s vit bi lin tc v ch ny. Cung phu hn na.
Hm ngt trong keilC

Cch dng hm ngt v mt s on code mu.

Hm ngt l mt hm khng c tham s, khng c kiu tr v. V thc cht cc bin m hm ny thao tc
chnh l cc bin ton cc (cc thanh ghi, cc port).
Cu trc mt hm ngt nh sau:
Code:

void tenham(void) interrupt a using b{

// code
}

Trong : nhng ch in nghing l bt buc phi c v using b c th c hoc khng c.

tn hm: ty cc bn chn.
a : l th t ca ngt trong bng vector ngt
a
a
a
a
a

=
=
=
=
=

0
1
2
3
4

:
:
:
:
:

ngt
ngt
ngt
ngt
ngt

ngoi 0
timer0
ngoi 1
timer1
ni tip

b: l bank c chn dng thc hin hm ngt. Do 8051 c 4 bank l bank 0, 1, 2, 3. Do : b c th l

mt trong cc gi tr 0,1,2,3.
Lu : nu khng vit thm using b th mc nh l hm ngt thc hin ti bank0.
Do , mt th d v hm ngt ni tip s c dng nh sau:
void inter4(void) interrupt 4 using 2{
// m thc hin hm
}
V sau y ti xin gii thiu mt on chng trnh to mt xung chn P1.0 v khi nhn c d liu ni
tip th chuyn sang port P2. Tn s thch anh l 11.0592 MHz. Dng AT89C51
Code:

# include "regx51.h"
// ham gay tre
void delay(int time){
while(time--){
unsigned char j = 122;
while(j--);
};
}
// ham thiet lap ban dau
void init(){

EA = 1; // cho phep dung ngat

ES = 1; // dung ngat noi tiep
// Thiet lap tan so bus
TMOD = 0x02; // dung timer1, che do 8 bit tu nap lai
TH1 = 253; // chon tan so bus = 9600
TR1 = 1 ; // khoi dong timer1
}
// Ham ngat
void inter4(void) interrupt 4 using 2{
if (RI){ // kiem tra co tran nhan RI.
P2 = SBUF; // lay du lieu tu SBUF
RI = 0; // xoa co ngat
};
}
// ham main
void main(){
// tao xung tren chan P1.0
init();
while(1){
P1_0 = 1;
delay(500);
P1_0 = 0;
delay(500);
}
}