EEE 51 (THW) Homework 3: FET Amplier Small Signal Due: 11 Dec 2008 (Thu)

Directions Answer the following problems completely. Use separate sheets for your solution. Write your solutions legibly and box your nal answers. You may keep this questionnaire. Common Gate Amplier For the FET amplier shown, bias the transistor at 1 mA drain current and 5 V drain voltage. Some circuit values and transistor parameters are given in the table below. 1. Find the resistor values needed to meet the biasing requirements. 2. Derive the small signal parameters Av , Zin and Zo . 3. If the frequency of operation is at the range 10 Hz to 50 kHz , what are the limiting values of the coupling capacitors used in the circuit?

FET Parameter VGS,of f VGS (on) IDS (on) rds

Value 3V 10 V 10 mA 100 k

Circuit Parameter VDD VSS Rgen RL

Value 10 V -10 V 50 10RD

Super Buer For this circuit, ignore DC analysis. Assume that transistors Q1 and Q2 has transconductance gm1 and gm2 , respectively. Capacitor C is not a bypass capacitor, but a load with impedance Z. 1. Derive the voltage gain assuming that the output resistance (rds ) of the transistors is very large. 2. Derive the voltage gain assuming that transistors Q1 and Q2 has output resistance rds1 and rds2 , respectively. 3. Why do you think that this circuit is called a super buer ? [Hint: Take into consideration the range of all load impedances possible.]