Automated Mixed-Signal SoC BIST Synthesis Utilizing Hardware Accelerators

Kiran George Computer Engineering Program California State University Fullerton, CA 92831, USA
Abstract BIST techniques for analog and mixed-signal circuits have attracted considerable research activity; especially utilizing on-chip ROMs to store high precision sinusoidal stimuli and precalculated Delta-Sigma modulated bit-streams. However, usage of ROMs in high-performance circuits has poses substantial challenges, mainly because of its inability to run at-speed tests and high area overhead due to its prohibitively large size. An alternative to ROM utilization is the use of LFSRs. But, the computation time of the LFSR based BIST synthesis for large mixed-signal SoC poses a huge challenge. A high-performance computing (HPC) based automated mixed-signal SoC BIST synthesis technique that can outperform the conventional ROM implementation not only with respect to the computation time needed to generate the test vectors or waveforms, but also the BIST hardware required, is presented in this paper. Furthermore, the versatility of the presented LFSR based BIST test vector generator, that allows itself to be used for embedding deterministic patterns for LBIST and storing sinusoidal stimuli or pre-calculated Delta-Sigma modulated bit-stream for analog BIST, is demonstrated. Keywords- mixed-signal BIST; LBIST; HPC; GPU; ROM

Chien-In Henry Chen Department of Electrical Engineering Wright State University Dayton, Ohio 45435
For mixed-mode testing, several techniques have been developed to that utilize LFSR based hardware to generate deterministic tests patterns. However, with the advent of multimillion transistor designs, the non-recurring costs related to BIST during the design process have become important. Particularly, the computation time related to the BIST synthesis for large IC designs which could be in the order of days or even weeks. This poses a big problem for companies dealing with the design and development of SoC designs for consumer electronics such as mobile communication products, which typically has a short time-to-market window [7]. Today, high performance computing (HPC) certainly allows us to challenge prevailing computational limits and explore unchartered research avenues. The complexity of HPC applications is partly defined by the number of processors and the amount of memory required in executing them. In addition to multi-core processors researchers are looking at different ways to offload the computation intensive tasks to specialized processor systems such as AMD accelerated processing unit (APU), many-core general purpose processing (GPP) TILE processor, and specialized hardware accelerators such as Virtex-7 FPGAs and nVIDIA's Tesla Graphic Processing Unit (GPU) cards. These specialized hardware has been utilized to accelerate several applications ranging from molecular modeling [8] to signal processing [9].

I. INTRODUCTION Built-In Self-Test (BIST) has proven to be an effective technique built in to integrated circuits that can reduce testing time and eliminate the necessity for external test equipment. Even though the BIST techniques for digital circuits are much more mature and have been successfully adopted in the past, BIST techniques for analog and mixed-signal circuits are still facing considerable challenges, primarily on the demand of consumer products which utilizes SoC designs that include high-speed mixed-signal blocks. The requirement of additional circuitry for BIST implementation still remains a major concern, which is especially true for: a) logic BIST where deterministic patterns are pre-stored in an on-chip read-only memory (ROM) [1][2]; and b) analog and mixed-signal applications where high precision sinusoidal stimuli [3] or precalculated Delta-Sigma modulated bit-stream [4][5] are stored in an on-chip ROM. Utilization of ROM for these applications not only has a high area overhead due to its prohibitive size but it also hinders its chips ability to run at-speed tests due to its computational complexity. As the result, industry generally tends to shy away from usage of ROM in high-performance circuits [6]. An alternative to ROM utilization is using LFSRs.
This research is supported in part by the National Science Foundation under Grant No. 1032470.

Fig. 1. BIST hardware for mixed-signal SoCs

978-1-4577-1772-7/12/$26.00 2012 IEEE