MISRIMAL NAVAJEE MUNOTH JAIN ENGINEERING COLLEGE

VLSI LAB MANUAL

ECE: VII SEMESTER (2006-2010)

By V.Thilakrathi(Lect/ECE)

 STUDY OF XC3S400 XILINX SPARTAN 3 FPGA FPGA DESIGN FLOW STUDY OF SIMULATION USING XILINX ISE-9.1.i STUDY OF SYNTHESIS USING XILINX ISE 9.1i STUDY OF SCHEMATIC ENTRY USING XILINX ISE 9.1i PLACE, ROUTE AND AC! ANNOTATION IN FIELD PROGRAMMA LE GATE ARRAY "FPGA# SIMULATION AND IMPLEMENTATION OF LOGIC GATES SIMULATION AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER SIMULATION AND IMPLEMENTATION OF HALF SU TRACTOR AND FULL SU TRACTOR SIMULATION AND IMPLEMENTATION OF PARALLEL ADDER SIMULATION AND IMPLEMENTATION OF PARALLEL SU TRACTOR SIMULATION AND IMPLEMENTATION OF CARRY LOO!-AHEAD ADDER SIMULATION AND IMPLEMENTATION OF CMOS GATES SIMULATION AND IMPLEMENTATION OF PARALLEL ADDER AND SU TRACTOR SIMULATION AND IMPLEMENTATION OF $%3 ENCODER AND 3%$ DECODER SIMULATION AND IMPLEMENTATION OF 1%$ DEMULTIPLEXER AND 4%1 MULTIPLEXER

 SIMULATION AND IMPLEMENTATION OF $ IT MULTIPLEXER SIMULATION AND IMPLEMENTATION OF FLIP FLOPS SIMULATION AND IMPLEMENTATION OF SYNCHRONOUS UP DOWN COUNTER SIMULATION AND IMPLEMENTATION OF UNI&ERSAL SHIFT REGISTER SIMULATION AND IMPLEMENTATION OF SERIAL ADDER SIMULATION AND IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER

STUDY OF XC3S400 XILINX SPARTAN 3 FPGA

AIM% To study XC3S400 XILINX Spartan 3 Field Programmable Gate rray !FPG " INTRODUCTION% #ield programmable gate array !FPG " is a semi$ondu$tor de%i$e $ontaining programmable logi$ $omponents $alled &$on#igurable logi$ blo$'s( and programmable inter$onne$ts) Logi$ blo$'s $an be programmed to per#orm t*e logi$ #un$tioning ranging #rom basi$ gates to more $omple+ logi$ #un$tion) In most FPG s, t*e logi$ blo$'s also in$lude memory elements, -*i$* may be simple #lip.#lops or more $omplete blo$'s o# memory) *ierar$*y o# programmable inter$onne$ts allo-s logi$ blo$'s to be inter$onne$ted as needed by t*e system engineer !designer") T*ese $an be programmed by t*e designer, a#ter FPG is manu#a$tured, to implement any logi$al #un$tion *en$e t*e name &FI/L0 P12G1 33 4L/() FPGA DESIGN AND PROGRAMMING To de#ine t*e be*a%ior o# t*e FPG t*e user pro%ides a *ard-are des$ription language !50L" or a s$*emati$ design) Common 50Ls are 650L and 6erilog) T*en, using an ele$troni$ design automation tool, a te$*nology netlist is generated) T*is $an be t*en #itted to t*e a$tual FPG ar$*ite$ture using a pro$ess $alled pla$e.and.route) T*e user -ill %alidate t*e map, pla$e and route results %ia timing analysis, simulation

and ot*er %eri#i$ation met*odologies) 2n$e t*e design and %alidation pro$ess is $omplete, t*e bit #ile is generated is used to $on#igure t*e FPG ) XILINX XC3S400 SPARTAN 3 FPGA It is spe$i#i$ally designed as %ery lo- $ost, *ig* per#orman$e logi$ solution #or *ig* %olume, $onsumer.oriented appli$ations) ARCHITECTURE OF XC3S400 T*is $onsists o# 7 #undamental programmable #un$tionable elements 8) Con#igurable logi$ blo$'s !CL4" $ontain 1 3 based loo'.up.tables !L9Ts" to implement logi$ and storage elements t*at $an be used as #lip #lops or lat$*es) CL4s $an be programmed to per#orm a -ide %ariety o# logi$al #un$tions as -ell as to store data) :) I;2 4lo$'s !I24s" $ontrol t*e #lo- o# data bet-een t*e I;2 pin and t*e internal logi$ o# t*e de%i$e) /a$* I24 supports bidire$tional data #lo- plus :.state operations) 0ouble 0ata rate !001" registers are in$luded) T*e digitally $ontrolled impedan$e !0CI" #eature pro%ides automati$ on.$*ip terminations, simpli#ying board designs) 3) 4lo$' 1 3 pro%ides data storage in t*e #orm o# 8<.80 bit dual port blo$'s 4) 3ultiplier blo$'s a$$ept t-o 8<.bit binary numbers as inputs and $al$ulate t*e produ$ts 7) 0igital $lo$' manager !0C3" blo$'s pro%ide sel# $alibrating, #ully digital solution #or distributing, delaying, multiplying, di%iding and p*ase s*i#ting $lo$' signals) T*ese elements are organi=ed as s*o-n in t*e diagram) ring o# I24s surrounds a regular array o# CL4s) It *as 4 1 3 $olumns) /a$* $olumn is made up o# se%eral 8<'bit 1 3 blo$'s> ea$* blo$' is asso$iated -it* a deli$ate multiplier) T*e 0C3s are positioned at t*e ends o# t*e outer blo$' 1 3 $olumns) XC3S400 $onsists o# ri$* net-or' o# tra$es and s-it$*es t*at inter$onne$t all #un$tional elements, transmitting signals among t*em) /a$* #un$tional element *as an asso$iated s-it$* matri+ t*at permits multiple $onne$tions as routing)

RESULT% T*us XC3S400 XILINX SP 1T N 3 #ield programmable gate array !FPG " -as studied)

FPGA DESIGN FLOW

AIM% To study FPG design #lo- using XILINX IS/ ?)8 i INTRODUCTION% T*e integrated so#t-are en%ironment !IS/" is t*e Xilin+ design so#t-are t*at allo-s to ta'e t*e design #rom design entry t*roug* Xilin+ de%i$e programming) T*e IS/ design #lo- $omprises t*e #ollo-ing steps, design entry, design synt*esis, design implementation, and Xilin+ de%i$e programming) 0esign %eri#i$ation -*i$* in$ludes bot* #un$tion %eri#i$ation and timing %eri#i$ation, ta'es pla$e at di##erent points during t*e design #lo-) DESIGN ENTRY% 0esign entry is t*e #irst step in t*e IS/ design #lo-) 0uring design entry, sour$es #iles are $reated based on t*e design ob@e$ti%es) T*e top.le%el design #ile $an be $reated using a 5ard-are 0es$ription Language !50L", su$* as 650L, 6erilog or using a s$*emati$) SYNTHESIS% #ter design entry and optional simulation, t*e synt*esis step is run) 0uring t*is step, 650L, %erilog, or mi+ed language designs be$ome netlist #iles t*at are a$$epted as input to t*e implementation step) IMPLEMENTATION% #ter synt*esis, t*e design implementation is e+e$uted, -*i$* $on%erts t*e logi$al design into a p*ysi$al #ile #ormat t*at $an be do-nloaded to t*e sele$ted target de%i$e) From pro@e$t Na%igator, t*e implementation pro$ess $an be run in one step, or ea$* o# t*e implementation pro$esses $an be run separately)

AC! ANNOTATION% 4a$' annotation is t*e translation o# a routed or #itted design to a timing simulation netlist) &ERIFICATION% T*e #un$tionality o# t*e design $an be %eri#ied at se%eral points is t*e design #lo-) T*e simulator so#t-are $an be used to %eri#y t*e #un$tionality and timing o# t*e design or a portion o# t*e design) T*e simulator interprets 650L or %erilog $ode into $ir$uit #un$tionality and displays logi$al results o# t*e des$ribed 50L to determine $orre$t $ir$uit operation) Simulation allo-s to $reate and %eri#y $omple+ #un$tions in a relati%ely small amount o# time) T*e in.$ir$uit %eri#i$ation $an also be run a#ter programming t*e de%i$e) DE&ICE CONFIGURATION% #ter generating a programming #ile, t*e target de%i$e is $on#igured) 0uring $on#iguration #iles are generated and t*e programming #iles are do-nloaded #rom a *ost $omputer to a Xilin+ de%i$e)

RESULT T*us t*e FPG design #lo- -as studied using Xilin+ IS/ ?)8i)

STUDY OF SIMULATION USING XILINX ISE-9.1.i

AIM% To study t*e simulation o# a digital $ir$uit using Xilin+ IS/ ?)8)i INTRODUCTION% 0uring 50L simulation, t*e simulator so#t-are %eri#ied t*e #un$tionality, t*e timing o# t*e design or portion o# t*e design) T*e simulator interprets 650L or 6erilog $ode into $ir$uit #un$tionality and displays t*e logi$al result o# t*e desired 50L to determine $orre$t $ir$uit operation) Simulation allo-s to $reate and %eri#y $omple+ #un$tions in a relati%ely small amount o# time) Simulation ta'es pla$e at se%eral points in t*e design #lo-) It is one o# t*e #irst steps a#ter design entry and one o# t*e last steps a#ter implementation) s part o# %eri#ying t*e end #un$tionality and per#orman$e o# t*e design) Simulation is an iterati%e pro$ess, -*i$* may reAuire repeating until bot* design #un$tionality and per#orman$e timing is met) For a typi$al design, simulation libraries 8) Compilation o# t*e simulation libraries :) Creation o# t*e designs test ben$* 3) Fun$tional simulation 4) Implementation o# t*e design and $reation o# t*e timing simulation netlist 7) Timing simulation SIMULATION LI RARIES 3ost designs are built -it* gentle $ode, so de%i$e spe$i#i$ $omponents are not ne$essary) 5o-e%er in $ertain $ases i# may be reAuired or bene#i$ial to use de%i$e spe$i#i$ation $omponents in t*e $ode to a$*ie%e t*e desired $ir$uit implementation and results -*en t*e $omponent is instantiated in t*e design, t*e simulator must re#eren$e a library t*at des$ribes t*e #un$tionality o# t*e $omponent to ensure proper simulation, XILINX pro%ides simulation libraries #or simulation primiti%es) UNISIM library #or #un$tional simulation o# XILINX primiti%es XILINX $ore library #or #un$tional simulation o# lin+ primiti%es

SIMPRIM lib #or timing simulation o# XILINX primiti%es TEST ENCH

To simulate your design you need bot* t*e design under test !09T" or unit under test !99T" and t*e stimulus pro%ided by t*e test ben$*) test ben$* is 50L $ode t*at allo-s to pro%ide a do$umental, repeatable set o# stimuli t*at is portable a$ross di##erent simulator) test ben$* $an be as simple as a #ile -it* $lo$' and input data or a more $ompli$ated #ile t*at in$ludes error $*e$'ing, #ile input and output and $onditional testing) T*e test ben$* $an be $reated using eit*er o# t*e #ollo-ing met*ods)

"i#

TEXT EDITOR T*is is t*e re$ommended met*od #or %eri#ying $omple+ designs) It allo-s to use all t*e #eatures a%ailable in t*e 50L language and gi%es you #le+ibility in %eri#ying design) lt*oug* t*is met*od may be more $*allenging in t*at one must $reate t*is $ode, t*e ad%antage is t*at it may produ$e more pre$ise B a$$urate results t*an using t*e ben$* -a%e#orm editor)

"ii#

XILINX TEST

ENCH WA&EFORM EDITOR

T*is is t*e re$ommended met*od #or %eri#ying less $ompli$ated simulation tas's, and is re$ommended i# t*e designer is ne- to 50L simulation) It allo-s to grap*i$ally enter t*e test ben$* to dri%e t*e stimulus to t*e design) T*e same test ben$* $an be used #or bot* #un$tions and timing simulation FUNCTIONAL SIMULATION #ter t*e simulation libraries B $reate t*e test ben$* B design $ode are $ompiled, one $an per#orm #un$tional simulation on t*e design) Fun$tional simulation is an iterati%e pro$ess, -*i$* may reAuire multiple simulations to a$*ie%e t*e desired end #un$tionality o# t*e design) R'()*+ % T*us t*e Simulation using XILINX IS/.?)8)i -as studied)

STUDY OF SYNTHESIS USING XILINX ISE 9.1i

AIM%

To study t*e synt*esis o# a digital $ir$uit using XILINX IS/ ?)8i) INTRODUCTION% #ter design entry and optional simulation is done, t*e synt*esis o# t*e design is run) T*e IS/ so#t-are in$lude XILINX synt*esis te$*nology !XST", -*i$* synt*esis 650L or %erilog or mi+ed language designs to $reate X.lin' spe$i#i$ netlist #iles 'no-n as NGC #iles) XST pla$es t*e NGC #iles in t*e pro@e$tor and #ile is a$$epted as input to translate step o# t*e implement design pro$ess) XST INPUT AND OUTPUT FILES% XST supports e+tensi%e 650L and %erilog subsets #rom t*e #ollo-ing standards 650LC I/// 80DE.8?<D, I/// 80DE.8??3, in$luding I/// standards and synopsis) 6erilogC I/// 83E4.8??7, I/// 83E4.:008) A# XILINX CONSTRAINT FILE "XCF#% XCF in -*i$* you $an spe$i#y synt*esis, timing and spe$i#i$ implementation $onstraints t*at $an be propagated to t*e NGC) # CORE FILES% T*ese #iles $an be in eit*er NGC or /0IF #ormat) XST does not modi#y $o%es) It uses t*em to in#orm area and timing optimi=ation) In addition to NGC #iles, XST also generates t*e #ollo-ing #iles or outputs) SYNTHESIS REPORT% T*is report $ontains t*e result #rom t*e synt*esis run, in$luding area and timing estimation) 1# RTC SCHEMATIC% T*is is t*e s$*emati$ representation o# t*e pre.optimi=ed design s*o-n at t*e 1TL) T*is representation is in terms o# generi$ symbols su$* as address, multiples, $ounters, N0 and 21 gates) ,# TECHNOLOGY SCHEMATIC% T*is is a s$*emati$ representation o# an NGC #ile s*o-n in terms o# logi$ elements) 2ptimi=ed to t*e target ar$*ite$ture or te$*nology) It is generated a#ter t*e optimi=ation and te$*nology)

3# HDL PASSING% 0uring 50L passing, XST $*e$'s -*et*er t*e 50L $ode is $orre$ted and reports any synta+ errors) 4# HDL SYNTHESIS% 0uring 50L synt*esis, XST analysis t*e 50L $ode and attempts to in#er spe$i#i$ design building blo$'s or ma$ros #or -*i$* it $an $reate e##i$ient te$*nology implementations) To redu$e t*e amount o# in#erred ma$ros XST per#orms a resour$e s*o-ing $*e$') T*is a$tually leads to a redu$tion o# t*e area as -ell as an in$rease in t*e $lo$' #reAuen$y) -# LOW LE&EL OPTIMI.ATION% 0uring lo- le%el optimi=ation XST trans#orms in#erred ma$ros and general glue logi$ into a te$*nology spe$i#i$ implementation)

RESULT% T*us t*e synt*esis o# digital $ir$uit -as studied using XILINX IS/ ?)8i)

STUDY OF SCHEMATIC ENTRY USING XILINX ISE 9.1i

AIM% To study t*e s$*emati$ entry o# a digital $ir$uit using XILINX IS/?)8i) INTRODUCTION%

S$*emati$s are used #or top le%el or lo-er le%el design #iles) It allo-s to *a%e a %isual representation o# t*e design) TOP LE&EL SCHEMATIC% S$*emati$s are used in t*e top le%el and lo- le%el modules are $reated using any o# t*e #ollo-ing sour$e types) To instantiate a lo-er le%el module in t*e top le%el design and t*e s$*emati$ symbol is instantiated) LOWER LE&EL SCHEMATIC% S$*emati$s $an be used to de#ine t*e lo-er le%el modules o# t*e design) I# t*e top le%el design is s$*emati$ symbol is $reated and it is instantiated in t*e top le%el) I# t*e top le%el design #ile is an 50L #ile a template is $reated) ll s$*emati$s are ultimately $on%erted eit*er 650L or %erilog stru$tural netlist be#ore being passed) SCHEMATIC DESIGN METHODS% F*en using a s$*emati$ t*e top le%el design eit*er o# t*e #ollo-ing met*od is used to des$ribe t*e lo-er le%el modules) i# TOP-DOWN SCHEMATIC DESIGN METHOD% 9sing t*is met*od a top le%el blo$' diagram des$ription o# t*e design is $reated using a s$*emati$) T*en ea$* symbol pus*ed do-n and its be*a%ior is de#ined using 50L or s$*emati$ #ile) 1# SCHEMATIC% T*e s$*emati$ $ontains input mar'ers t*at $orrespond to t*e pins in t*e blo$' symbol $reated) T*e s$*emati$ is built by adding symbols ad des$ribed in adding a symbol)

,# &HDL "OR# &ERILOG% T*e template $ontains 50C port des$riptions t*at $orrespond to t*e pins in t*e blo$' symbol $reated) T*e be*a%ior o# t*e module $an be t*en added) T*e IS/ language template pro%ides a $on%enient met*od to insert) ii# OTTON-UP SCHEMATIC DESIGN METHOD%

9sing t*is met*od a top le%el s$*emati$ design is $reated and lo-er le%el #un$tional blo$'s is t*en $reated to instantiate)

RESULT% T*us t*e s$*emati$ entry o# a digital $ir$uit -as studied using XILINX IS/ ?)8i)

PLACE, ROUTE AND AC! ANNOTATION IN FIELD PROGRAMMA LE GATE ARRAY "FPGA#
AIM% To study t*e pla$e, route and ba$' annotation in FPG ) PLACE AND ROUTE% Pla$e and route is a stage in t*e design o# FPG during -*i$* logi$ elements are pla$ed and inter$onne$ted on t*e grid o# t*e FPG ) s implied by t*e name, it is

$omposed o# t-o steps, pla$ement and routing) T*e #irst step, pla$ement in%ol%es de$iding -*ere to pla$e all ele$troni$ $omponent $ir$uitry and logi$ element in a generally limited amount o# spa$e) T*is is #ollo-ed by routing, -*i$* de$ides t*e e+a$t design o# all t*e -ires needed to $onne$t t*e pla$ed $omponents) T*ese pro$esses are similar at a *ig* le%el but t*e a$tual details are %ery di##erent) Fit* large si=es o# t*e modern designs, t*is operation is usually proportional by /0 tools) MANUAL PLACING AND ROUTING% T*e FPG editor $an be used to #ine tune t*e design and impure t*e per#orman$e o# t*e pla$e and route pro$ess, on$e $an be manually s-apped $omponents and pins as -ell as route and in route nets) F*en t*e design is manually $*anged in FPG editor) F*en a group o# $omponents reAuires spe$i#i$ pla$ements, relationally pla$ed ma$ros are used to de#ine t*e relati%e pla$ements) DIRECTED ROUTING% 0ire$ted routing allo-s t*e design to retain and timing #or a small number o# loads intended sour$es) lt*oug* it is ne$essary to lo$' pla$ement so t*at t*e appropriate routing $an be reprodu$ed) T*e dire$ted routing $annot be used as pla$ement tool) AC! ANNOTATION% It is t*e translation o# a router on #itted design to a timing simulation netlist) 4e#ore timing simulation $an o$$ur t*e p*ysi$al design in#ormation must be translated and distributed ba$' to t*e logi$al design)

NETGEN% It is a $ommand line program t*at distributes in#ormation about delays, set up and *old timer, $lo$' to out and pulse -idt*s #ound in t*e p*ysi$al NC0 design #ile ba$' to t*e logi$al NG0 #ile)

Netgen reads an NC0 as input) T*e NC0 #ile $an *a%e only design as a partially or #ully pla$ed and normal routed design) n NG3 #ile $reated 3 0 is optional sour$e is input) Netgen merges mapping in#ormation #rom t*e optional #ile -it* pla$ement routing and timing in#ormation #rom NC0 #ile)

RESULT% T*us t*e pla$e, route and ba$' annotation in Field Programmable Gate rray !FPG " is studied)