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D1-D4
4 x 1N4007
200
+190 V DC
IC2
2951
R17
100k
100u
Vt
100n
X1
4MHz
C9
47uF D
+ 385V
R25
470k
Q16
MPSA92
R32
100k
C2
C3
C4
C5
C6
10n/200V
10n/200V
10n/200V
10n/200V
10n/200V
10n/200V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR
AN0
AN1
AN2
AN3
RA4
AN4
GND
OSC1
OSC2
RC0
RC1
RC2
RC3
R12
18k
R15
18k
R16
18k
+A
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
+A
SEC
+A
MIN
+A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R14
18k
+A
HR
1
2
3
4
5
6
7
8
9
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
GND
RC7/RX
RC6/TX
RC5
RC4
R13
18k
1
2
3
4
5
6
7
8
9
0
R11
18k
1
D9
5V6
C12
Q15
MPSA92
C1
IC1 PIC16F876
R22
33k
R29
100k
R33
68k
S1
50 Hz / 60 Hz
Q14
MPSA92
R30
68k
C8
100n
R19
1M
R26
100k
R27
68k
S2
Q13
MPSA92
R24
68k
VDD
GND
RB6
UP / DIMM
R23
100k
R21
68k
J1 PGM
Programming socket
RB7
R34
47k
MCLR
R35
47k
Q12
MPSA92
R20
100k
R18
68k
6
R36
47k
Q11
MPSA92
1
2
3
4
5
6
7
8
9
0
/ER
+A
1
2
3
4
5
6
7
8
9
0
330u
D5-D8
4 x 1N5817
FEED
+ C10
+ C11
OUT
GND
IN
ON/OFF
200
+5
60 x
1N4148
+5
C7
100n
R1
33k
Q1
MPSA42
Q2
MPSA42
R2
33k
Q3
MPSA42
R3
33k
Q4
MPSA42
R4
33k
Q5
MPSA42
R5
33k
Q6
MPSA42
R6
33k
Q7
MPSA42
R7
33k
Q8
MPSA42
R8
33k
Q9
MPSA42
R9
33k
Q10
MPSA42
R10
33k
A
Title
Size
Revision
2
B
Date:
File:
1
25-Jun-2002
D:\TST\DIV\NIXIE\MyDesign.ddb
Sheet 1 of 1
Drawn By: OZ2CPU Thomas
6