FPGA design flow

FPGA Design Flow

Design Ideas (Specifications)

Design Entry

Functional Simulation

Device Programming
FPGA CPLD

Timing Simulation
tpd=22.1ns fmax=47.1MHz

Synthesis & Implementation

Design Specification
What are the main design considerations?
Functionality Determine I/O signals Implementation platform Performance power consumption

Cost
Development time

Design Entry
HDL (Hardware Description Language), e.g. Verilog, VHDL
Requires some experience, harder to debug Easy to modify Greater productivity

Schematic
easy to debug Poor designer productivity (gates/time)

Use vendor-supplied IP libraries to reduce design time Create & manage user-created libraries (circuits)

Functional Simulation
Functional simulation
To verify the functionality of the design only.

Preparation for simulation

Generate simulation patterns
Waveform entry HDL testbench

Simulation results
Waveform display Text output Self-checking testbench

Challenge
Sufficient & efficient test patterns

HDL Synthesis
Synthesis = Translation + Optimization
Translate HDL design files into gate-level netlist Optimize according to your design constraints
Area constraints Timing constraints Power constraints

assign z=a&b
a b z

a b

z
FPGA CPLD

Design Implementation
Translate

01011...

- Merges the Netlist and UCF file into a Xilinx design file (NGD) Map - The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs . o/p design is a NCD file. Place and Route - The Place and Route process takes a mapped NCD file, places and routes the design.

Timing Simulation
Post-layout simulation Includes component and wire delays, clock skew. Same input vectors with functional simulation

Device Programming

FPGA CPLD

Downloading the bitstream (bit file) via a download cable

Programming onto a non-volatile memory device &

attaching it on the circuit board

Hardware debugging - Verify the results on the hardware.

Thank you