module moore1010 (inp,clk,rst,y); /*A verilog module for 1010 moore overlapping FSM */ input inp,clk,rst; output reg

y; reg [2:0] current,next; parameter first = 3b000, second = 3b001, third = 3b010, fourth = 3b011, fifth = 3b100; always @ (posedge clk) begin if (rst) current <= first; else current <= next; end always @ (current or inp) begin case (current) first: begin y = 1b0; if (inp == 1b1) next = second; else next = current; end second: begin y = 1b0; if (inp == 1b0) next = third; else next = current; end third: begin y = 1b0; if (inp == 1b1) next = fourth;

else next = first; end fourth: begin y = 1b0; if (inp == 1b0) next = fifth; else next = second; end fifth: begin y=1b1; if (inp == 1b0) next = first; else next = fourth; end default: next = first; endcase end endmodule

Verilog Testbench for 1010 Moore Sequence Detector

module moore1010tstbnch; reg inp,clk,rst; wire y; //mealy1010 mo1 (inp,clk,rst,y); moore1010 mo1 (.inp(inp), .clk(clk), .rst(rst), .y(y)); initial begin rst = 1b0 ; clk = 1b0 ; inp = 1b0; $monitor ($time, , ,I=%b,inp, , ,Y=%b,y, , ,C=%b,clk, , ,R=%b,rst);

#12 inp = 1b1; #12 inp = 1b0; #12 inp = 1b1; #12 inp = 1b0; #12 inp = 1b1; #12 inp = 1b0; #12 inp = 1b0; #12 inp = 1b1; #12 inp = 1b0; #12 inp = 1b1; #12 inp = 1b0; #12 inp = 1b1; end //always #12 inp = ~inp; always #6 clk = ~clk; initial #151 $finish; endmodule