NAND-ONLY LOGIC CIRCUITS

Any logic circuits can be transformed to an implementation where only NAND gates (and inverters) are used.

The general approach to finding a NAND-gate realization: Use DeMorgans theorem to eliminate all the OR operations.

NAND-ONLY LOGIC CIRCUITS

(Example) F = A + B (C + D) = A + B (CD) Note that (CD) = C + D and (AX) = A + X F = (A (B (CD))) Now there is no OR operation in the Boolean expression. Note that A NAND B = (AB)

F= (A (B (CD)))
The logic circuit for this function is given by:

We can also use the same procedure to do NOR only gates.

Ch2. Decoder
Dr. Bernard Chen Ph.D.
University of Central Arkansas Spring 2009

Integrated Circuits

An integrated circuit is a piece (also called a chip) of silicon on which multiple gates or transistors have been embedded

These silicon pieces are mounted on a plastic or ceramic package with pins along the edges that can be soldered onto circuit boards or inserted into appropriate sockets

Integrated Circuits

SSI, MSI, LSI: They perform small tasks such as addition of few bits. small memories, small processors VLSI Tasks: - Large memory - Complex microprocessors, CPUs

An SSI chip contains independent NAND gates

Examples of Combinational Circuits

a) Decoders b) Encoders c) Multiplexers d) Demultiplexers

Decoder

Accepts a value and decodes it

Output corresponds to value of n inputs

Consists of:

Inputs (n) Outputs (2n , numbered from 0 2n - 1) Selectors / Enable (active high or active low)

The truth table of 2-to-4 Decoder

2-to-4 Decoder

2-to-4 Decoder

The truth table of 3-to-8 Decoder

A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 D0 1 1 1 1 1 1 D1 D2 D3 D4 D5 D6 D7

1
1

1
1

0
1

1
1

3-to-8 Decoder

3-to-8 Decoder with Enable

2-to-4 Decoder: NAND implementation

Decoder is enabled when E=0 and an output is active if it is 0

2-4 Decoder with 2-input and Enable

Decoder Expansion

Decoder expansion Combine two or more small decoders with enable inputs to form a larger decoder

3-to-8-line decoder constructed from two 2-to-4-line decoders

The MSB is connected to the enable inputs if A2=0, upper is enabled; if A2=1, lower is enabled.

Decoder Expansion

Combining two 2-4 decoders to form one 3-8 decoder using enable switch

The highest bit is used for the enables

Combinational Circuit Design with Decoders

Combinational circuit implementation with decoders n A decoder provide 2 minterms of n input variables Since any Boolean function can be expressed as a sum of minterms, one can use a decoder and external OR gates to implement any combinational function.

Combinational Circuit Design with Decoders

Example Realize F (X,Y,Z) = (1, 4, 7) with a decoder:

Encoders

An encoder has

2N inputs N outputs

An encoder outputs the binary value of the selected (or active) input. An encoder performs the inverse operation of a decoder. Issues

What if more than one input is active? What if no inputs are active?

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Encoders
D C B A
I0

I1
I2

Out0 Out1

Z Y

I3

A 0 0 0 1

B 0 0 1 0

C 0 1 0 0

D 1 0 0 0

Y 0 0 1 1

Z 0 1 0 1

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Priority Encoders

If more than one input is active, the higher-order input has priority over the lower-order input.

The higher value is encoded on the output

A valid indicator, d, is included to indicate whether or not the output is valid.

Output is invalid when no inputs are active

d=0 d=1
Why is the valid indicator needed?

Output is valid when at least one input is active

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Priority Encoders
msb Valid bit

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Multiplexers

A multiplexer has

N control inputs 2N data inputs 1 output

A multiplexer routes (or connects) the selected data input to the output.

The value of the control inputs determines the data input that is selected.
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Multiplexers

Data inputs Control input

Z = A.I0 + A.I1

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Multiplexers
A 0 0 1 1 B 0 1 0 1 F I0 I1 I2 I3

MSB

LSB

Z = A.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

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Multiplexers
A
0 0 0 0 1 1 1 1

B
0 0 1 1 0 0 1 1

C
0 1 0 1 0 1 0 1

F
I0 I1 I2 I3 I4 I5 I6 I7

MSB

LSB

Z = A.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 + A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

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Multiplexers

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Demultiplexers

A demultiplexer has

N control inputs 1 data input 2N outputs

A demultiplexer routes (or connects) the data input to the selected output.

The value of the control inputs determines the output that is selected.

A demultiplexer performs the opposite function of a multiplexer.

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Demultiplexers
Out0

In

Out1 Out2 S1 S0

Out3

W X Y Z

W = A'.B'.I X = A.B'.I Y = A'.B.I Z = A.B.I

A B
A 0 0 1 B 0 1 0 W I 0 0 X 0 I 0 Y 0 0 I Z 0 0 0

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