ISCAS 2010

CMOS Analog Design Using All-Region MOSFET Modeling 1

CMOS ANALOG DESIGN USING ALL-
REGION MOSFET MODELING: PART I
Carlos Galup-Montoro, Mrcio Cherem Schneider
Federal University of Santa Catarina
Brazil
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 2
CONTENTS
Two-terminal MOS structure
Unified charge control model (UCCM)
Drain current
Pinch-off and threshold voltage
Small-signal parameters
Noise and mismatch compact models
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 3
V
G
G
B
+ + + + + + + + +
Q
I
Q
G
-
-
-
-
-
-
-
-
-
Q
B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TWO-TERMINAL MOS STRUCTURE
gate-to-bulk voltage
oxide capacitance per unit area
surface potential
inversion charge per unit area
bulk charge per unit area
flat-band potential
( )
( )
G ox G FB s I B
Q C V V Q Q

= = +
ox
C

I
Q

B
Q

FB
V
G
V
+

s
_
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 4
MOSFET SMALL-SIGNAL EQUIVALENT CIRCUIT
G
gb
G
dQ
C
dV

=
1
1 1
gb
c ox
C
C C

=
+


I I
i
s t
dQ Q
C
d

=

2
ox
b
s t
C
C

c b i
C C C

= +
body-effect coefficient

thermal voltage
(26 mV @ 300K)
t
kT
q
=
CMOS Analog Design Using All-Region MOSFET Modeling 5
Determination of
Potential balance
0
s
sa
Q
I

=
=
THE LINEARIZATION SURFACE POTENTIAL
sa
G
V
s sa
=
B
Q

+
_
b
C

+
_
0
I
Q

=
0
i
C

=
ox
C

( )
( ) 1
sa t
G FB sa sa sa t
V V sgn e



= + +
( )
( )
( )
/
1
1 1
2sgn 1
sa t
sa t
G b
sa ox
sa sa t
e
dV C
n
d C
e

= = + = +

+
25/05/2010
ISCAS 2010
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 6
UNIFIED CHARGE CONTROL MODEL (UCCM)-1
n
+
n
+
p
V
S
V
G
V
D
1
t
C I
ox I
dV dQ
nC Q

| |

=
|

\
( )
ox b ox
G
C C nC
n n V

+ =
=
I
i
t
Q
C

=
I ox s
dQ nC d

=
S C D
V V V
s i
C i ox b
d C
dV C C C

=
+ +
1
1
I
ox t
Q
nC

<

WI
SI
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 7
7
1
t
C I
ox I
dV dQ
nC Q

| |

=
|

\
Integrating between V
C
and V
P
yields UCCM
ln
IP I I
P C t
ox IP
Q Q Q
V V
nC Q

| |

= +
|

\
UNIFIED CHARGE CONTROL MODEL (UCCM)-2
IP ox t
I
I
ox t
Q nC
Q
q
nC

Thermal charge
Normalized inversion charge density
( 1 ln )
P C t I I
V V q q

= +
Normalized UCCM
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 8
8
I
C s t
I
dQ
dV d
Q


=

( )
I i C s
dQ C dV d

=
C
dV
s
d
G
V
I
i
t
Q
C

=
I
dQ

+
_
DRAIN CURRENT: PAO-SAH MODEL
s t C I
D I I
I
d dV dQ
I WQ WQ
dy Q dy dy


| |

= =
|

\
D
S
V
D I C
V
W
I Q dV
L

,
( , )
G S
D
md I D G
D
V V
I W
g Q V V
V L

= =

drift
I
diff
I
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CMOS Analog Design Using All-Region MOSFET Modeling 9
DRAIN CURRENT: CHARGE-SHEET MODEL
I ox s
dQ nC d

=
( )
2 2
2
IS ID
D t IS ID
ox
Q Q W
I Q Q
L nC

=
(

s I
D I t
d dQ
I WQ W
dy dy

= +
drift diffusion
drift diffusion
2
2
t
S ox
I C n S

=
Normalization (specific) current
2
2
t
SH ox
I C n

=
Sheet normalization (specific) current
W
S
L
=
D F R S f r SH f r
I I I I i i SI i i
( (
= = =

ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 10
10
Long-channel MOSFET
) , ( ) , (
D G S G R F D
V V I V V I I I I = =
I
F
: forward current I
R
: reverse current
I
F
=
I
R
=
FORWARD AND REVERSE CURRENTS
(Forward) Saturation
D F R F
I I I I =
Triode
D F R
I I I =
Triode for V
DS
0
;
F R D F R F
I I I I I I = <<
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 11
MASTER DESIGN EQUATION
2
2
IS
F drift diff t IS
ox
Q W
I I I Q
L nC

= + =
(

ms IS
W
g Q
L

= Pao-Sah model
( )
1
2 /
ms
F ms t
ox t
g
I g
C n W L

(
= +
(

(

( )
( )
/
1
/
th
Dsat WI
W L
I I
W L
(
= +
(
(

or
( ) ( )
/ 2
ms ox t
th
g W L nC

=
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 12
ASPECT RATIO VS. CURRENT EXCESS
( )
( )
/
1
/
th
Dsat WI
W L
I I
W L
(
= +
(
(

ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 13
WEAK, MODERATE, STRONG INVERSION
D F R S f r
I I I I i i
(
= =

( ) ( ) ( ) ( ) ( )
2
2 1 1
f r IS D IS D IS D f r
i q q q i

= + = +
WI MI SI
1 100
f
i < < 1
f
i < 100
f
i <
0.4 9
I
q

< <
9
I
q

<
0.4
I
q

<
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 14
14
Common-source characteristics
( )
1 2 ln 1 1
P S t f f
V V i i
(
= + + +

UNIFIED I-V RELATIONSHIP (UICM)
since
D S f r S f
f r
I I i i I i
i i
(
=

>>
1,00E-09
1,00E-08
1,00E-07
1,00E-06
1,00E-05
1,00E-04
1,00E-03
0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00
10
-3
10
-6
10
-9
V
S
= 0 V
3.0
2.5
2.0
1.5
0.5
1.0
0 1 2 3 4
V
G
(V)
I
D
(A)
V
D
= V
G
WI
MI
SI
V
D
I
D
V
G
V
S
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 15
THE PINCH-OFF CHARGE DENSITY
The channel charge density corresponding to the
effective channel capacitance times the thermal
voltage, or thermal charge, defines pinch-off
( )
IP ox b t ox t
Q C C nC

= + =
The name pinch-off is retained herein for historical
reasons and means the channel potential
corresponding to a small (but well-defined)
amount of carriers in the channel.
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 16
THE PINCH-OFF VOLTAGE V
P
The channel-to-substrate voltage (V
C
) for which the
channel charge density equals the pinch-off charge
density is called the pinch-off voltage V
P
.
UCCM is asymptotically
correct in weak inversion if
in weak
inversion
( ) ( )
2 / 2 /
( 1)
sa F C t sa F C t
V V
I b t ox t
Q C e C n e




= =
2 1 ln
1
P sa F t
n
V
n

(
| |
= +
| (

\

2
P sa F
V
0
2 2
T FB F F
V V + +
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 17
THE THRESHOLD VOLTAGE V
T0
Equilibrium threshold voltage V
T0
, for V
C
=0,
gate voltage for which Q
I
= Q
IP
= -nC
ox

t
(gate voltage for which V
P
=0 )
2
P sa F
V
G FB sa ox sa t
V V C

= +
Recalling that
it follows that
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 18
Pinch-off voltage and slope factor as functions of V
G
[0.18 m CMOS technology].
V
P
[V]
PINCH-OFF VOLTAGE AND SLOPE FACTOR
0 G T
P
V V
V
n

( )
0 1 3 2 ln 1 3 1
P S
V V
(
= = + + +

i
f
=3 at pinch-off
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 19
SATURATION VOLTAGE
Saturation voltage
(V
DSsat
): V
DS
at which
the ratio
ID IS
q q =
,
Saturation voltage versus inversion level
( )
( )
1
ln 1 1 1
DSsat t f
V i

(
| |
= + +
( |
\

( )
1
is the saturation level
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 20
( )
2
1 1
f
S
ms S IS f
S t
di
I W
g I Q i
dV L

= = = +
B mb D md S ms G mg D
V g V g V g V g I + + =
Calculation of g
ms
TRANSCONDUCTANCES
0
mg ms md mb
g g g g + + =
D F R S f r
I I I I i i
(
= =

( ) ( ) ( )
2
2
( 1 ln )
f r IS D IS D
P C t I I
i q q
V V q q

= +

= +
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 21
Transconductance
-to-current ratio
1 1
2
) (
) (
) (
+ +
=
r f
R F
t d ms
i
I
g
1
( )
2
f r
i

WI (i
f
<1)
SI (i
f
>>1)
TRANSCONDUCTANCE-TO-CURRENT RATIO
n
g g
g
md ms
mg

=
ms
mg
g
g
n
=
in saturation:
10
-4
10
-2
10
0
10
2
10
4
i
f
t
ox
= 28 nm (I
S
= 26 nA)
model
10
2
10
1
10
0
g
ms
/I
F
t
ox
= 5.5 nm (I
S
= 111 nA)
Seqncia1
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 22
PARAMETER EXTRACTION
( ) ( )
max
/ 1/
m D t
g I n =
( ) ( )
( )
IS D IS D
IS D
IP ox t
Q Q
q
Q nC

= =

max
2
2
m m
D D IS ID
g g
I I q q
| |
=
|

+ +
\
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 23
INTRINSIC CAPACITANCES
( )
1
gb ox gs gd
n
C C C C
n

=
V
DS
= 1 V
( )
2
2 1 2
3 1
1
IS
gs ox
IS
q
C C
q

+
=
+
+
( )
2
2
2 2
3 1
1
ID
gd ox
ID
q
C C
q

+
=
+
+
( 1)
bd gd
C n C =
( 1)
bs gs
C n C =
1
1
ID
IS
q
q

+
=
+
ox ox
C WLC

=
bg gb
C C =
( )
2 3
3
4 3
15 1
1
ID
sd ox
ID
q
C nC
q

+ +
=
+
+
( )
2
3
4 1 3
15 1
1
IS
ds ox
IS
q
C nC
q

+ +
=
+
+
A set of 9 independent MOSFET capacitances
Channel linearity factor
( ) /
dg gd m sd ds
C C C C C n = =
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 24
SMALL-SIGNAL MOSFET MODEL
G
D
S
B
DB
md DB sd
dv
g v C
dt
+
GB
mg GB m
dv
g v C
dt

SB
ms SB ds
dv
g v C
dt
+
C
gs
C
bs
C
gd
C
bd
C
gb
( ) /
dg gd m sd ds
C C C C C n = =
CMOS Analog Design Using All-Region MOSFET Modeling 25
INTRINSIC TRANSITION FREQUENCY
( ) ( )
2 2
mg
ms
T
gs gb gs gb
g
g
f
C C n C C
= =
+ +
( )
2
2 1 1
2
t
T f
f i
L

+
25/05/2010
ISCAS 2010
26
NOISE & MISMATCH
The spontaneous fluctuations over time of the current
and voltage inside a device, which are basically
related to the discrete nature of electrical charge, are
called electrical noise.
Time-independent variations between identically
designed devices in an integrated circuit due to the
spatial fluctuations in the technological parameters
and geometries are called mismatch.
Mismatch (spatial fluctuation) and noise (temporal
fluctuation) are similar phenomena, both being
dependent on the process, device dimensions, and
bias.
Mismatch can be seen as dc noise.
25/05/2010
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling
THERMAL NOISE EXCESS FACTOR-1
For V
DS
0, the transistor is equivalent to a resistor and
where g
ms
(=g
md
) is the equivalent conductance of the transistor
In weak inversion
For a saturated transistor (g
ms
>>g
md
) in weak inversion
CMOS Analog Design Using All Region MOSFET Modeling 27
2
2
4 4
d IS
ms
i WLQ
kT kTg
f
L

= =

( )
2
4 4
2 2
IS ID
d ms md
Q Q g g i W
kT kT
f L

+ +
=

2
2
d
ms
i
kTg
f
=

25/05/2010
ISCAS 2010
THERMAL NOISE EXCESS FACTOR-2
In general, the channel thermal noise is written as
is the excess noise factor and its value is 2/3 for a long-channel
saturated transistor in strong inversion.
for a short-channel transistor
where L
e
and L
esat
are the electric length of the channel in the
linear and the saturation regions, respectively. Considering that
L
esat
= L
e
-L, where L is the channel shortening due to CLM, then
we can write
for short-channel transistors it is possible that >1 due to the CLM
effect.
CMOS Analog Design Using All Region MOSFET Modeling 28
2
4
d
ms
i
kT g
f
=

2
e I
short
esat I
L Q
L WQ
=

2
1
I
short
e e IS
Q L
L WL Q

| |

+
|

\
25/05/2010
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 29
THERMAL AND 1/F NOISE
10n 100n 1 10 100 1m 10m
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9
(N
ot
=2.6x10
7
cm
-2
)
Thermal Noise
Simulated
(Typ.NMOS model)
Measured
1/f Noise
Simulated
(a)
Simulated
(b)
Measured
S
I
D
/
I
D
2
Drain Current [A]
Normalized flicker and thermal PSD at f=1Hz for saturated NMOS-T
(W/L=200/5)
25/05/2010
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling
30
CORNER FREQUENCY
Noise corner frequency (frequency at which the PSD of the 1/f
noise equals the PSD of the thermal noise)
100n 1 10 100
100
1k
10k
100k
Corner frequency f
c
Calculated from measured g
m
Calculated from estimated g
m
Measured
C
o
r
n
e
r

F
r
e
q
u
e
n
c
y




f
c

[
H
z
]
Drain Current I
D
[A]
2
F
c T
t
K
f f
nq

25/05/2010
ISCAS 2010
F
K
SPICE NLEV 2,3
1/f noise constant
PELGROMS MODEL OF MISMATCH
In most applications: the standard deviation of the difference
between the threshold voltages of two identical transistors
(V
T0
=V
T1
-V
T2
) is
CMOS Analog Design Using All Region MOSFET Modeling 31
( )
( )
0
number of acceptors under gate
/ ( )
T d A ox
ox
V q q WLx N WLC
WLC

= =

( ) ( )
0 0
2
2
d A
VT
T T
ox
q x N
A
V V
C WL WL
= = =

2
d A
VT
ox
q x N
A
C
=

ISCAS 2010
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 32
MISMATCH EXPERIMENTAL RESULTS
Dependence of mismatch on inversion level - Linear: (V
DS
=50mV);
Saturation: (V
DS
=1V) regions. Model :
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 33
CMOS ANALOG DESIGN USING ALL-
REGION MOSFET MODELING: PART II
Carlos Galup-Montoro, Mrcio Cherem Schneider
Federal University of Santa Catarina
Brazil
CONTENTS
The intrinsic gain stage
The source-coupled pair
The two-transistor current mirror
A self-biased current source
A folded cascode amplifier
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 35
SUMMARY OF MAIN DESIGN EQUATIONS - 1
2
/ 2
SH ox t
I C n

=
( )
/
S SH
I I W L =
( )
D F R S f r
I I I I i i = = Specific (normalization)
current
0.35 um CMOS
technology
70 nA
25 nA
SHN
SHP
I
I

Forward and reverse currents

V
DD
V
T0
+
3I
SH
/ 1 W L =
25%
S
I
Sheet specific current
D F S f
I I I i = saturation
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 36
SUMMARY OF MAIN DESIGN EQUATIONS-2
( )
2
1 1
S
m f
t
I
g i
n
= +
Saturation
/
ds D A
g I V =
( )
1 3
DSsat t f
V i = + +
( ) ( )
( )
( ) ( )
1 1 1 ln 1 1
P S D
f r f r
t
V V
i i

+ = + + +
UICM
0 G T
P
V V
V
n

A E
V V L =
Gate transconductance
DS DSsat
V V >
Output conductance
I
D
V
DS
ds
g
A
V
m G
g V
DSsat
V
0
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 37
THE INTRINSIC GAIN STAGE - 1
V
max
V
min
maximum
output swing
V
DSsat1
V
DSsat2
V
DD
V
DD
v
o
v
i V
TH
v
o
=v
i
A
v
( )
01
1 1
1
1 2 ln 1 1
TH T
f f
t
V V
i i
n

+ + +
From UICM we find the dc voltage
V
TH
at the input:
V
DD
V
I
M
1
+
I
B
C
L
I
D
I
L
M
2
V
O
V
DD
I
D
V
O
I
B
V
G
M
1
M
2
Output characteristics
Voltage transfer characteristic
1 1 1
1
;
B
D B F R f
S
I
I I I I i
I
=
0
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling
C
L
g
o
g
m
v
g
v
i
+
v
g
v
o
0
1 1
1 /
o
V m V
i o L b
v
A g A
v g sC s
| |
= = =
|
+ +
\
V-I converter (transconductor)
followed by an I-V converter
(output impedance)
THE INTRINSIC GAIN STAGE - 2
1
1
B
ds
A
I
g
V
=
1 1
0
1
m m
V
o ds
g g
A
g g

= =
1 1 A E
V V L =
1
0
1
1
2
1 1
A
V
t
f
V
A
n
i

=
+ +
38
|A
V
|
dB

b
0
-20 dB/dec
|A
V0
|
Voltage gain vs frequency
/
/
b o L
u m L
g C
g C

=
=
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 39
C
L
g
o g
m
v
g
v
i
+
v
g
v
o
0
1
1
E
V
t
V L
A
n ECF
=
+
min D WI m t
I I g n = =
( )
( )
/ 1 1 / 2
D WI WI f
ECF I I I i = = +
1
2
m
ox t
g W
L C ECF
=

Power-area tradeoff
How long can L be?
Sizing and biasing: W, L, I
B
ECF
C
IN
and transit time are both proportional
to L
2
(for constant W/L)!
THE INTRINSIC GAIN STAGE - 3
1 1
2
f
D t m
i
I n g
+ +
=
m u L
g C =
( )
min min
/
D D D
ECF I I I =
Design example
Specifications:
0
, ,
u L V
C A
How do we choose i
f
?
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 40
2 2
1
4 4 1
ch F m c
ms ms
ox
i K g f
kTg kTg
f WLC f f

| |
= + +
|

\
2
ch
i
Bias-dependent
factor
Thermal 1/f
MOST noise
model
2
F
c T
t
K
f f
nq

Corner
frequency
2 1/ 2
1
3
1 1
f
i

| |
|
=
|
+ +
\
1/2 (WI) 2/3 (SI)
2000
T
c
f
f
0.35 um CMOS
technology
2
/
ch
i f
c
f f
Noise current
generator
Input-referred noise model
2 2
2
1
n ch
m
e i
f g f
=

2
n
e
Noiseless
MOST
- +
THE INTRINSIC GAIN STAGE - 4
CMOS Analog Design Using All-Region MOSFET Modeling
2
/
ch
i f
c
f f
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 41
V
SS
I
T
+
v
G1
-
M
1
M
2
I
1
I
2
+
v
G2
-
First order analysis:
Ideal current source
M
1
& M
2
in saturation I
1
& I
2
independent
of drain voltage;
1 2
1 2
1 2
0
S S S
r r
n n n
I I I
i i
=
=
= =
1 2
1 2
1 2
T
OD
G G id
I I I
I I I
V V V
+ =
=
=
1 1 2 2
/ /
/ /
t T S od OD S
S S
i I I i I I
i I I i I I
= =
= =
Normalization
THE SOURCE-COUPLED PAIR -1
1 2 1 2

t od
i i i i i i = + =
1 1
2 2
ln 1 1 1 1
2 2
id t od t od
t
t od t od
V i i i i
n
i i i i

+
= + + +
(
| | | |
+
+ +
( | |
(
\ \

0 8 4 12 -4 -8 -12
1
i
t
=1000
100
10
<1
I
1
/I
T
I
2
/I
T
id
t
V
n
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 42
V
SS
I
T
+
v
G1
-
M
1
M
2
I
1
I
2
+
v
G2
-
02 01 2 1
;
T T T S S S
V V V I I I = + = +
2
S T
G OS T
m S
I I
V V V
g I

= =
Offset voltage V
OS
= V
G
=V
G2
- V
G1
such that
I
D
= I
2
- I
1
=0
Simple model
( )
0
S m D
G T
D S D
I g I
V V
I I I

+
The differential input voltage at the input required for I
D
=0 is
THE SOURCE-COUPLED PAIR - 2
0
( , )
D S f r S G T S
I I i i I f V V V ( = =

0
( )
0 0
0
@
D D D D
D S G T S m G T S
S G T S
I I I I
I I V V I g V V V
I V V I

+ + = +

ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 43
V
SS
I
T
+
v
G1
-
M
1
M
2
I
1
I
2
+
v
G2
-
( ) ( )
( )
2
2
2 2
2
2
S
T
OS T
m S
I
I
V V
g I

| |
= +
|
\
2
S T
G OS T
m S
I I
V V V
g I

= =
( )
( )
2
2 2
2
2
;
S
VT IS
T
S
I
A A
V
WL I WL

Pelgroms
model
( )
2
2 2
2
2
VT IS T
OS
m
A A I
V
WL g WL

| |
= +
|
\
1 1
2 2
f
T D
t
m m
i
I I
n
g g

| |
+ +
| = =
|
\
Uncorrelated V
T
& I
S
Reminder
IS
A A

=
THE SOURCE-COUPLED PAIR - 3
(I) (II)
(I) is dominant
over (II) for
2
1 1
VT
f
t IS
A
i
n A
+ + <
0
580 ( +0.8 V) for 32 mV,
8 mV m, 2 % m
f G T t
VT
i V V n
A A

< < =
= =
( )
2
2 mV for 16m & 100
OS f
V WL i = <
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 44
THE TWO-TRANSISTOR CURRENT MIRROR - 1
V
DD
i
i
+
v
G
-
i
o
v
o
+
-
M
1
M
2
1:1
M
1
: iv converter
M
2
: vi converter
Basic principle
V
G1
=V
G2
; V
S1
=V
S2
;
v
out
>V
Dsat
i
o
i
i
i
D
v
D
locus
v
D
=v
G
v
G
v
o
i
D1
i
D2
o i o i o i
i i A E
i i v v v v i
i i V V L

=
Error due to difference in V
D
values
Error due to mismatch
0
0
0
1

D D D
S T
D D S T
S m
T
S D
I I I
I V
I I I V
I g
V
I I
| |

+
|

\

( )
( )
( )
2 2
2 2
2 2 2
2 2
1
D S
m m
T VT IS
D D S D
I I g g
V A A
I I I WL I

(
| | | |
( = + = +
| |
(
\ \

( )( )
0
, 1 /
D S f G T S D A D Dsat
I I i V V V V V V V + >
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 45
THE TWO-TRANSISTOR CURRENT MIRROR - 2
( )( )
1 1 2 2 1
1 1 1 2
1
A gs gb gs gb db B
A gs gb db ovd
C C C C C C C
C A C C C C
= + + + + +
= + + + +
1:A
2 m
g v
1
1

m
ds
g
g +
i
i
+
v
-
i
o
C
A
C
B
i
i
i
o
M
1
M
2
V
DD
( )
1
1

1 2
o A B
i m T
I C C A A
s
I s g f

+ +
=
+
i
i
i
o
M
1
M
2
i
1
i
2
1:A
( )
( )
2
2 2 2 2
2 2
1 2
1 1
2 2 2 2 2
1 1


m m
o i
m m
o i
g g
i i i i A
g g
i A i i Ai
| |
= + + =
|
\
= + +
Uncorrelated noise sources
Noise analysis
ac analysis
The effect of M
1
on noise is A times greater than
that of M
2
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 46
Gain-of-two current mirrors
V
DD
I
I
I
O
1/2:1
W/L
W/L
W/L
V
DD
I
I
I
O
1:2
W/L
W/L
W/L
CURRENT MIRROR: GAIN SCHEMES
V
DD
i
i
i
o=
=Ai
i
......
V
DD
i
i
i
o=
=i
i
/A
......
Gain=A
Gain= 1/A
i
i
i
o=
=i
i
/(NM)
.....
.
.
.
.
.
.
.
N
M
Gain=1/(NM)
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 47
A SELF-BIASED CURRENT SOURCE 1
2
1 2 2
1
1
1 1
f f f
S
i i i
S N

(
| |
= + + =
( |
\

2
2 2
2
1 1
1 1 ln
1 1
f
X
f f
t
f
i
V
i i
i

| |
+
|
= + + +
|
+
\
Applying UICM to both M
1
& M
2
SELF-CASCODE MOSFET (SCM)
Sat.
Triode
2 x
I NI =
M
1
M
2
( )
2 2 2
1 1 2
( ) ( 1)
S f r x
S f f x
I i i NI
I i i N I
=
= +
2 1 f r
i i =
0
2
2 2
X X
f
S SH
NI NI
i
I S I
= =
where
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 48
A SELF-BIASED CURRENT SOURCE 2
1 1
1 1 ln
1 1
X
even SH
X X X
t even SH even SH
X
even SH
I
S I
V I I
S I S I
I
S I

| |
+
|
|
= + + +
|
+
|
|
\
1
0.01 S =
2
0.01 S =
I
X
I
X
2I
X
SCM
1,2
1
1 1
even
odd
S
S N

| |
= + +
|
\
/
X t
V
/
X SH
I I
SCM
1,2
SCM
3,4
2
3
0.01 S
=
=
4
18.7
1.13 S
=
=
3
10 S =
4
1.13 S =
I
X
I
X
2I
X
SCM
3,4
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 49
VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)
1
9
ln( )
ref S t
V V JK = +
1
B. Gilbert, AICSP vol. 38, pp. 83-101, Feb. 2004
When both M
8
& M
9
operate in WI:
8
9
8 8
8
1 1
1 1 ln
1 1
f
ref S
f f
t
f
JKi
V V
JKi i
i

| |
+

|
= + + +
|
+
\
A SELF-BIASED CURRENT SOURCE 3
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 50
V
x
VFCM
V
x
A SELF-BIASED CURRENT SOURCE 4
/
X t
V
/
X SH
I I
SCM
1,2
SCM
3,4
VFCM is a positive feedback circuit
return ratio must be < 1 for stability
1
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 51
A SBCS 5: DESIGN
Output current: I
ref
=10 nA
I
SHn-channel
100 nA, I
SHp-channel
40 nA
2
1 2
1
1
1 1 3
S
S N

| |
= + + =
|
\
1 30 1
1 30 1 10 ln 2.93
1 10 1
X
t
V

| |
+
= + + + =
|
|
+
\
2(4)
2(4) 2(4)
2(4)
1 1
1 1 ln
1 1
f
X
f f
t
f
i
V
i i
i

| |
+
|
= + + +
|
+
\
VFCM
Let us choose
i
f3(4)
<<1 (WI)
2.93
3 4 3 4
ln 18.7
X
t
V
e

=
4 4
3 4
3 3
1
1 1 8.85
1
S S
S S

| |
= + + =
|
\
=10 nA
2 2 2 2 1
10 nA 1 nA 0.01
S f S
I i I S S = = = =
Let us choose
4 3 3 4
/ 0.01
f f
i i

= =
4 4 4 4
10 nA 1 A 10
S f S
I i I S = = =
4
3
1.13
8.85
S
S = =
i
f2
= 10, S
2
= S
1
Let us choose
i
f3
=0.187
1
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 52
A SBCS 6: DESIGN
S i
f
i
r
M
1
0.01 30 10
M
2
0.01 10 0
M
3
1.13 0.187 0.01
M
4
10 0.01 0
M
8
, M
8(a)
1 0. 1 0
M
9
, M
9(a)
1 0. 1 0
M
P
(all) 2.5 0.1 0
4
10 S =
VFCM
=1
=10 nA
2
1 0.0 S =
2.93
X t
V =
2.93
X t
V =
3
1.13 S =
1
1 0.0 S =
Summary
Core area in 0.35m CMOS 0.02 mm
2
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 53
A SBCS 7 : I
OUT
vs. V
DD
AT CONSTANT T
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 54
A FOLDED CASCODE AMPLIFIER - 1
I
T
i
o
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
+ -
I
T
I
T
V
DD
GND
to V
B3
+
v
o
-
C
L
v
i1
v
i2
to V
B2
to V
B1
to V
B4
V-I converter Current sources
1:1
High-R
o
current
mirror
M
3
& M
4
common-
gate configuration
I
T
/2
I
T
/2
V
B3
& V
B4
are such that M
9(10)
& M
5(6)
operate on the edge
of saturation
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 55
I
T
i
o
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
+ -
I
T
I
T
V
DD
GND
to V
B3
+
v
o
-
C
L
v
i1
v
i2
to V
B2
to V
B1
to V
B4
V
DD
I
RE
F
M
16
M
1
2
GND
M
1
3
M
1
4
M
1
5
V
B
1
V
B2
V
B3
V
B4
M
17
M
18
0.5 m CMOS
I
SHN
40 nA, I
SHP
16 nA, n
N
n
P
1.2,
V
EN
=V
EP
=10 V/ m, V
T0N
=0.7 V, V
T0P
=-0.9 V,
. =2.5 fF/ m
2
ox
C

C
L
=1 pF, V
DD
=5 V, I
REF
=0.6 A.
Transistor W
(m)
L
(m)
I
D
(A)
i
f
M
1
,M
2
, M
5
-M
8
12.5 1 3 15
M
3
,M
4
5 1 3 15
M
9
,M
10
10 1 6 15
M
11
25 1 6 15
M
12
-M
14
10 4 0.6 15
M
15
6 16 0.6 100
M
17,
M
18
4 4 0.6 15
M
16
7.5 50 0.6 100
A FOLDED CASCODE AMPLIFIER - 2
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 56
I
T
i
o
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
+ -
I
T
I
T
V
DD
GND
to V
B3
+
v
o
-
C
L
v
i1
v
i2
to V
B2
to V
B1
to V
B4
I
SHN
40 nA, I
SHP
16 nA, n
N
n
P
1.2,
V
EN
=V
EP
=10 V/ m, =2.5 fF/ m
2
, C
L
=1 pF
ox
C

Transistor W
( m)
L
( m)
I
D
( A)
i
f
M
1
,M
2
, M
5
-M
8
12.5 1 3 15
M
3
,M
4
5 1 3 15
M
9
,M
10
10 1 6 15
( )
( )
1
1 1
2 /
1 1
SHP
m f
t
I W L
g i
n
= +
=40 A/V
Amplifier transconductance
Output conductance
Voltage gain
0 1
/ 5, 330 V/V
V m o
A g G =
A FOLDED CASCODE AMPLIFIER - 3
10 2 6
4 4 8 8
0.6 0.3 0.3
/ / 48/ 0.3 48/ 0.3
7.5 nA/V
ds ds ds
o
ms ds ms ds
o
g g g
G
g g g g
G
+ +
+ = +

ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 57
I
T
i
o
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
+ -
I
T
I
T
V
DD
GND
to V
B3
+
v
o
-
C
L
v
i1
v
i2
to V
B2
to V
B1
to V
B4
Transistor W
( m)
L
( m)
I
D
( A)
i
f
M
1
,M
2
, M
5
-M
8
12.5 1 3 15
M
3
,M
4
5 1 3 15
M
9
,M
10
10 1 6 15
1
/ 40 /1 A/V/pF
= 40 Mrad/s
m L
GB g C = =
I
SHN
40 nA, I
SHP
16 nA, n
N
n
P
1.2,
V
EN
=V
EP
=10 V/ m, . =2.5 fF/ m
2
, C
L
=1 pF
ox
C

Gain-bandwidth product
Slew rate
max
6 V/ s
o T
L
V I
SR
t C

= = =

Offset voltage
( ) ( ) ( ) ( )
2 2
2 2 2 2 5 9
01 05 09
1 1
m m
OS T T T
m m
g g
V V V V
g g

| | | |
+ +
| |
\ \
( )
( ) ( )
2 2
0
5 1 9 1
2 2
01,5,9
/ ; 10 mV m
/ 1 / 2
8, 8, 10 mV 7.5 mV
T VT VT
m m m m
T OS
V A WL A
g g g g
V V


= =
= =
=
Pairs M
3
-M
4
& M
7
-M
8
contribute
negligibly to the offset voltage
A FOLDED CASCODE AMPLIFIER - 4
(*)
(*) : For this design I
T
=2.5*I
Tmin
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 58
I
T
i
o
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
+ -
I
T
I
T
V
DD
GND
to V
B3
v
i1
v
i2
to V
B2
to V
B1
to V
B4
NOISE ANALYSIS
2 2 2 2
1 5 9
2
no n n n
i i i i
f f f f
| |
| + +
|

\
PSD of the output noise current
Pairs M
3
-M
4
& M
7
-M
8
contribute
negligibly to amplifier noise
A FOLDED CASCODE AMPLIFIER - 5
2
/
(pA/ Hz)
no
i f
(kHz) f
2.5
10
ISCAS 2010
CMOS Analog Design Using All-Region MOSFET Modeling 59
59