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c lp T do Hnh phc
M mn hc: 401039
S tn ch: 03
Loi mn hc:
Bt buc:
La chn:
Gi tn ch i vi cc hot ng:
: 20 tit
Lm bi tp trn lp
: 10 tit
Tho lun
: 15 tit
: tit
T hc
: 60 gi
2. Mc tiu ca mn hc
-
4. Ti liu hc tp
[1]. http://resource.renesas.com/lib/eng/e_learnig/h8_300henglish/
[2]. http://academic.csuohio.edu/simond/courses/eec417/syllabus.html
[3]. http://www.cs.colostate.edu/~cs460/
[4]. Zainalabedin Navabi, Embedded core design with FPGAs, McGraw Hill, 2008
[5]. Jean J.Labrosse, Embedded systems building blocks, 2000, Miller Freeman.
[6]. http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
[7]. http://www.altera.com/literature/hb/nios2/n2sw_nii52002.pdf
[8]. Mt s sch ting Vit c trn th trng.
[9]. Phn mm HEW ca Renesas, Nios II IDE ca Altera.
Nhng bi c chnh: Thit k h thng nhng trn FPGA, Thit k h thng trong mt vi
mch lp trnh c.
im nh gi nhn thc v thi tham gia tho lun, Seminar, bi tp: 10%
im thi gia k: 10%
Hnh thc thi (t lun/ trc nghim/ vn p, hoc bao gm cc hnh thc): t
lun
Sinh vin c tham kho ti liu hay khng khi thi: khng
9. Ni dung chi tit mn hc (ghi tn cc phn, chng, mc, tiu mcvo ct (1)) v
phn b thi gian (ghi s tit hoc gi trong cc ct (2), (3, (4), (5), (6) v (7))
Ni dung
(1)
Chng 1: M u
1.1. Gii thiu
1.2 Tng quan v h thng nhng:
Yu cu, thit k v nh gi mt h
thng nhng
1.3 Cc cng ngh vi x l
1.4
H thng nhng trn c s vi
iu khin v FPGA
10
20
40
20
35
Bi thc hnh 1
Ci t v tm hiu phn mm
Bi thc hnh 2
6
6
Bi thc hnh 3
Bi thc hnh 4
Bi thc hnh 5
Ngi vit
(K v ghi r h tn)
( k)
Nguyn Trng Hi
T trng B mn
(K v ghi r h tn)
TS.H Ngc B
Trng khoa
(K v ghi r h tn)
TS.Nguyn Thanh Phng
TRNG I HC
K THUT CNG NGH TP. HCM
KHOA C- IN-IN T
c lp T do Hnh phc
Tiu chun
con
1. Mc tiu
hc phn
2. Ni dung
hc phn
3. Nhng yu
cu khc
S tn ch: 2
Tiu ch nh gi
2
x
im
1
/3,0
9 n 10
- Tt:
8 n cn 9
- Kh:
7 n cn 8
- Trung bnh:
6 n cn 7
- Khng t:
di 6.