Chapter1. An Overview of VLSI 1.1 Introduction 1.2 What is VLSI? 1.3 Comp e!it" 1.# $esi%n 1.

& 'asic concepts An Overview of VLSI

(his chapter dea s with the )asic concepts of VLSI and VLSI $*SI+,. A few -uestions such as what is VLSI.VLSI $*SI+,? Wh" is VLSI? so on and so forth. (he chapter oo/s at the VLSI $*SI+, f ow and the various options of desi%n that are avai a) e for a desi%ner. 1.1 Introduction (he e!pansion of VLSI is 0Ver"1Lar%e1Sca e1Inte%ration2. 3ere4 the term 0Inte%ration2 refers to the comp e!it" of the Inte%rated circuitr" 5IC6. An IC is a we 1pac/a%ed e ectronic circuit on a sma piece of sin% e cr"sta si icon measurin% few mms )" few mms4 comprisin% active devices4 passive devices and their interconnections. (he techno o%" of ma/in% ICs is /nown as 07IC8O*L*C(8O,ICS2. (his is )ecause the si9e of the devices wi )e in the ran%e of micro4 su) micrometers. (he e!amp es inc ude )asic %ates to microprocessors4 op1amps to consumer e ectronic ICs. (here is so much evo ution ta/en p ace in the fie d of 7icroe ectronics4 that the IC industr" has the e!pertise of fa)ricatin% an IC successfu " with more than 1:: mi ion 7OS transistors as of toda". ICs are c assified /eepin% man" parameters in mind. 'ased on the transistors count on the IC4 ICs are c assified as SSI4 7SI4 LSI and VLSI. (he minimum num)er of transistors on a VLSI IC is in e!cess of #:4:::. (he concept of IC was conceived and demonstrated )" ;AC< <IL'= of (*>AS I,S(8?7*,(S at $a as of ?SA in the "ear 1@&A.(he si icon IC industr" has not oo/ed )ac/ since then. A ot of evo ution has ta/en p ace in the industr" and VLSI is the resu t of this. (his techno o%" has )ecome the )ac/)one of a the other industries. We wi see ever" other fie d of science and techno o%" %ettin% )enefit out of this. In fact the advancements that we see in other fie ds i/e I(4 A?(O7O'IL* or 7*$ICAL4 are )ecause of VLSI. (his )ein% such important discip ine of en%ineerin%4 there is so much interest to /now more a)out this. (his is the motivation for this course name " 0VLSI CI8C?I(S2.

1.2

What is VLSI? VLSI is 0Ver" Lar%e Sca e Inte%ration2. It is the process of desi%nin%4 verif"in%4 fa)ricatin% and testin% of a VLSI IC or C3IB.A VLSI chip is an IC4 which has transistors in e!cess of #:4:::. 7OS and 7OS techno o%" a one is used. (he active devices used are C7OSC*(s. (he sma piece of sin% e cr"sta si icon that is used to )ui d this IC is ca ed a 0$I*2. (he si9e of this die cou d )e 1.&cms!1.&cms. (his die is a part of a )i%%er circu ar si icon disc of diameter 3:cms.(his is ca ed a 0WAC82. ?sin% )atch process4

where in #: wafers are processed simu taneous "4 one can fa)ricate as man" as 124::: ICs in one fa)rication c"c e. *ven if a ow "ie d rate of #:D is considered "ou are ia) e to %et as man" as &::: %ood ICs. (hese cou d )e comp e! and versati e ICs. (hese cou d )e a B*,(I?7 7icroprocessor IC of I,(*L4 or a $SB processor of (I costin% around 8s1:4:::. (hus "ou are i/e " to ma/e 8s&: mi ion 58s&crore6 out of one process f ow. So there is ot of mone" in VLSI industr". (he initia investment to set up a si icon fa)rication unit 5ca ed 0CA'2 in short and a so ca ed sometimes as si icon foundr"6 runs into a few E'i ion. In I,$IA4 we have on " one si icon foundr"1SCL at BunFa) 5Semiconductor Comp e! Ltd.4 in Chandi%arh6. Ver" strin%ent and critica re-uirements of power supp "4 c ean iness of the environment and purit" of water are the reasons as to wh" there are not man" CA'S in India. 1.3 Broducin% a VLSI chip is an e!treme " comp e! tas/. It has num)er of desi%n and verification steps. (hen the fa)rication step fo ows. (he comp e!it" cou d )e )est e!p ained )" what is /nown as 0VLSI desi%n funne 2 as shown in the Ci%ure1.1.

Ci%ure1.1 (he VLSI desi%n tunne

CHAPTER 3.0 PHYSICAL STRUCTURE OF CMOS ICs

3.1 3.2 3.3 3.4 3.

IC Layers MOSFETs CMOS Layers Designing FET array S!""ary Re#eren$es

PHYSICAL STRUCTURE OF CMOS ICs

3 VLSI chip desi%n f ow as discussed in the chapter 14 has two parts name "4 the front1end desi%n and the )ac/ end desi%n. (he front1end desi%n is a a)out o%ic and circuit desi%n of the chip. (he )ac/ end desi%n trans ates the circuit e ements G active4 passive components and their interconnections to respective a"outs. (hese are the a"outs4 which u timate " sit on the si icon die at different a"er eve s to %et the finished IC. (he actua dimensions of these innumera) e po "%ons have to )e desi%ned. (he optima p acin% 5he ps in savin% si icon rea estate6 and routin% 5he ps in achievin% re-uired speed of operation6 of these po "%ons is a so part of the )ac/ end desi%n. (his is ca ed the 0 ph"sica desi%n2. (his chapter discusses the various a"ers that one sees on an IC in %enera and oo/s at the detai s of a C7OS process. A num)er of e!amp e circuits have )een dea t to show how the a"outs are done optima ". (his chapter wi e!amine the ph"sica structure of a C7OS IC as seen at the microscopic si icon eve in the desi%n hierarch". 3.1 IC La"ers An" IC in %enera wi have some conductin%4 semi conductin% and the insu atin% a"ers stac/ed vertica ". (hese are startin% semiconductor wafer4 si icon dio!ide 5insu ator64 diffusion 5or imp ant64 po "cr"sta ine si icon 5%ate materia in1 short1 po "si icon6 and the top meta a"er. ?sin% these a"ers4 %eometrica patterns are done and appropriate connectivit" is esta) ished amon% a the ph"sica patterns. (he a"out detai s of a )asic IC is shown in Ci%.3.1

Gate S P-Substrate 5a6 D

G G SiO2
5)6

A T E

SiO2

Ci%ure.3.1. IC a"out 5a6 cross1sectiona view 5)6 (op view Once the a"out detai s are /nown it is to eva uate the resistance and capacitance va ues of the ph"sica entities sittin% on the si icon. (his is re-uired to eva uate the de a" encountered )" the si%na in f owin% from one component to an other. (he sheet resistance 58s6 of each of the a"ers wi )e /nown in advance. <nowin% the 8s va ue of a a"er4 one can ca cu ate the resistance of the pattern made out of a particu ar a"er. 3.1.1 Sheet resistance (he resistance of a"er with resistivit" and with the dimensions as shown in Ci%.3.2 is %iven )" 8s H L H L. W. t A 3.1 Where A H cross1sectiona area of the a"er4 H 8esistivit" of the a"er materia in ohm1cm4 L H the en%th of the a"er4 W H the width of the a"er4 t H thic/ness of the a"er. In e-uation 3.1 if W H L4 8s H . t H Sheet resistance 5ohms per s-uare6. (hus the sheet resistance of a"er is defined as the resistance offered to the f ow of current )" the a"er of thic/ness 0t2 and a perfect s-uare. If the %iven a"er is not a perfect s-uare4 "ou can ca cu ate e-uiva ent num)er of s-uares 0,2 5H L.W6. (hen the resistance 8 H ,.8s H I.8s. 0I2 5L.W6 is a num)er and it is the reciproca of the aspect ratio.

t L

Ci%ure.3.1. (he %eometr" of a a"er 3.1.2 La"er capacitance <nowin% the area of the a"er and the die ectric constant4 area capacitance can )e ca cu ated usin% the e-uationJ CHA.t 3.2 Where H : ins4 and t H thic/ness of the a"er : H A.A&# !1: G1# C.cm4 Sio2 H #.:4 A H Area of the a"er 3.1.3 $e a" timer constant

(he product of the resistance and the capacitance %ives the de a" time constant 02. (he output of a %ate passes to an input of a %ate throu%h a connectin% wire4 which has a resistance of 8 ine. (here wi )e a capacitance 5%ate capacitance6 at the input of the %ate as shown in the Ci% 3.2. (he si%na wi ta/e 02 seconds to reach the input of the %ate 2 from the output of the %ate 1. +ate1 Line Cin +ate2 8 ine C ine

= Rline. Cin
Ci%ure.3.2 $e a" throu%h the interconnect wire )etween the 2 %ates. 3.2 7OSC*(s Whenever a po "si icon cuts across the diffusion4 at the intersection a 7OSC*( is formed. In )etween these a"ers si icon dio!ide is sand witched and "ou %et the fie d effect. Whi e writin% the a"out dia%rams o!ide a"er wi not )e shown. Other a"ers i/e diffusion4 po "si icon and the meta a"er are shown. (he ,7OSC*( s"m)o and its a"out are shown in the Ci%.3.3. +ate +ate $rain Source 5a6 Ci%ure.3.3 ,7OSC*( a6 s"m)o 4 )6 a"out 3.2.1 Current C ow in a C*( (he current in a ,7OSC*( is due to f ow of e ectrons from source to drain under the inf uence of app ied drain vo ta%e V$$. (he device %oes to on state with V+S V(. 3ere4 V+S is the %ate vo ta%e with respect to the source4 and V( is the thresho d vo ta%e of the enhancement ,7OSC*( under consideration. (hresho d vo ta%e is the %ate vo ta%e with respect to source at which the su)strate underneath the %ate )etween the source and the drain %ets inverted and the ,1channe is formed. ,ow with V$$ on4 the e ectrons move from source towards the drain. And the conventiona drain current f ows from drain to source. (he ma%nitude of the current is proportiona to the tota char%e created in the channe and inverse " proportiona to the transit time of the e ectrons. (he schematic of the ,7OSC*( showin% the current f ow is depicted in the Ci%.3.#. S + $

S
5)6

<e"J

V$$

7eta Bo " si icon $iffusion Cie d o!ide +ate o!ide

s,n n+

n+

Channel P-Substrate
Ci%ure.3.# Schematic of ,7OSC*( with different a"ers (he e!pression for I$S can )e deduced asJ I $S H Char%e in the channe . (ransit time of e ectrons H K . S$ Where S$ H Channe en%th . * ectron drift ve ocit" H L . n *$S H L . n V$S . L H L 2 . n V$S (he channe char%e is %iven )"J K H 1 C + 5V+S G V(6 3.# 3.3

Where C+ H +ate o!ide Capacitance4 as %iven )" *-uation 3.2 Com)inin% *-uations 3.3 and 3.# we %et4 I$S H : o! n W. 5L t o!6 . 5V+S GV(6 .V$S H n. 5V+S G V(6.V$S Where n H %ain factor 5A. V26 3.3 C7OS La"ers C7OS C*(S are fa)ricated usin% three processes4 name " i6 ,1We process ii6 B1 We process and iii6 (win G(u) Brocess. If the process is started with a B1su)strate4 ,7OSC*(s can )e fa)ricated. On the same wafer4 to put B7OSC*(4 one shou d have a ,1 semiconductor. (his active ,1 area is o)tained )" ion imp antation. (his is ca ed the ,1We . =ou shou d have a B1We to accommodate ,7OSC*(s4 if the startin% materia is a ,1su)strate. In the case of twin Gtu) process4 an epita!ia a"er of sin% e cr"sta si icon is %rown )" chemica vapor deposition process 5CV$6. On this a"er4 )oth ,1we and B1We imp ants are done to accommodate B7OS and ,7OS C*(s. (he top view of the patternin% of the C*(s in a ,1We process is shown in the 3.&

Ci%.3.&.Cor the imp ementation of a particu ar o%icL the ,7OSC*(s and B7OSC*(s ma" have to )e connected in series or para e .

n+

n+

n+

n+

P+

p+

P+

p+

N-Well

Ci%ure.3.& (op view of patternin% of the C*(s 3.# $esi%nin% C*( arra"s When a o%ic %ate is imp emented4 ,7OSC*(s are arran%ed in the pu 1down structure. (hese transistors wi depend upon the input pins of the %ate. $ependin% on the 'oo ean e!pression4 these transistors are connected in series4 para e or series1para e com)ination. In an" case these transistors cou d )e arran%ed in an arra". In order to optimi9e the si icon space4 a"out desi%n of these arra"s is a must. Same thin% ho d %ood for the B7OSC*( arra"s4 which come as pu 1up devices )etween V$$ and the output ine. We sha discuss the desi%n of the C*(s connected in series and para e . 3.#.1 ,7OSC*(s in series. para e Si icon patternin% for two ,7OSC*(s connected in series is shown in Ci%.3.&. S1 $2 S2 $1 S1 $2 S2 5a6 5)6 Ci%ure.3.& Si icon patternin% of 2 ,7OS C*(s in series Si icon patternin% of the 2 ,7OSC*(s connected in para e is shown in Ci%.3.M. ! A " 5a6 ' 5)6 $1

Ci%ure.3.M Batternin% of the 2 ,7OSC*(s connected in para e 5a6 Schematic 5)6 La"out

3.#.2 La"out of a ,O( %ate (he circuit schematic and the correspondin% a"out is shown in the Ci%.3.N.In the ,O( %ate ,7OSC*( is connected in series with the B7OSC*(. (he drains of the 2 transistors are connected to the meta wire4 which %oes out as an output ine. Simi ar " the two %ates of po "si icon have )een connected to%ether and the intersection points %oes to the output ine. V$$ ! ! V$$ ! "

VSS 5a6 5)6 Ci%ure.3.N Circuit to a"out trans ation of ,O( %ate (he )asic procedure to adopt whi e drawin% a"out dia%rams for an" o%ic circuit is to ma/e the circuit of the o%ic circuit. (hen identif" the drain and source of the ,7OS and the B7OS transistors. (he source of B7OS wi )e connected to V$$ and the source of the ,7OS wi )e connected to VSS. (he drain5s6 of )ottom most transistor5s6 is 5are6 connected to the drain 5s6 of the top most transistor5s6. (his Function is the output ine. (he po "si icon a"er cuts across the B1diffusion and the ,1 diffusion to form the two transistors and the Function is the input ine. Co owin% the a)ove %iven procedure a"out of an" o%ic %ate can )e easi " drawn. 3.& Summar" (he various a"ers4 which ma/e an inte%rated circuit4 are identified in this chapter. (he a"ers that are stac/ed to%ether for simp e C7OS process are e!p ained. (he o%ic circuits can )e easi " trans ated to the a"outs )" fo owin% standard procedure. (he different a"ers are drawn in different co ours. 'ut a state of art of VLSI chip wi have man" more a"ers. (here cou d )e M11: meta a"ers. When a these a"ers are stac/ed on top of an other4 "ou %et a fat IC. (he a"out detai s of a transistor and the circuit wi %ive "ou a correct picture of the process f ow. (he order in which the a"ers are inte%rated on the su)strate wi )e c ear. 8*C*8*,C*S5for a the 3 chapters6
1.Introduction to VLSI circuits and s"stemsJ ;ohn B. ?"emura4 *dition 2::&4 ;ohn Wi e" O Sons4 Inc. 2.'asic VLSI desi%nJ $.A. Buc/ne 4 <.*shra%hian4 III *dition4 Brentice13a OC India Bvt.Ltd. 3.C7OS $i%ita Inte%rated Circuits GAna "sis and $esi%nJ Sun%1 7o <an%4 =usuf Le) e)ici4 III *dition.4(ata 7c+raw13i Bu) ishin% Compan" L($.4

VSS

#. App ication Gspecific Inte%rated CircuitsJ Smith4 Addison Wes e" 1@@N. &. C7OS Circuit desi%n4 La"out and Simu ationJ 8.;aco) 'a/er4 I*** Bress.42::: M. Brincip e of C7OS VLSI $esi%nJ ,ei Weste and <. *shra%hian Addison Wes e".41@@A.