Aji Widhi Wibowo @2013 Jawaban sebisanya Fundamentals of Digital Logic with VHDL Design 3rd Edition -- S.

Brown & Z.Vranesic

Problem 8.13
Hasil simulasi kode VHDL:

Figure 1: hasil simulasi timing

Figure 2: bentuk sirkuit yang dihasilkan kode VHDL

1|Page| problem 8.13

Aji Widhi Wibowo @2013 Jawaban sebisanya Fundamentals of Digital Logic with VHDL Design 3rd Edition -- S.Brown & Z.Vranesic Kode VHDL menggunakan 2 file terpisah: d_ff.vhd untuk D flipflop dan threebitparitygen.vhd sebagai kode utamanya.
library ieee; use ieee.std_logic_1164.all; package components is component d_ff port(D, Clock : in std_logic; Q : out std_logic); end component; end components; library ieee; use ieee.std_logic_1164.all; use work.components.all; entity threebitparitygen is port(w, Clock: in std_logic; state : buffer std_logic_vector(2 downto 0); P : out std_logic ); end threebitparitygen; architecture bhvr of threebitparitygen is signal Y : std_logic_vector(2 downto 0); begin y0: d_ff port map(Y(0), Clock, state(0)); y1: d_ff port map(Y(1), Clock, state(1)); y2: d_ff port map(Y(2), Clock, state(2)); Y(0) <= (not state(1) and not w) or (state(1) and state(2)) or (w and state(1)); Y(1) <= (not state(1) and state(0) and not w) or (state(2) and state(0)) or (w and not state(1) and not state(0)); Y(2) <= (not w and not state(1)) or (w and state(1)); parity: process (state) begin if state = "101" then P <= '1'; else P <= '0'; end if; end process; end bhvr;

Kode tersebut menggunakan fungsi Y0, Y1, dan Y2 yang didapatkan dari Kmap table eksitasi
Y(0) <= (not state(1) and not w) or (state(1) and state(2)) or (w and state(1));

Y0 = y1 w + y1 y2 + w y1
Y(1) <= (not state(1) and state(0) and not w) or (state(2) and state(0)) or (w and not state(1) and not state(0));

Y1 = y1 y0 w + y2 y0 + w y2 y0
Y(2) <= (not w and not state(1)) or (w and state(1));

Y2 = w y1 + w y1 2|Page| problem 8.13