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    shreetam behera
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    If each instruction in a microprocessor takes 5 clock cycles (unpipelined) and we have a 4 stage pipeline, the ideal average CPI with the pipeline will be ________? d. What are the characteristics of RISC pipelining? e. What do you mean by Speed up in pipelining approach?

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    If each instruction in a microprocessor takes 5 clock cycles (unpipelined) and we have a 4 stage pipeline, the ideal average CPI with the pipeline will be ________? d. What are the characteristics of RISC pipelining? e. What do you mean by Speed up in pipelining approach?

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    15 views1 page

    Vlsisa 2

    Uploaded by

    shreetam behera
    If each instruction in a microprocessor takes 5 clock cycles (unpipelined) and we have a 4 stage pipeline, the ideal average CPI with the pipeline will be ________? d. What are the characteristics of RISC pipelining? e. What do you mean by Speed up in pipelining approach?

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    of 1

    Centurion University of Technology and Management Centurion Institute of Technology, Jatni

    M.Tech 1stSemester

    2nd Internal Test


    VLSI SYSTEM ARCHITECTURE
    Time:-1 Hr F.M.:- 30

    1. Answer all Questions (compulsory): a. What are the properties of RISC architecture? b. What do you mean by pipelining stalling?

    [2*5=10]

    c. If each instruction in a microprocessor takes 5 clock cycles (unpipelined) and we have a 4 stage pipeline, the ideal average CPI with the pipeline will be ________? d. What are the characteristics of RISC pipelining? e. What do you mean by Speed up in pipelining approach?

    2. Answer any two Questions:

    [2*10=20]

    a. Discuss the hardwired control and micro-programmed control for CISC architecture? b. Explain about different pipelining hazards? How can you avoid data hazard? (5+5) c. Write short notes on any two(5+5) Cache memory Instruction level Parallelism Pipelining

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