MATERIALS SCIENCE & ENGINEERING

ELSEVIER Materials Science and Engineering A199 (1995) 45-51

For a n e w educational strategy for ULSI microelectronics

Georges Kamarinos
Laboratoire de Physique des Composants ~ Semiconducteurs, 23, rue des Martyrs, BP 257, 38016 Grenoble Cgdex 1, France

Abstract

It is well established today that the development of integrated circuits, for at least the next decade, will be mainly based on scaleddown CMOS technology on silicon (0.1/zm channel length, 108 transistors per chip, 10 ps delays...). A mass and efficient fabrication must be based on two principles: (1) scientific fabrication, which means a sequence of sharply controlled physico-chemical processes; (2) physical (not empirical) modeling and simulation of the working of the devices and of their coupling. In this paper, it is first shown that such an approach needs to go back to the "first principles" of physics (as 50 years ago when semiconductors came into view). Among the necessary physics developments in the domain of the physical-chemistry and of solid state physics, one can cite: molecular dynamics; very thin oxidation and its relation to microroughness and surface states; non-Fickian diffusion; microcontamination; electromigration; exact solution of the Boltzmann transport equation (taking into account the electronic structure of the material, the transient regime and the quantum effects); analysis of the electric, electromagnetic and phononic coupling of devices and their noise; etc.; Then it is shown that these developments need: (1) a revision of the classical educational program for microelectronics materials and processes; a list of "new" topics to-be-developed is given; (2) a very tight coupling of R&D industrial laboratories with university teams; they have to work on the same space and with the same equipment for technology research projects (doctor degree preparation). The above two points can constitute the framework for a new educational strategy involving, in a new base, a closer collaboration between university and industry. Finally, it is shown that Grenoble can be a strong pole in an efficient European Network for the 21st century silicon microelectronics.
Keywords: Silicon; Microelectronics; Integrated circuits; Electronics education

1. I n t r o d u c t i o n : microelectronics

the importance

of silicon

It is well established today that in the heart of an electronic system, the signal processing unit is the principal element; this unit is composed of electronic devices belonging to one or more integrated circuits (IC). The development of these IC, and consequently the development of computers, is based on the continuous development of silicon microelectronics (Si-pe). This technology goes continuously to: higher speeds (frequencies), higher scaling-down (miniaturization), higher densities (higher number of transistors per cm2), higher complexity (higher number of functions in a chip). During the last decade the IC are characterized by an increase of: 1.1 5/year in scaling-down, 1.31/year in den0921-5093/95/$09.50 1995 Elsevier Science S.A. All rights reserved S S D I 0921-5093(95)09906-9

sity, 1.40/year in complexity, 1.24/year in speed. Stating that Si microelectronics is very important for economic development is not sufficient: one has to add that CMOS technology (Complementary Metal-OxideSemiconductor) will cover probably more than 80% of the world market of ICs in a few years (Fig. 1); in the same figure one can see that Si will continue to cover 99% of the market when other semiconductors (like GaAs) will continue to share only 1% of the same IC world market [1]. It is thus evident that education concerning the physical-chemistry and the physics of: the silicon material, the physicochemical processes involved in the fabrication of the electronic devices, the transport of carriers in electronic devices, when they are scaled-down, are of paramount importance for research and the industry engineers for the immediate future.

46

G. Kamarinos I Materials Science and Engineering A199 (1995) 45-51

100 go
80 70

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I

112% 1987
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1982 ($10.2B)

1991 ($52.2B) 1990 ($47.8B)

1996

($I07.0B)

YEAR
Fig. 1. World market for IC (1982-1996).

2. Today's state-of-the-art and expected progress for the beginning of the 21st century in silicon microelectronics
The R & D laboratories of the most important industries today develop and study [1,2]: D R A M (memory) of 256 Mbit, transistors (MOST) of channel length (L) of 0.25/~m, integrated circuits having 108 MOSTs per chip, devices of a speed of 100 ps, processes on wafers of diameter 200 mm, This is the V L S I (Very Large Scale Integration) step of Si-/~e. In the more advanced basic research laboratories today: the M O S T of length L of 1000/k or less is a " c o m m o n " object; the M O S T of 100/~ is fabricated and it works [3,4], the M O S T of (a channel length of) 300 ~ is correctly modelled and simulated for its electrical working) [5]. The trend for the first decade of the 21st century is the fabrication of the Giga-Chip; this IC will be:

a CMOS circuit, memory of, at least, 1 Gigabit; it will be thus possible to transmit: 10 Gigabit information/s, or to process: 1 GIPS (Giga-instructions/s); such an integrated circuit will have: 10 l MOS transistors (the human brain has 10 ~2 neurons). the channel length of a M O S T in such a chip will be

50oA,
the speed of the M O S T will be on the order of 10 ps, the Si wafer, in the beginning of fabrication, will have a diameter of 300 mm. This will be the ULSI (Ultra Large Scale Integration) step of Si-/~e. The cost of an industrial setting (pilot-line and peripherals) for such a fabrication is higher than 109 US dollars [6]. It is therefore evident that a concentration of invested capital for such a strategic activity is unavoidable. Such industries will exist only in economically healthy countries where an important source of flexible and competent technicians, engineers and researchers will be available in place.

G. Kamarinos / Materials Science and Engineering A199 (1995) 45-51

3. M a t e r i a l remaining needs science and development technological problems of Si-/te: and educational

47

The development of Si-/~e depends on the advancement of the knowledge and the technological progress concerning: (a) the technical processes of fabrication; (b) the working of the devices and the integrated circuits. (Evidently the design, the CAD, the architecture and testing of IC are very important, but these fields are not discussed in the present approach.) In the following paragraphs, a very brief review of the more important remaining problems of Materials Sciences and Physics concerning the above items, (a) and (b), is given. Education orientations are suggested.
3.1. Technical p r o c e s s e s

The lithography drives the rate of the development of Si-/~e. Phase shift deep ultraviolet (P-S) lithography for the near future (for lines of 100 nm) will replace the optical lithography (x = 400 nm) of today. For the ULSI step (L < 1000/~) probably electron beam lithography will be operational [7]. The problems facing this kind of lithography are essentially two: (i) the back scattering of secondary electrons; (ii) the coulombian interaction of primary electrons. Oxidation [8] is also a key step in the fabrication. It ensures not only the isolation between different devices (thick oxides) but also the gate isolation (very thin oxides or other dielectrics). Thin gate oxidation (thickness not lower than 30 A) is a very important step for ULSI and several physicochemical problems have now to be examined; one can cite [9]: native oxidation (0-20 ]k), the influence of surface microroughness in thin oxidation, the influence of surface microcontamination (Ns < 101 cm -2) to thin oxidation, the relationship between electrical breakdown and surface microroughness [ 10], the relationship between the electrical barrier in the interface (Si/SiO2) and the oxide thickness, the preparation of ultra-clean oxides (to avoid dispersion of the threshold voltage of the MOS transistor), etc. The physics of ion implantation at very low energies (3-15 keV) and with strong currents, for the fabrication of shallow junctions (xj < 500/~) constitute the more important problem to be faced [11]. The Fickian approach for diffusion is always of the highest interest and particularly' the defect-assisted diffusion in preamorphization steps (for shallow junctions). The macroscopic approach of the diffusion allows a nu-

merically possible calculation of 2D or 3D impurity profiles [12,13]. The CVD-PVD [14] (chemical and physical vapor deposition) techniques are, of course, of rapidly increasing interest. Indeed modern microelectronics has "become" a surface science [15]; but the more important processes are, yet, approached with an empirical and macroscopic view, which is not satisfactory for reaching the requirements of modeling and simulation of devices and circuits [16]. We need therefore a "scientific approach" to: surface reactions kinetics far from thermodynamic equilibrium; one has to take this into account in such an approach, the dynamics of gas flux near the surface, among other problems one can also cite selective epitaxy, rapid thermal annealing has to be described and examined also in the light of non-equilibrium thermodynamics. The return to basic and classical thermodynamics and the emergence of non-equilibrium thermodynamics and molecular dynamics for nearly all the physico-chemical steps of fabrication is the principal and the essential characteristic of the new educational era for silicon microelectronics. These "first principles" or elementary (particular) approaches can give solid indications for the establishment of macroscopic laws for oxidation, diffusion and vapor deposition of thin films; these laws can then be inserted into R&D simulation numerical programs. This remark is also valid for the synthesis of silicides (in particular germanium alloys) [17] and for more complex phenomena such as electromigration [19] which now constitutes a serious drawback of scaling-down as it threatens the reliability of the circuits. For this phenomenon, an abundant literature exists but a satisfactory description of the failure (of metallic lines) process as well as the solution to technical problem are yet unknown. ULSI silicon microelectronics requires a minimum in the dispersion of the electrical characteristics of the tremendous number of devices on a chip. This non-dispersion can be reached only by a very homogeneous fabrication on a Si wafer. Consequently each elementary process must be exactly known and firmly controlled in the environment and for the geometry of the R&D equipment. The ULSI requires a scientific fabrication which ensures a minimum number of random defects in the circuit. In this context the role of microcontamination [9,20] on the surface as well as in the bulk of the material emerges as a first order item. It is known that the "zerodefect" scientific fabrication needs the control of the influence of very low concentration of contaminants: Nss < 10 9 cm -2 in the surface of less than 10 I1 cm -3 in the bulk of the material [20]. So a number of very exciting metrological problems await solution:

48
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G. Kamarinos I Materials Science and EngineeringA199 (1995)45-51

How to measure these concentrations in a (already doped or processed) surface or volume? How to detect a particle of 0.03/zm size locally in the clean room of the R&D laboratory? How to measure two foreign particles in a milliliter of a liquid used in a process in an R&D environment? (to the above metrology challenges one can add the difficulties of temperature, and AT, measurement in situ). The above very brief review of the problems arising in scientific fabrication, required by ULSI Si-/te, points out that research activities concerning fabrication cannot be performed far from the environment of the R&D laboratory. The absolute necessity of the injection of the basic research activities in the R&D laboratories is a new requirement. It is so evident that R&D laboratories connected with the industrial centers must fund the insertion of basic (university groups) research teams in their environment; a direct consequence of this remark is also that a part of the activity and the equipment of such a laboratory must serve the education of future engineers and researchers for ULSI Si-/ze.
-

The channel length of the elementary MOS transistor will satisfy 200/~ < L < 1000 A,, ULSI line width

3.2. Physics of working ULSI devices and circuits

The design and the simulation of working VLSI ICs are based implicitly, up to now, on the partition principle [21,22]. According to this principle an IC is a network of discrete devices which are operating discretely; they communicate only by established metallic connections. This principle holds for the "macroscopic scale" of integration where the channel length L of a MOS transistor is longer than the mean free path of electrons l, and l is very much longer than the radius of the collisions of carriers with the lattice << l < L, macroscopic scale

The macroscopic scale of integrations holds so that when L is higher than 0.3/zm. For this scale all transport phenomena can be satisfactorily approached with the concepts of effective mass (m*eff), the bands of electron energies, etc.; the current is strongly connected to the electric field (except for very high frequencies (f> 100 GHz) and the conduction regime is stationary. The simulations of I,V characteristics of such devices are based on hydrodynamic-like equations or, better, on the classical integration of the Boltzmann equation. Even high field effects are classically approached with sufficient accuracy. The future ULSI IC will include devices which will be characterized by ~. << l = L, intermediate scale

Here the partition principle fails, indeed: The screening effects and the corresponding lengths depend on fields and geometry; the injection of charge is not efficient and the "vertical quantification" in the channel drives many transport global coefficients and effects. Inertial effects appear; the current is not highly coupled with the electrical field (in time and space); the transport becomes ballistic, the electron velocity overshoot is observed and the collision cross sections depend on fields. In this step of integration, the Boltzmann treatment of electronic transport is still valid if perturbation methods are applied and high electric field effects are well approached in spite of their complexity [23]. For higher levels of integration, the nanostructures on Si will be analyzed as quantum objects; their interconnections will be seen as de Broglie wave guides and the analysis of the influence of the high electric fields is yet unknown [24]. Evidently these structures probably will come after the ULSI step but even today the 9, fl structures, the permeable base transistor and the nanoparticular systems (e.g. diodes on porous silicon) constitute 2D, 1D or 0D nanostructures on silicon [25-29] (Fig. 2), There are two important problems due to the scalingdown and the high density of integration; they are caused by two types of effects: the high electric field effects which provoke the degradation (ageing) of the devices and the failure or the loss of the reliability of an integrated circuit [30], the inter-devices coupling effects which affect the reliability of the IC [21,22]. (a) The high electric fields ( E > 106V/cm) and the conduction by hot carders result in the: injection into oxides (gate and isolation oxides), generation of crystalline defects near the drain or into the gate oxide; impact ionization near the drain; increase in the electrical noise of the transistor ( l l f excess noise). To avoid these effects or to remediate them one must intervene at two levels: in the design and fabrication of the device and of the circuit (to find geometries softening the field near the drain, drain engineering, to enhance the quality and the purity of oxides, avoid microntamination and control microroughness, to know exactly the 2D profile of impurity diffusion), in the modeling of the working of the device and of the circuit (to lower the drain voltage, VD goes to 1 V, to identify exactly the more sensitive transport
-

G. Kamarinos / Materials Science and Engineering A199 (1995) 45-51

49

e" beam X - rays ion beams

10 p.m 1 ~tm

6~
10 "1~ s

/
I~l

DUV

Optical lithography (OL Industrial Depletion layer

_ ]

0,1 p.m 100,~ 10~ I

10"~2s

I....
10-13s 10-14s

approx, fail~ Debye length * Retarded transport Mean free path Quantum regime de Broglie electron wavelength ~-e Cellular dimensions

Approximation meff fails

1oo A

1 pm

nteratomic spacing 100 ~m

Attainable linewidths * Existing "laboratory" devices R-D "research-development" devices R "research" devices

Fig. 2. Lithography linewidth and characteristic lengths for silicon. Ferry's diagram for present devices.

parameters and to measure them, to know exactly the 2D transport of carriers). To develop a detailed knowledge of the working of a device the Mont6-Carlo methods of resolution of the Boltzmann transport equation coupled with the energy distribution and dissipation (and, to take into account quantum effects, the Schr/Sndinger equation) must be developed [31 ] and transferred to R&D laboratories. The advanced numerical method of resolution of nonlinear differential equations are of growing importance for future engineers. (2) The inter-device coupling is due to the high density of the devices in a chip (more than 107 MOST per cm2). The classical coupling, i.e. capacitive of electromagnetic (for high frequencies) is satisfactorily approached by classical methods of elementary electrostatics and electromagnetism. On the contrary, thermal coupling has been neglected up to now but this situation is rapidly changing [31,32]. The slowing down of thermalization of phonons due to selection rules in the Si/SiO2 interface is an exciting problem for solid state physics. The noise in very small devices, its dispersion and its non-stationarity and non-ergodicity constitute another exciting problem which is now studied after the observation of the Random Telegraph Signal Noise (RTS) which is a one-electron phenomenon observed at room temperature [33-35]. This problem is evidently connected with the concepts of local equilibrium in a system far from thermodynamic equilibrium.

Evidently the noise is not, in first order, an inter-device effect; nevertheless its dispersion for ULSI IC can seriously affect the reliability and, so, low frequency noise can constitute a limitation for scaling down [33-35]. Another class of effects which will emerge in this scale of integration are the cooperative effects due to strong electrical non-linear coupling of the devices [21,22]; tunneling effects, superlattice effects and chaotic effects are already observed in several situations. The influence of the above effects is now considered as a drawback for the ULSI, but a new idea is slowly emerging. All these cooperative effects can be positively exploited in a new architecture of integrated circuit where the emergence of these effects is favored; the era of "holistic integration" would therefore be open: the circuit now works as a whole and not as a system of connected discrete devices. It is evident that to analyze and describe the working of ULSI devices, the quantum mechanics approach of ULSI structures, the Boltzmann treatment of transport with advanced numerical methods, the introduction of advanced concepts of irreversible thermodynamics and statistical mechanics as well as the methods of treatment of the chaotic effects must enter the Educational Program of future engineers and researchers. On the contrary, in the situation concerning fabrication processes, basic (university) research can blossom and can be developed outside of R&D groups. Evidently a tight collaboration between R&D groups and university teams is absolutely necessary. The R&D laboratory can then furnish the university group with the advanced devices for characterization and comparison with modeling and simulation; the two groups can collaborate for the definition of long term objectives and thus, for their common program. The mutual benefits of such a collaboration is obvious.
4. Conclusion

Some years ago for good engineering in silicon microelectronics, it was sufficient to know that a semiconductor is a system of two electron reservoirs with electronic localized states in the gap. The carrier concentrations are described by Fermi statistics and the currents are approached by hydrodynamical equations. With this elementary background, it was possible for an engineer to understand and model the usual devices and circuits [36]. Concerning the fabrication, classical chemistry and physical chemistry of equilibrium were sufficient and some complicated situations were approached by empirical laws. Now advanced VLSI and the beginning of the ULSI era are rapidly changing the landscape; quantum mechanics is again necessary to understand the electric transport in inversion layers, numerical treatment of the Boltzmann transport equation is used for modelling the I,V character-

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G. Kamarinos / Materials Science and Engineering A199 (1995) 45-51

istics and the statistical m e c h a n i c s and irreversible therm o d y n a m i c s are n e e d e d to understand and exploit c o o p erative and i n t e r - d e v i c e c o u p l i n g effects. C o n c e r n i n g the fabrication the necessity for the return [37,38], to basic "first p r i n c i p l e s " and the end o f empirism is obvious. T h e p r o g r a m s o f E d u c a t i o n m u s t therefore be drastically revisited. O u r analysis also s h o w s that university research m u s t be closer to the R & D laboratories. In the c a s e o f research (and education o f doctor d e g r e e students) w e s u g g e s t that the university groups must w o r k in the s a m e p l a c e and with the s a m e e q u i p m e n t as the R & D groups. F o r studies c o n c e r n i n g the electrical working o f d e v i c e s and circuits, the two types o f groups can c o n s e r v e their g e o g r a p h i c a l i n d e p e n d e n c e . S u c h a s c h e m e o f c o l l a b o r a t i o n is possible in several places in E u r o p e . F o r e x a m p l e G r e n o b l e , in France, is a p l a c e w h e r e strong university groups ( C N R S laboratories) and large R & D laboratories ( C N E T / C N S , L E T I / C E A ) strongly c o n n e c t e d to Industry ( S G S - T H O M S O N ) exist. O n e can find there the b e g i n n i n g o f such a collaboration w h i c h for the m o m e n t exists o n l y due to a voluntary impulsion. References [1] G. Courtois, CAD and testing of IC's and systems; where are we going? TIMA/CNRS/INPG Grenoble, May 1993. [2] (a) IEE (Journal of Electronic Engineering); spotlighting: semiconductors and ICs: the latest development trends on SRAMs, ASSP LSIS, ASICs, Flash memories, MOSFETs etc. Collection of technical review articles 29(308) (1992). (b) IEEE MICRO: chips, systems, software, and applications. Special issue, Microelectronics in Europe, August (1992). [3] A. Harstein, Ultra-short channel Si MOSFET. Electrochemical Society Spring Meeting, Washington, DC, 1991, pp. 432-433. [4] Electronics: At IEDM, future IC's reach limits of theoretical physics, (1993) p. 3 (review article). [5] D.J. Franck, S.E. Laux and M.V. Fischetti, MontE-Carlo simulation of a 30 nm Dual-Gate MOSFET: how short can Si do ?. International Electron. Devices Meeting: IEDM 92, 1992, sponsored by E.D Soc. of IEEE Technical Digest, 1992, pp. 553-556. [6] D. Bois, Perspectives techniques et 6conomiques des composants intEgrEs. L'onde dlectrique 73(6) (1993) 4-10. [7] C. Morgan, Giin Shan Chen, C. Boothroyd, S. Bailex and C. Humphreys, Ultimate limits of lithography, Phys. World, 5(11) (1992) 28-32. [8] E.A. Lewis and E.A. Irene, Models for the oxidation of silicon, J. Vac. Sci. TechnoL A, 4(3) (1986) 916-925. [9] T. Ohmi and T. Shibata, Scientific ULSI manufacturing in 21st century. The electrochemical Society, Interface, 1 (1992) 32-37. [10] S. Verhaverbeke, Dielectric breakdown in thermally grown oxide layers. Thesis, Katholieke University Leuven, Imec, 1993. [11] L. Laanab, G. Bergaud, M.M. Faye, D. Faure, A. Martinez and A. Claverie, A model to explain the variation of "end of range" densities with ion implantation parameters, Mater. Res. Soc. Syrup. Proc., 279 (1993) 381-386. [12] S. List, P. Pichler and H. Ryssel, Atomistie evaluation of diffusion theories for the diffusion of dopants in vacancy gradients. Simulation of Semiconductor Devices and Processes, Vol. 5, SpringerVerlag, Vienna, 1993, pp. 97-100. [13] M.E. Law, Achieving accurate 3D process simulation. Simulation

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