The ARM Processor Architecture

Seminar: Vorname: Name: Matr-Nr.: E-Mail:

Multimedia Ioannis Skazikis 637868 Ioannis.Skazikis@MNI-Fh- iessen.!e

Table of contents: ". Some words about ARM #. Introduction of the ARM's core families and their benefits #." $%er%ie& o' ()M*s +urrent 'amilies o' their main +ores #.# ,he E%olution o' the ()M ar+hite+ture #.3 !e%elo-ment Value #.. )edu+in/ S0stem 1osts #.2 ,he ()M -rodu+t roadma3. Explanation of the ARM architecture 3." (r+hite+ture 3asi+s 3.# ,!MI 3.#." ,hum3 "6-3it instru+tions 3.#.# !e3u/ E4tensions 3.#.3 Em3eddedI1E lo/i+ . Archtecture details! features " comparison of the ARM#! ARM$! and ARM%& core families .." ()M7,!MI 5ro+essor 1ore .."." ()M7,!MI-S ..".# ()M7#6, ..".3 ()M7E7 ..# ()M S1"66 ..3 1om-arison o' the ()M7,!MI &ith the ()M8,!MI 'amilies ... ()M8,!MI 5ro+essor 1ore ...." ()M8.6, Ma+ro+ell ....# ()M*s 8.6, +ore stru+ture ....3 ()M8#6, Ma+ro+ell ..... ()M8##, ....2 ()M8#6, and ()M8##, MM9 ....6 ()M8E Famil0 ....6." ()M8E 1ore (r+hite+ture ....6.# ()M866E-S ....6.3 ()M8.6E-S ....6.. ()M8.6E-S 1a+hes ....7 ()M8E7-S 1ore (r+hite+ture ....7." ()M8#6E7-S ..2 ()M"6E (r+hite+ture Enhan+ements ..2." :i/h 5er'orman+e Features ..2.# ()M"6#6E and ()M"6##E ..6 Ve+tor Floatin/ 5oint ;VF5"6< ..7 Famil0 Summar0 '. Some words about the ARM's AM(A architecture ) An open bus standard *. +e,words 7. Resources

%. Some words about ARM

()M desi/ns mi+ro-ro+essor te+hnolo/0 that lies at the heart o' ad%an+ed di/ital -rodu+ts= 'rom mo3ile -hones and di/ital +ameras to /ames +onsoles and automoti%e s0stems= and is leadin/ intelle+tual -ro-ert0 ;I5< -ro%ider o' hi/h--er'orman+e= lo&-+ost= -o&er-e''i+ient )IS1 -ro+essors= -eri-herals= and s0stem-on-+hi- ;So1< desi/ns throu/h in%ol%ement &ith or/anizations su+h as the Virtual So+ket Inter'a+e (llian+e ;VSI(< and Virtual 1om-onent E4+han/e ;V1><. ()M also o''ers desi/n and so't&are +onsultin/ ser%i+es. ()M*s ar+hite+ture is +om-ati3le &ith all 'our ma?or -lat'orm o-eratin/ s0stems: S0m3ian $S= 5alm $S= @indo&s 1E= and Ainu4. (s 'or so't&are= ()M also &orks +losel0 &ith &ith its -artners to -ro%ide o-timized solutions 'or e4istin/ market se/ments. ,hese 3ene'its are makin/ the ()M +om-an0 a +om-lete solution -ro%ider.

.i/ure &%- Some products that currentl, use ARM technolo/,.

@ith o%er 'ort0 -artners li+ensed to use its ar+hite+ture= ()M ena3les ori/inal eBui-ment manu'a+turers ;$EM< to realize an a++elerated time-to-market throu/h +om-lete -rodu+t o''erin/s= su+h as 5rime1ell 5eri-herals= em3edded so't&are I5= de%elo-ment tools= trainin/= and su--ort.

.i/ure &0- ARM's Partnership 1ompanies

,he +om-an0 o''ers a +om-lete solution that is essential to the manu'a+turin/ -ro+ess. (lthou/h ()M does not manu'a+ture -ro+essors itsel'= ()M li+enses its +ores to semi-+ondu+tor manu'a+turers to 3e inte/rated into (SI1 standards and then the +om-an0 in usin/ test +hi-s manu'a+tured 30 its -artners to measure and %alidate the 'un+tionalit0 o' the +ore. ()M is a3le to a++elerate $EM time-to-market 30 +a-italizin/ on its ar+hite+ture. C0 -ro%idin/ the I5 and su--ortin/ ser%i+es= +ustomers +an /ain a ?um- on their desi/n +0+le and o3tain a +om-etiti%e ed/e in their tar/eted market se/ment. (t that -oint= the ar+hite+ture is -orta3le to 'urther -rodu+t /enerations or a--li+ations as all +ode +reation is dire+tl0 +om-ati3le &ith an0 'uture ar+hite+ture -rodu+ed 30 ()M. ()M*s lo3al ,e+hnolo/0 5artner Net&ork is the lar/est in the industr0= s-annin/ 'rom semi+ondu+tor manu'a+turers to distri3utors. ()M has &orked dili/entl0 to ensure that the -artnershi-s -ro%ide -ro%en solutions in real-time o-eratin/ s0stems ;),$S<= E!( tools= de%elo-ment s0stems= a--li+ations so't&are= and desi/n +onsultin/= all 3uilt around the ()M ar+hite+ture.

.i/ure &3- ARM 2orldwide 3etwor4

,he ()M +om-an0 is &orkin/ to esta3lish standards= not ?ust &ithin the +om-an0= 3ut a+ross the industr0 30 takin/ ad%anta/e o' leadershi- o--ortunities in the +reation o' standards.

.i/ure & - ARM's 2orldwide Standarts

,his 3lo+k dia/ram des+ri3es the ()M solution. ,he +om-an0 re+o/nizes that it +annot ?ust -resent hardened ma+ros and s0nthesiza3le 159s to the industr0= 3ut it must also -ro%ide the (SI1 in'rastru+ture in the 'orm o' (MC(= the 5rime1ell 5eri-herals= and models and modelin/ tools 'or the +ores. ,here is also the need 'or ()M to -ursue -orts 'or ),$Ss= de%elo- de3u/ hard&are and so't&are de%elo-ment tools= and= o' +ourse= em3edded so't&are 'or Do''-the-shel'D inte/ration. ()M +om3ines all these 'utures to/ether &ith su--ort and trainin/= to a++elerate the desi/n +0+le and 'a%our a su++ess'ul -rodu+t.

.i/ure &'- ARM's solution

Sumur0 : ()M is the industr0 standard em3edded mi+ro-ro+essor ar+hite+ture= and is a leader in lo&--o&er hi/h -er'orman+e +ores. ()M also has a lar/e -artner net&ork su--ortin/ the entire desi/n and de%elo-ment +0+le. ()M is a 'ull-solutions -ro%ider= su--ortin/ a 3road ran/e o' a--li+ations.

0. Introduction of the ARM's 1ore .amilies and their benefits #." $%er%ie& o' ()M*s +urrent 'amilies o' main +ores: ,he ()M7 and ()M8 'amilies ha%e +ontri3uted to ()M*s su++ess. Ea+h +ore 'amil0 has se%eral D+hildrenD that in+or-orate man0 di''erent %alue-added 'eatures and +om3inations. Essentiall0= there are 'our main 'amilies a%aila3le no& 'or li+ense: ()M7= ()M8= ()M8E-S= and ()M"6. ,he ()M7 'amil0 'eatures hardened and s0nthesiza3le ma+ro+ells &ith %ariants that in+or-orate +a+he &ith either a memor0 -rote+tion unit ;M59< or memor0 mana/ement unit ;MM9<. $ther 'eatures in+lude real-time de3u/ ;),!< and real-time tra+e ;),,< te+hnolo/0. ,he ()M8 'amil0 +onsists o' hardened ma+ro+ells &ith %ariants also in+ludin/ +a+he &ith an M59 or MM9= as &ell as the ),! and the ),,. (lthou/h the ()M8E-S 'amil0 &as released under a di''erent ar+hite+ture %ersion= ()M%2,E= the 'undamental desi/n o' the +ore is 3ased on the ()M8,!MI 'amil0. ,he DED identi'ies that the 'amil0 is a !S5-enhan+ed ar+hite+ture and the DSD identi'ies that the 'amil0 is s0nthesiza3le. ,he ()M"6 'amil0 is the hi/hest -er'orman+e 'amil0 to date and &ill also em3od0 the DED e4tensions that &ere de%elo-ed 'or the ()M8E-S 'amil0. Finall0= the Stron/()M and >S+ale 'amilies are ()M +om-liant ar+hite+tures a%aila3le 'rom Intel. #.# ,he E%olution o' the ()M ar+hite+ture:

.i/ure &*- E5olution of the ARM Architecture (r+hite+ture V" &as im-lemented onl0 in the ()M" 159 and &as not utilized in a +ommer+ial -rodu+t. (r+hite+ture V# &as the 3asis 'or the 'irst shi--ed -ro+essors. ,hese t&o ar+hite+tures &ere de%elo-ed 30 (+orn 1om-uters 3e'ore ()M 3e+ame a +om-an0 in "886. ('ter that introdu+ed ()M the (r+hite+ture V3= &hi+h in+luded man0 +han/es o%er its -rede+essors. ,hese +han/es resulted in an e4tremel0 small and -o&er-e''i+ient -ro+essor suita3le 'or em3edded s0stems. (r+hite+ture V.= +o-de%elo-ed 30 ()M and !i/ital Ele+troni+s 1or-oration= resulted in the Stron/ ()M series o' -ro+essors. ,hese -ro+essors are %er0 -er'orman+e-+entri+ and do not in+lude the on+hi- de3u/ e4tensions. ,his ar+hite+ture &as 'urther de%elo-ed to in+lude the ,hum3 "6-3it instru+tion set ar+hite+ture ena3lin/ a 3#-3it -ro+essor to utilize a "6-3it s0stem. ,oda0= ()M onl0 li+enses +ores 3ased on (r+hite+ture V., or a3o%e. ,he latest ar+hite+tures= %ersion 2,E and 2,E7= em3od0 added instru+tions 'or !S5 a--li+ations and the 7azelle-7a%a e4tensions= res-e+ti%el0. 1urrentl0= the ()M8E and "6E 'amil0 o' -ro+essors are the onl0 im-lementations o' these ar+hite+tures. !etails on these ar+hite+tures and +ores &ill 3e -ro%ided later in the +ourse.

#.3 !e%elo-ment Value: From a de%elo-ment stand-oint= ()M +ores o''er the ad%anta/e o' a 'ull0 3#-3it -ro+essor desi/ned s-e+i'i+all0 'or em3edded a--li+ations. (n im-ortant 'eature is the em3edded +ore de3u/ 'a+ilities= &hi+h redu+e the de3u//in/ sta/e o' de%elo-ment. In some +ases= this +an 3e t&o-thirds o' the o%erall de%elo-ment +0+le. (r+hite+ture +om-ati3ilit0 allo&s +ode re-use and results in redu+ed desi/n time. ,his in turn leads to redu+ed s0stem +ost= 30 eliminatin/ in%estment in a se+ond set o' de%elo-ment tools to &rite +ode 'or a ne& -ro+essor ar+hite+ture. ,he modular a--roa+h o' the ad%an+ed mi+ro-+ontroller 3us ar+hite+ture= ;(MC(<= ena3les desi/n reuse. ,his lo&ers the +om-le4it0 o' s0stem on-+hi- ;So1< desi/ns and redu+es 'uture desi/n +osts. ()M and third -arties o''er the de%elo-er -ro%en +om-iler te+hnolo/0 and de3u/ solutions. Multi-le ),$Ss and sili+on sour+es mean that the de%elo-er &ill not need to +han/e the -re'erred %endor in order to mi/rate to this ar+hite+ture. #.. )edusin/ S0stem 1osts:

.i/ure &#- Example of Redusin/ S,tems 1osts Fi/ur*s 67 dia/ram sho&s the ad%anta/es o' +om3inin/ the 'un+tions -er'ormed 30 se-arate 159s into a sin/le= hi/h--er'orman+e S0stem-on-1hi- 3ased on an ()M -ro+essor. In the inte/rated solution= there is no du-li+ation o' memor0= memor0 +ontrollers= 3uses= and -ins. Sa%in/s +an 3e %er0 hi/h i' o''-+hi- memor0 su3s0stems +an 3e re-la+ed 30 a sin/le memor0 s0stem usin/ +ommodit0 !)(M or S!)(M.

#.2 ,he ()M -rodu+t roadma-:

.i/ure &6- ARM's Product Roadmap Sin+e the introdu+tion o' the ()M7 ar+hite+ture= there has 3een hu/e lea-s in +ore -ro+essin/ -er'orman+e. (s sho&n here= ()M 'amilies -ro%ide a &ide ran/e o' -er'orman+e= 'rom "66 MI5S to "666 MI5S. ,his in+rease in -er'orman+e +an 3e attri3uted to t&o main dri%in/ 'a+tors. ,he most o3%ious 'a+tor is the ad%an+es that ha%e 3een made in ne& -ro+ess te+hnolo/ies. ,he other is the en/ineerin/ +han/es im-lemented in ea+h su3seBuent /eneration o' ()M -ro+essors and ar+hite+tures. S-e+i'i+ e4am-les in+lude a ne& -i-eline in the ()M8 'amil0= and the im-lementation o' a :ar%ard 3us ar+hite+ture in the ()M 8 o%er the Von Neumann ar+hite+ture in the ()M7. ,he result is that the ()M8 'amil0 dou3les the -er'orman+e o' the ()M7 'amil0. )e+ent de%elo-ments in+lude !S5 and 7azelle-7a%a e4tensions to some o' the ne& ar+hite+tures. ,hese -rodu+ts ena3le 'eature ri+h a--li+ations to 3ene'it 'rom the hi/h--er'orman+e and lo& -o&er +onsum-tion intrinsi+ to ()M -ro+essor +ores. Ce+ause o' the 'a+t that true em3edded +ontrol a--li+ations t0-i+all0 reBuire a -ro+essor &ith +a+he and memor0 -rote+tion to utilize real-time o-eratin/ s0stems= ()M has de%elo-ed a %erti+al e4-ansion o' 159s to mat+h these reBuirements. Ea+h -ro+essor -ro%ides a uniBue= and in some +ases +on'i/ura3le= amount o' +a+he. For e4am-le= the ()M8E-S 'amil0 o''ers the a3ilit0 to +on'i/ure the size o' instru+tion and data +a+he= as &ell as the a3ilit0 to +on'i/ure ti/htl0 +ou-led S)(M 3lo+ks. ,hese 'eatures ena3le 0ou to +ustom 'it the 159 to s-e+i'i+ a--li+ation reBuirements. Man0 other 'eatures +an 3e added %ia the +o--ro+essor inter'a+e= su+h as the Ve+tor Floatin/ 5oint unit 'or the ()M"6 and ()M8E 'amilies. In other &ords= ()M has -rodu+ed ar+hite+tural 'amilies that are +om-ati3le= 'le4i3le= and en+om-ass the 'ull ran/e o' em3edded reBuirements. Ea+h -rodu+t is desi/ned to allo& multi-sour+in/ at e%er0 le%el o' de%elo-ment. ()M is no& the de-'a+to standard in em3edded I5.

3. Explanation of the ARM architecture 3." (r+hite+ture 3asi+s ()M +ores use a 3#-3it= Aoad-Store )IS1 ar+hite+ture. ,hat meanins that the +ore +annot dire+tl0 mani-ulate the memor0. (ll data mani-ulation must 3e done 30 loadin/ re/isters &ith in'ormation lo+ated in memor0= -er'ormin/ the data o-eration and then storin/ the %alue 3a+k to memor0. ,here are 37 total re/isters in the -ro+essor. :o&e%er= that num3er is s-lit amon/ se%en di''erent -ro+essor modes. ,he se%en -ro+essor modes are used to run user tasks= an o-eratin/ s0stem= and to e''i+ientl0 handle e4+e-tions su+h as interru-ts. Some o' the re/isters &ith in ea+h mode are reser%ed 'or s-e+i'i+ use 30 the +ore= &hile most are a%aila3le 'or /eneral use. ,he reser%ed re/isters that are used 30 the +ore 'or s-e+i'i+ 'un+tions are r"3 is +ommonl0 used as the sta+k -ointer ;S5<= r". as a link re/ister ;A)<= r"2 as a -ro/ram +ounter ;51<= the 1urrent 5ro/ram Status )e/ister ;15S)<= and the Sa%ed 5ro/ram Status )e/ister ;S5S)<. ,he S5S) and the 15S) +ontain the status and +ontrol 3its s-e+i'i+ to the -ro-erties the -ro+essor +ore is o-eratin/ under. ,hese -ro-erties de'ine the o-eratin/ mode= (A9 status 'la/s= interru-t disa3leEena3le 'la/s and &hether the +ore is o-eratin/ in 3#-3it ()M or "6-3it ,hum3 state.

.i/ure &$- The ARM's Re/ister 7r/ani8ation ,here are 37 total re/isters di%ided amon/ se%en di''erent -ro+essor modes. Fi'/ure 68 sho&s the 3ank o' re/isters %isi3le in ea+h mode. 9ser mode= the onl0 non--ri%ile/ed mode= has the least num3er o' total re/isters %isi3le. It has no S5S) and limited a++ess to the 15S). FIF and I)F are the t&o interru-t modes o' the 159. Su-er%isor mode is the de'ault mode o' the -ro+essor on start u- or reset. 9nde'ined mode tra-s unkno&n or ille/al instru+tions &hen the0 are -assed thou/h the -i-eline. (3ort mode tra-s ille/al memor0 a++esses as a result o' 'et+hin/ instru+tions or a++essin/ data. Finall0= s0stem mode= &hi+h uses the user mode 3ank o' re/isters= &as introdu+ed to -ro%ide an additional -ri%ile/ed mode &hen dealin/ &ith nested interru-ts. Ea+h additional mode o''ers uniBue re/isters that are a%aila3le 'or use 30 e4+e-tion handlin/ routines. ,hese additional re/isters are the minimum num3er o' re/isters reBuired to -reser%e the state o' the -ro+essor= sa%e the lo+ation in +ode= and s&it+h 3et&een modes. FIF mode= ho&e%er= has an additional 'i%e 3anked re/isters to -ro%ide more 'le4i3ilit0 and hi/her -er'orman+e &hen handlin/ +riti+al interru-ts. @hen the ()M +ore is in ,hum3 state= the re/isters 3anks are s-lit into lo& and hi/h re/ister domains. ,he ma?orit0 o' instru+tions in ,hum3 state ha%e a 3-3it re/ister s-e+i'ier. (s a result= these instru+tions +an onl0 a++ess the lo& re/isters in ,hum3= )6 throu/h )7. ,he hi/h re/isters= )8 throu/h )"2= ha%e more restri+ted use. $nl0 a 'e& instru+tions ha%e a++ess to these re/isters.

3.0 T9MI ,-!-M-I stands 'or: Thum3= &hi+h is a "6-3it instru+tion set e4tension to the 3#-3it ()M ar+hite+ture= re'erred as states o' the -ro+essor. D9D and DID to/ether +om-rise the on-+hi- de3u/ 'a+ilities o''ered on all ()M +ores. ,hese stand 'or the 9e3u/ si/nals and Em3eddedI1E lo/i+= res-e+ti%el0. ,he M si/ni'ies the su--ort 'or 6.-3it results and an enhan+ed multi-lier= resultin/ in hi/her -er'orman+e. ,his multi-lier is no& standard on all ()M%. ar+hite+tures and a3o%e. 3.0.% ,hum3 "6-3it Instru+tions @ith /ro&in/ +ode and data size= memor0 +ontri3utes to the s0stem +ost. ,he need to redu+e memor0 +ost leads to smaller +ode size and the use o' narro&er memor0. ,here'ore ()M de%elo-ed a modi'ied instru+tion set to /i%e market-leadin/ +ode densit0 'or +om-iled standard 1 lan/ua/e. ,here is also the -ro3lem o' -er'orman+e loss due to usin/ a narro& memor0 -ath= su+h as a "6-3it memor0 -ath &ith a 3#-3it -ro+essor. ,he -ro+essor must take t&o memor0 a++ess +0+les to 'et+h an instru+tion or read and &rite data. ,o address this issue= ()M introdu+ed another set o' redu+ed "6-3it instru+tions la3eled ,hum3= 3ased on the standard ()M 3#-3it instru+tion set. For ,hum3 to 3e used= the -ro+essor must /o throu/h a +han/e o' state 'rom ()M to ,hum3 in order to 3e/in e4e+utin/ "6-3it +ode. ,his is 3e+ause the de'ault state o' the +ore is ()M. ,here'ore= e%er0 a--li+ation must ha%e +ode at 3oot u- that is &ritten in ()M. I' the a--li+ation +ode is to 3e +om-iled entirel0 'or ,hum3= then the se/ment o' ()M 3oot +ode must +han/e the state o' the -ro+essor. $n+e this is done= "6-3it instru+tions are 'et+hed seamlessl0 into the -i-eline &ithout an0 result. It is im-ortant to note that the ar+hite+ture remains the same. ,he instru+tion set is a+tuall0 a redu+ed set o' the ()M instru+tion set and onl0 the instru+tions are "6-3itG e%er0thin/ else in the +ore still o-erates as 3#-3it. (n a--li+ation +ode +om-iled in ,hum3 is 36H smaller on a%era/e than the same +ode +om-iled in ()M and normall0 36H 'aster &hen usin/ narro& "6-3it memor0 s0stems.

(n e4am-le: ()M7,!MI Clo+k !ia/ram Fi/ure "6 sho&s the re/ister 3ank in the +enter o' the dia/ram= -lus the reBuired address 3us and data 3us. ,he multi-lier= in-line 3arrel shi'ter= and (A9 are also sho&n. In addition= the dia/ram illustrates the in-line de+om-ression -ro+ess o' ,hum3 instru+tions &hile in the de+ode sta/e o' the -i-eline. ,his -ro+ess +reates a 3#-3it ()M eBui%alent instru+tion 'rom the "6-3it ,hum3 instru+tion= de+odes the instru+tion= and -asses it on to the e4e+ute sta/e.

.i/ure %&- ARM#T9MI (loc4 9ia/ram

3.#.# !e3u/ E4tensions ,he !e3u/ e4tensions to the +ore add s+an +hains to monitor &hat is o++urrin/ on the data -ath o' the 159. Si/nals &ere also added to the +ore so that -ro+essor +ontrol +an 3e handed to the de3u//er &hen a 3reak-oint or &at+h-oint has 3een rea+hed. ,his sto-s the -ro+essor ena3lin/ the user to %ie& su+h +hara+teristi+s as re/ister +ontents= memor0 re/ions= and -ro+essor status. 3.#.3 Em3eddedI1E Ao/i+ In order to -ro%ide a -o&er'ul de3u//in/ en%ironment 'or ()M-3ased a--li+ations the Em3eddedI1E lo/i+ &as de%elo-ed and inte/rated into the ()M +ore ar+hite+ture. It is a set o' re/isters -ro%idin/ the a3ilit0 to set hard&are 3reak-oints or &at+h-oints on +ode or data. ,he Em3eddedI1E lo/i+ monitors the ()M +ore si/nals e%er0 +0+le to +he+k i' a 3reak-oint or &at+h-oint has 3een hit. Aastl0= an additional s+an +hain is used to esta3lish +onta+t 3et&een the user and the Em3eddedI1E lo/i+. 1ommuni+ation &ith the Em3eddedI1E lo/i+ 'rom the e4ternal &orld is -ro%ided %ia the test a++ess -ort= or ,(5= +ontroller and a standard IEEE "".8." 7,( +onne+tion. ,he ad%anta/e o' on-+hi- de3u/ solutions is the a3ilit0 to ra-idl0 de3u/ so't&are= es-e+iall0 &hen the so't&are resides in )$M. ,his is +riti+al in shortenin/ the de%elo-ment +0+le. ,he use o' MultiI1E and Em3eddedI1E -ro%ides 'ull de3u/ +a-a3ilities 'or a -ro+essor inte/rated dee- inside an (SI1= e%en in a -rodu+tion %ersion o' a +onsumer -rodu+t.

. Archtecture details! features " comparison of the ARM#! ARM$! and ARM%& core families .." ()M7,!MI 5ro+essor 1ore

(r+hite+ture %ersion .,: -- 3-sta/e -i-eline -- 9ni'ied 3us ar+hite+ture -- 3#-3it ()M IS( -lus "6-3it ,hum3 e4tension For&ard +om-ati3le +ode Em3eddedI1E on-+hi- de3u/ :ard Ma+ro+ell I5 -- Smallest !ie Size: 6.23 mm# on 6."8 Im -ro+ess 9- to ""6 M:zJ on ,SM1 standard 6."8 Im Industr0 leadin/ 6.#2 m@EM:z .i/ure %%- ARM#T9MI 1ore

,he ()M7,!MI has a +ore 3ased on the 'ourth %ersion o' the ()M ar+hite+ture. ,his im-lementation uses a three sta/e -i-eline - a standard 'et+h-de+ode-e4e+ute or/anization. It 'eatures a uni'ied +a+he= as &ell as the ,hum3 e4tension -ermittin/ 3#-3it and "6-3it o-eration. It is +om-letel0 'or&ard +om-ati3le= meanin/ that an0 +ode &ritten 'or this +ore &ill 3e +om-ati3le &ith an0 ne& +ore releases= su+h as ()M8 or ()M"6. ,his +ore also in+ludes the on-+hi- de3u/ e4tension dis+ussed in the -re%ious trainin/ module. ,he +ore is su++ess'ul mainl0 3e+ause o' the e4tremel0 small 3ut hi/h -er'orman+e -ro+essor sli/htl0 more than 76=666 transistors in all an &ith e4tremel0 lo& -o&er +onsum-tion.

.."." ()M7,!MI-S

S0nthesiza3le ),A +om-liant &ith the ()M7,!MI 1ustom Ma+ro+ell: -- Full0 +om-ati3le &ith the ()M%., ar+hite+ture. -- )i/ht denied to modi'0 ()M7,!MI instru+tion set. -- 1o-ro+essor inter'a+e allo&s +ustom 'un+tions to 3e added outside +ore. -- Em3eddedI1E su--ort &ith DMulti-I1ED -roto+ol +on%erter or third -art0 de%i+e. Su--orts (MC( inter'a+e: -- Standard inter'a+e= ideal 'or inte/ration o' the +ore into an (SI1 desi/n. Su--orts 'ull-s+an and automati+ test -attern /enerator. .i/ure %0- ARM#T9MI)S 1ore

Fi/ure "# -resents a model o' the ()M7 -ro+essor that is a s0nthesiza3le %ersion o' the ()M7,!MI. ,his %ersion is 'ull0 +om-ati3le &ith the ()M%., ar+hite+ture and is 'un+tionall0 identi+al to the hardened ()M7,!MI ma+ro+ell. (lthou/h it is a s0nthesiza3le solution= the li+ensee does not ha%e the ri/ht to +han/e an0 'eature o' this +ore.

..".# ()M7#6,

1a+hed Ma+ro+ell 'or 5lat'orm $S (--li+ations ()M7,!MI +ore: -- ()M %., IS( -- ,:9MC "6-3it instru+tion set -- )e% 3 on&ards su--orts E,M7 'or non-sto- de3u/ 8 KC +a+he: -- :i/h -ro+essor -er'orman+e &ith lo&-s-eed memor0 inter'a+e Memor0 Mana/ement 9nit: -- Full su--ort 'or @indo&s1E and S0m3ian $S (SC 3us inter'a+e .i/ure %3- ARM#0&T 1ore

()M7#6,+ore o''ers 8 KC o' uni'ied instru+tion and data +a+he. (lso in+luded is a memor0 mana/ement unit ;MM9< that o''ers %irtual-to--h0si+al address translation= 6.-entr0 translation lookaside 3u''er ;,AC<= t&o-le%el -a/e ta3les stored in memor0= and hard&are -a/e-ta3le &alkin/. ,here is also a hi/hl0 'le4i3le ma--in/ s+heme that su--orts " MC se+tions &ith -ermissions= 6. KC lar/e -a/es &ith 'our sets o' -ermissions= and . KC small -a/es &ith 'our sets o' -ermissions. ,his -ro+essor ena3les u- to "6 domains= ea+h &ith indi%idual a++ess ri/hts. It also 'eatures +0+li+ re-la+ement and lo+kdo&n 'eatures to lo+k instru+tions or data into +a+he 'or +riti+al real-time +ode. ,he ()M7#6, &as desi/ned to 3e 'le4i3le and a--li+ation-s-e+i'i+= es-e+iall0 'or de%i+es runnin/ +om-le4 o-eratin/ s0stems su+h as Ainu4= @indo&s 1E= S0m3ian $S= or 5alm$S. It in+ludes a s0stem +ontrol +o-ro+essor 'or +a+he and s0stem initialization and the (MC( (d%an+ed S0stem Cus= or (SC= inter'a+e.

..".3 ()M7E7

Ne& 7azelle-enhan+ed 3#-3it -ro+essor +ore ,hum3= 7azelle and !S5 e4tensions Fi%e sta/e -i-eline and hi/h -er'orman+e multi-lier 9ni'ied instru+tion and data 3us %2,E7 ar+hite+ture )eal-time tra+e &ith the E,M8 ma+ro+ell 1onta+t ()M 'or a%aila3ilit0 and +hara+teristi+s data

.i/ure % - ARM#E: 1ore ,he ()M7E7 solution is a +om-a+t 159 s-e+i'i+all0 desi/ned 'or a--li+ations demandin/ lo& -o&er +onsum-tion. It has a memor0 inter'a+e identi+al to that o' the ()M7,!MI-SL +ore. It 'eatures the V2,E7 ar+hite+ture instru+tions= in+ludin/ !S5 e4tensions. ,his +ore im-lementation also 'eatures a 'i%e-sta/e -i-eline similar to that o' an ()M8 +lass -ro+essor= and su--orts eas0 inte/ration o' the Em3edded ,ra+e Ma+ro+ell-8 'or real-time-tra+e +a-a3ilit0.

..# ()M S1"66 Se+ure 1ode

$-timized -ro+essor 'amil0 'or smart +ard solutions Se+urit0 enhan+ed ()M7,!MI desi/n -- ()M%., +om-liant -- Ao& -o&er= hi/h -er'orman+e and small die size -- Memor0 5rote+tion 9nit ;M59< -- (nti-tam-erin/E+ounter'eitin/ measures -- 7a%a1ard su--ort -- Standard +o-ro+essor inter'a+e 'or in+or-oration o' +r0-to/ra-hi+ solutions. S1"66 - Small s0nthesiza3le I5: -- 32K /ates - " mm# area -- 66 M:zJ on 6.#2 mm @#.2 V -- 5o&er: 6.7 m@EM:z

.i/ure %'- ARM's S1%&& 1ore

,he ()M Se+ur1ore 'amil0 -ro%ides uniBue 3#-3it )IS1-3ased solutions 'or smart +ard de%elo-ment needs= o''erin/ s0stem desi/ners -ri%ile/ed a++ess to ()M -ro+essor +ores to +reate 'ast and se+ure e-+ommer+e solutions. ,he 'le4i3le Memor0 5rote+tion 9nit &as s-e+i'i+all0 desi/ned to ensure se+urit0 o' o-eratin/ s0stem and a--li+ation data. ,his ena3les 'uture /enerations o' smart +ard solutions ha%in/ multi-le a--li+ations runnin/ on a sin/le +ard. S-e+ial 'eatures in the +ore ha%e 3een desi/ned to hel- o3s+ure -ro+essor a+ti%it0 and hide a--li+ation -ro/ram si/natures= makin/ Se+ur1ore a+ti%it0 di''i+ult to dete+t and o3ser%e. ,he S1"66 runs all e4istin/ ()M 7a%a1ard so't&are im-lementations. Future Se+ur1ore -ro+essors &ill in+lude ()M*s 7azelle te+hnolo/0 'or dire+t e4e+ution o' 7a%a 30te +odes to ena3le hi/h-er'orman+e lo&--o&er 7a%a1ard a--li+ations. ,he ad%anta/es o%er a -urel0 so't&are-emulated 7a%a1ard %irtual ma+hine are +lear: si/ni'i+ant redu+tion in e4e+ution time= im-ro%ed res-onsi%eness= and si/ni'i+antl0 lo&er -o&er +onsum-tion. ,he Se+ur1ore 'amil0 o' -ro+essors also in+ludes a standard +o-ro+essor inter'a+e 'or sim-le in+or-oration o' +r0-to/ra-hi+ +o-ro+essors. ( +o-ro+essor +an 3e desi/ned 'or a %er0 s-e+i'i+ -ur-ose and +an +ontain as man0 re/isters and data -aths as needed to im-lement the s-e+i'i+ 'un+tions. ,o -ro%ide one solution= ()M has inte/rated into the S1"66 +ore a +r0-to/ra-hi+ a++elerator= the Mont/omer0 Multi-lier En/ine ;MME<. ,his en/ine is o-timized 'or )S( +al+ulations= -ro%idin/ 'i%e times the -er'orman+e o' so't&are solutions &ithout an0 restri+tions on ke0 len/th. ,he Se+ur1ore 'amil0 o''ers all the 3ene'its o' ()M*s industr0 leadin/ hi/h--er'orman+e= lo&--o&er ar+hite+ture= &ith si/ni'i+ant desi/n di''eren+es that make the ()M a--roa+h ideal 'or se+ure a--li+ations.

.3 1omparison of the ARM#T9MI with the ARM$T9MI families

.i/ure %*- Pipeline 1omparison ,o in+rease -er'orman+e= the -i-eline o' the ()M8,!MI +ore &as re-en/ineered 'rom the threesta/e s0stem used 30 the ()M7,!MI 'amil0 to 'i%e sta/es. $-erations -re%iousl0 -er'ormed in the e4e+ute sta/e o' ()M7 are s-read a+ross 'our sta/es in the ()M8 -i-eline: de+ode= e4e+ute= memor0= and &rite. ,he reor/anization and remo%al o' these +riti+al -aths resulted in a mu+h hi/her +lo+k 'reBuen+0. (nother -er'orman+e im-ro%ement is the redu+ed +0+les -er instru+tion ratin/ o' the -ro+essor. ,his is due to im-ro%ed load and store instru+tion +0+le +ounts. Sin/le load and store instru+tions are no& sin/le-+0+le o-erations. ,his is an enhan+ement o%er the ()M7 o-eration= &hi+h used the e4e+ute sta/e three times: 'irst= to +al+ulate the addressG se+ond= to a++ess the memor0 and +a+heG and third= to &rite the data to the re/ister 3ank. $n ()M8= ea+h ste- has a se-arate -i-eline sta/e reBuirin/ onl0 one +0+le= a%oidin/ -i-eline stalls.

.i/ure %#- Applications usin/ the ARM .amil, 1ores ,he ()M7,!MI 'amil0 is -o-ular &ith a--li+ations &here small die size= hi/h -er'orman+e= and lo& -o&er +onsum-tion hel- redu+e s0stem +osts= es-e+iall0 &hen the s0stem does not reBuire +a+he. (--li+ations in+lude +ellular -hones= M53 -la0ers= and mass stora/e. ,he ()M8,!MI 'amil0 are used 'or hi/h -er'orman+e a--li+ations that -re%iousl0 +ould not 3e im-lemented at the same +ost. ,his 'amil0 o' +ores &as de%elo-ed &ith t&i+e the -er'orman+e o' the ()M7,!MI and &ithout +han/es to the ar+hite+ture. It is ideall0 suited 'or the ne4t /eneration o' +ell -hones= -ersonal di/ital assistants= multi-'un+tion -eri-herals and 'ast -rinters= and set-to- 3o4 a--li+ations.

... ()M8,!MI 5ro+essor 1ore

()M 3#-3it and ,hum3 "6-3it instru+tions ;%., IS(<. Ver0 hi/h +ode +om-ati3ilit0 &ith ()M7,!MI: -- $nl0 +han/e is sim-li'ied data-a3ort handler 5orta3le to 6.#2= 6."8 Im 1M$S and 3elo&. :ar%ard 2-sta/e -i-eline im-lementation: -- :i/her -er'orman+e 'rom redu+ed +0+le -er instru+tion ;".2< 1o-ro+essor inter'a+e 'or on-+hi- +o-ro+essors: -- (llo&s 'loatin/ -oint= !S5= /ra-hi+s a++elerators. Em3eddedI1E de3u/ +a-a3ilit0 &ith e4tensions: -- :ard&are sin/le ste-- Creak-oint on e4+e-tion. .i/ure %6- ARM$T9MI 1ore

,he :ar%ard 3us ar+hite+ture +reates se-arate instru+tion and data memor0 inter'a+es= ena3lin/ simultaneous a++ess to instru+tions and data. ,he ()M8,!MI re-resents a ne& 'amil0 o' 159 te+hnolo/0. ,he enhan+ements made to this +ore 'amil0 dou3les the -er'orman+e o' the ()M7,!MI 'amil0. ...." ()M8.6, Ma+ro+ell 5ro+essor 'or real-time em3edded a--li+ations: -- ()M8,!MI 1ore ;%., IS(< -- . KC instru+tion and data +a+he &ith lo+k-do&n -- 5rote+tion unit 'or ),$S -- 1ode +om-ati3le 'rom ()M7 ,hum3 159s -- :ard Ma+ro I5: -- ..# mm# on 6."8 Im -- 9- to #66 M:z ;&orst +ase< on ,SM1 standard 6."8 Im -- 5o&er: 6.72 m@EM:z

.i/ure %$- ARM$ &T Macrocell 1ore ,he ()M8.6, re-resents the 'irst sam-le o' a +a+he-ena3led ()M8,!MI +ore. ,his +ore +ontains . KC ea+h o' instru+tion and data +a+he= &ith an M59 'or use 30 real-time o-eratin/ s0stems. ,his s0stem makes the 8.6, an ideal 159 'or em3edded +ontrol a--li+ations= su+h as &ireless net&orkin/ de%i+es= -rinters= or automoti%e +ontrol de%i+es. ,he -rote+tion units allo& de'inition o' ei/ht re/ions o' memor0= ea+h &ith inde-endent +a+he= &rite 3u''er ena3le= and a++ess -ermissions. ,he -rote+tion unit is +on'i/ured usin/ on-+hi- re/isters= &hi+h -ro%ides a sim-le -ro/rammer*s model. ,his eliminates the need 'or -a/e-ma--in/ ta3les stored in memor0.

....# ()M*s 8.6, 1ore Stru+ture ,he +ore -ro+essor is a3out one-third o' the die size. @hen other +om-onents are in+or-orated - the s0stem +ontrol +o-ro+essor= 3us +ontrol= memor0 -rote+tion unit= and the +a+he itsel' - the inte/er unit 3e+omes insi/ni'i+ant in total die area. ,his +ore has . KC +a+hes= the smallest amount o' +a+he used in the entire -rodu+t 'amil0. $ne +an %isualize ho& small this inte/er unit and +a+he lo/i+ 3e+omes &hen inte/rated &ith s0nthesized -eri-herals and the other 'eatures that +om-lete the s0stem-on-+hi- ;So1< desi/n. .i/ure 0&- ARM's $ &T core structure ....3 ()M8#6, Ma+ro+ell

1a+hed -ro+essor 'or -lat'orm $S a--li+ations: -- "6 KC instru+tion and data +a+he -- ()M%. MM9 'or 5alm $S= S0m3ian $S= Ainu4= and @indo&s 1E -- 1ode +om-ati3le 'rom ()M7 ,hum3 159s -- :ard Ma+ro I5: -- "".8 mm# on 6."8 Im -- 9- to #66 M:z ;&orst +ase< on ,SM1 standard 6."8 Im -- 5o&er: 6.8 m@EM:z .i/ure 0%- ARM$0&T Macrocell 1ore

,he ()M8#6, &as +reated to address the needs o' more +om-le4 s0stems usin/ a -lat'orm o-eratin/ s0stem= su+h as @indo&s 1E or S0m3ian $S. ,his +ore re-la+es the M59 o' the 8.6, &ith a 'ull memor0 mana/ement unit= and in+reases the instru+tion and data +a+he sizes to "6 KC 'or ea+h. ,he -er'orman+e= MM9= and +a+he o' this +ore make it ideal 'or 5ersonal !i/ital (ssistants= smart-hones= and set-to- 3o4 a--li+ations. ..... ()M8##, 1a+hed -ro+essor 'or 5lat'orm $S a--li+ations:

8 KC instru+tion and data +a+he ()M%. MM9 'or: 5alm $S= S0m3ian $S= Ainu4= and @indo&s 1E 1ode +om-ati3le 'rom ()M7 ,hum3 159s :ard Ma+ro I5: -- 8." mm# on 6."8 Im 9- to #66 M:z ;&orst +ase< on ,SM1 standard 6."8 Im 5o&er: 6.8 m@EM:z .i/ure 00- ARM$00T 1ore

,he ()M8##, +ore &as +reated &ith hal' the amount o' instru+tion and data +a+hes o' the 8#6,= resultin/ in smaller sili+on o%erhead. $ther than this sim-le di''eren+e= the t&o +ores are 'undamentall0 identi+al.

....2 ()M8#6, and ()M8##, MM9

,&o ,ACs: -- 6.-entr0 instru+tion ,AC -- 6.-entr0 data ,AC ,&o-le%el -a/e ta3les ;stored in memor0< :ard&are -a/e-ta3le &alkin/ 10+li+ re-la+ement Ao+kdo&n 'eatures: -- Ao+k instru+tions or data into +a+he 'or +riti+al real-time +ode

Coth the 8#6, and 8##, +ore utilize an MM9 &ith the same 'eatures. ,here are t&o= 6.-entr0 translation look-aside 3u''ers 'or instru+tion and data= t&o-le%el -a/e ta3les= hard&are -a/e-ta3le &alkin/= and su--ort 'or random or round ro3in re-la+ement. Ao+kdo&n 'eatures are also in+luded to se+ure +riti+al real-time +ode. ,his +a+he ar+hite+ture results in t&o solutions that are sim-ler to -ro/ram and minimize -o&er= area= and reBuired memor0.

....6 ()M8E Famil0

.i/ure 03- ARM's $E 1ore .amil, ,he ()M8E 'amil0 is +urrentl0 +om-rised o' 'our di''erent units. ,he 3ase ()M8E inte/er -ro+essor o''ers a hi/h -er'orman+e and lo& /ate +ount s0nthesized solution in its most 3asi+ 'orm. ,he other units o''er the true +a-a3ilities o' the +ore &hen +ou-led &ith S)(M= +a+he= %e+tor 'loatin/ -oint a++eleration= and the 7azelle 7a%a e4tensions. (s a suite o' s0nthesiza3le solutions= the 'inal /ate +ount and -o&er +onsum-tion statisti+s o' these +ores de-ends on the im-lementation and the -ro+ess te+hnolo/0 used.

....6." ()M8E 1ore (r+hite+ture

3#-3it loadEstore )IS1 ar+hite+ture E''i+ient 2-sta/e -i-eline ()M and,hum3 instru+tion sets 37 4 3#-3it re/isters 3#-3it (A9 and 3arrel shi'ter Enhan+ed 3#-3it M(1 3lo+k E,M8 inter'a+e (MC( (:C inter'a+e 1o-ro+essor inter'a+e S0nthesiza3le or so't I5

.i/ure 0 - ARM$E Architecture (s mentioned hard ma+ro+ells al&a0s ha%e 3een the ultimate ans&er 'or o-timized -er'orman+e and die size in an0 /i%en -ro+essor desi/n. Cut ne&er s0nthesized desi/n 'lo&s are -ushin/ the en%elo-e 'or So1 a--li+ations. ,he ()M8E 'amil0 &as 3uilt u-on the standard set 30 the ()M8,!MI 'amil0= 3ut it also -ro%ides 'reedom 'or de'inin/ the +a+he and ti/htl0 +ou-led S)(M +on'i/urations used 30 the +ore. It &as also the 'irst 'amil0 o' 159s desi/ned to the (:C 3us o' the (MC( #.6 s-e+i'i+ation. (nother ke0 te+hnolo/i+al enhan+ement to this 'amil0 o' 159s in+ludes !S5 e4tensions 'or true realtime s0stems. ,his im-ro%ement to the ar+hite+ture introdu+es additional multi-l0 and saturated math instru+tions 'or use 30 +om-le4 !S5 al/orithms. ,his 'amil0 is also 'ull0 +ode +om-ati3le &ith ()M%., ar+hite+ture +ores. Aastl0= to enhan+e the de3u/ +a-a3ilities alread0 +ommon in ()M 159s= the Em3edded ,ra+e Ma+ro+ell inter'a+e &as added. ,his inter'a+e ena3les real-time de3u//in/ o' +om-le4 real-time s0stems. ....6.# ()M866E-S

Solution 'or hard real-time a--li+ations: ()M8E +ore ;%2,E IS(<. I and ! ,1M memor0 inter'a+es &ith *&ait* si/nal Sele+ta3le size Instru+tion and !ata ,1M ;6 KC - 6. MC< (MC( (:C 3us inter'a+e 5ro%ides an Do''-the-shel'D standard ()M8E solution E,M8 inter'a+e 'or real-time tra+e &ith E,M8 "26 M:zJ on ,SM1 6."8 Im .i/ure 0'- ARM$**E)S 1ore

,he ()M866E-S +ore &as desi/ned &ith hard real-time a--li+ations as the -rimar0 o3?e+ti%e. (n e4am-le is ser%o-motor +ontrol in hard disk dri%es. ,he ke0 'eature o' this 159 o%er the 3ase ()M8E-S is the ti/htl0 +ou-led memor0 inter'a+e that allo&s sele+ta3le S)(M sizes o' u- to 6. MC.

....6.3 ()M8.6E-S

1a+hed -ro+essor 'or em3edded real-time a--li+ations: M59 to su--ort ),$S: like II,)$N and V4@orks Sele+ta3le size instru+tion and data +a+hes and ,1Ms:;6 KC= . KC= 8 KC ... " MC< Instru+tion and data ,1M inter'a+es. "26 M:zJ on ,SM1 6."8 Im

Fi/ure 0*- ARM$ *E)S 1ore ,he ()M8.6E-S +ore takes the de%elo-ments made 30 the 866E-S and adds sele+ta3le instru+tion and data +a+hes. Sin+e the memor0 -rote+tion unit is inte/rated &ith +a+he= this -ro+essor is an e4+ellent hi/h -er'orman+e solution 'or em3edded real-time a--li+ations= su+h as en/ine mana/ement s0stems in automo3iles and net&ork a--lian+es. ....6.. ()M8.6E-S 1a+hes

1a+he is .-&a0 set asso+iati%e: 1an 3e 3uilt &ith +om-iled (SI1 )(M. Sizes o' 6 KC= . KC= 8 KC L " MC su--orted: I and ! +a+he sizes are inde-endentl0 sele+ta3le. 1a+he lo+k-do&n on -er-set 3asis: ranularit0 is a Buarter o' the +a+he size. So't&are sele+ta3le re-la+ement al/orithm: Su--orts -seudo-random and round-ro3in @rite throu/h and &rite 3a+k sE& sele+ta3le Aine len/th 'i4ed at 8 &ords

,he +a+he memor0 3lo+ks o' this +ore are sele+ta3le u- to " MC. ,he +a+he is .-&a0 set asso+iati%e and sele+ta3le u- to " MC. It also 'eatures lo+k-do&n su--ort on a -er-set 3asis= random and round ro3in re-la+ement su--ort= so't&are sele+ta3le o-tions 'or &rite throu/h and &rite 3a+k= and ei/ht&ord +a+he lines.

....7 ()M8E7-S 1ore (r+hite+ture

3#-3it loadEstore )IS1 ar+hite+ture E''i+ient 2-sta/e -i-eline: Fet+h !e+ode E4e+ute Memor0 @rite3a+k ()M= ,hum3 and 7a%a instru+tion sets 3" 4 3#-3it re/isters 3#-3it (A9 and 3arrel shi'ter Enhan+ed 3#-3it M(1 3lo+k E,M8 inter'a+e 1o-ro+essor inter'a+e .i/ure 0#- ARM$E:)S 1ore Architecture

,his 'amil0 o' s0nthesiza3le 159s soon &ill in+lude an additional enhan+ement to the ar+hite+ture: 7azelle 7a%a e4tensions. ,he 7azelle te+hnolo/0 de%elo-ed 'or this ne& ran/e o' +ores &ill in man0 &a0s a+t like the ,hum3 "6-3it e4tension. (n additional state o' the -ro+essor is added to su--ort the e4e+ution o' 7a%a instru+tions= -ro%idin/ a tremendous -er'orman+e im-ro%ement o%er +urrent solutions. ,his ran/e o' +ores &ill ha%e all the +hara+teristi+s o' the other ()M8E +ores and &ill 3e +ode+om-ati3le &ith ()M%., ar+hite+ture im-lementations. It in+or-orates a se-arate instru+tion and data (MC( (:C 3us inter'a+e= as &ell an Em3edded ,ra+e Ma+ro+ell-8 inter'a+e. ....7." ()M8#6E7-S

7azelle enhan+ed +a+hed -ro+essor 'or $S-3ased -lat'orm a--li+ations: MM9 to su--ort: S0m3ian $S= Ainu4= 5alm $S= and @indo&s 1E Sele+ta3le size instru+tion and data +a+hes - . K= 8 K= "6 KM"#8 K ,i/htl0 +ou-led memories su--orted 6 K= . K= 8 KM"MC Instru+tion and data ,1M inter'a+es &ith &ait state su--ort Se-arate instru+tion and data (:C 3uses E,M8 inter'a+e 'or real-time tra+e &ith the E,M8 ma+ro+ell "86 M:zJ on ,SM1 6."8 Im

.i/ure 06- ARM$0*E:)S

,he ()M8#6E7-S +ore= &ith 'ull MM9 su--ort and sele+ta3le ti/htl0 +ou-led memor0 and +a+he sizes= introdu+es a ne& /eneration o' Internet-ena3led de%i+es. For e4am-le= set-to--3o4es and &ireless +ommuni+ations -rodu+ts 3ene'it 'rom this sin/le -ro+essor solution. ,his -ro+essor +an 3e +om-ared to the ()M8#6, or 8##, +ores in its 3ase 'un+tionalit0 and -er'orman+e. No&= &ith the added 7azelle enhan+ements= 7a%a 'un+tions +an 3e -er'ormed &ithout the need 'or +om-li+ated +o-ro+essors or slo& so't&are im-lementations.

..2 ()M"6E (r+hite+ture Enhan+ements ()M"6E im-lements: :ar%ard 6-sta/e -i-eline Su--orts %2,E instru+tion set Em3eddedI1E ),II de3u/ lo/i+ Full0 +om-ati3le &ith %., ar+hite+ture 386-766 MI5S inte/er -er'orman+e 3ased on !hr0stone #." Cran+h -redi+tion: Eliminates 76H o' 3ran+hes on t0-i+al +ode seBuen+es Se-arate loadEstore unit: 6.-3it -ath to re/ister 3ank - load t&o re/isters simultaneousl0 :it-under-miss +a+hes: Si/ni'i+antl0 redu+es -i-e-line stalls @rite 3u''er: :olds u- to 8 dou3le-&ords ;"6 re/ister %alues< Ne& ener/0 sa%in/ -o&er do&n modes (nti+i-atin/ the market*s needs 'or multimedia di/ital +onsumer de%i+es= ()M de%elo-ed the ()M"6 'amil0 o' ad%an+ed mi+ro-ro+essor +ores &ith 386-766 MI5S inte/er -er'orman+e. ,o a+hie%e this -er'orman+e= additional 'eatures &ere added. ,he -i-eline &as &idened to add an additional sta/e= and im-ro%ements &ere made to the Em3eddedI1E lo/i+ to -ro%ide su--ort 'or realtime de3u/. (ll the &hile= +om-ati3ilit0 &as maintained &ith ()M%2,E and %., 'or ease o' +ode mi/ration. 5er'orman+e enhan+ements in+lude the introdu+tion o' 3ran+h -redi+tion= hit-under-miss su--ort in the MM9 and +a+he ar+hite+ture= an im-ro%ed &rite 3u''er that holds u- to ei/ht dou3le-&ords= and a se-arate load and store unit. ,hese 'eatures im-ro%e +ode -er'orman+e 30 lo&erin/ the a%era/e num3er o' +0+les -er instru+tion o' the -ro+essor= and also hel- &hen +ode is hea%il0 de-endent on +a+he o-erations. (s an added enhan+ement= the ar+hite+ture= +ir+uits= la0out= and so't&are +ontrolled -o&er-do&n modes ha%e 3een de%elo-ed s-e+i'i+all0 to a+hie%e lo&--o&er o-eration on hi/h--er'orman+e -ro+esses. ,hese enhan+ed 'eatures ha%e 3een o-timized to take ad%anta/e o' +lo+k /atin/ and d0nami+ -o&er redu+tion. ..2." :i/h 5er'orman+e Features

6.-3it a++esses to on-+hi- I and ! +a+hes: Fet+h t&o instru+tionsE+0+le AoadEstore t&o re/istersE+0+le ;A!MES,M< !ual 6.-3it 'ast (:C 3us: Se-arate 3uses 'or instru+tion and data N" 30teEse+ 3and&idth @ #66 M:z ;ea+h< S-lit transa+tion e4tensions 6.-3it +o-ro+essor inter'a+e: AoadEstore dou3le--re+ision o-erands in one +0+le 3#-3it inte/er data -ath sa%es area and -o&er

,he ()M"6E is also the 'irst 'amil0 o' -ro+essors desi/ned &ith a 6.-3it data 3us. ,his 'eature +om3ines the 'ru/al -o&er and die size +hara+teristi+s o' a 3#-3it 159 &ith the 3and&idth reBuirements o' hi/h -er'orman+e s0stems. ,he 6.-3it +o-ro+essor inter'a+e also allo&s 'or in+reased -er'orman+e o' 'loatin/ -oint o-erations &hen +om3ined &ith the Ve+tor Floatin/ 5oint-"6 +o-ro+essor.

..2.# ()M"6#6E and ()M"6##E

:i/hest -er'orman+e ()M -ro+essor +ores: ".3 MI5SEM:z ".24 ()M8 -er'orman+e Su--ort 'or :i/h 5er'orman+e IEEE 72. Floatin/ 5oint: 666-"#66 MFA$5S 366M:z ;&orst +ase< on ,SM1 6."2 Im Ao& 5o&er: 6.7 m@Emi-s ;6."2 Im< ()M"6#6E: 3#K I and ! +a+he "7.2 mm# ()M"6##E: "6K I and ! +a+he "# mm# )oadma- to 7azelle enhan+ed +ores .i/ure 0$- ARM%&0&E 1ore

,he ()M"6#6E and ()M"6##E -ro+essor +ores o''er the hi/hest -er'orman+e -er unit o' -o&er o' an0 3#-3it -ro+essor runnin/ a3o%e #66 M:z. @ith an un-re+edented 6.7 m@EMI5S -o&er +onsum-tion ratio= &orst +ase on 6."2 Im -ro+ess te+hnolo/0= these -ro+essors o''ers ideal solutions 'or hi/h end -lat'orm a--li+ations. E4am-les in+lude M5E . %ideo-hones= smart-hones= and @e3 -ads. Memor0 Mana/ement and +a+hes are +om-ara3le to the ()M8#6,= ()M8##, and ()M7#6, -rodu+ts - ensurin/ +ode -orta3ilit0 and -rote+tion 'or e4istin/ so't&are in%estments. Future im-lementation in this 'amil0 &ill also inte/rate the 7azelle 7a%a enhan+ements esta3lished 30 the ()M8E7-S 'amil0. ..6 Ve+tor Floatin/ 5oint ;VF5"6<

:i/h--er'orman+e IEEE 72. 'loatin/ -oint: Sin/le and dou3le -re+ision Ve+tor o-erations ;u- to 8 %alues -er %e+tor< ,hirt0-t&o 3#-3it ;S5< re/isters ;usa3le as si4teen !5 re/isters< Sin/le +0+le FM(1 throu/h-ut ;sin/le -re+ision - dou3le -re+ision FM(1 in # +0+les< "6-"664 -er'orman+e in+rease o%er so't&are emulation $-tional +o-ro+essor: ".6 mm# in 6."2 Lm ,ar/et: 5rinters= ima/in/= /ra-hi+s= em3edded +ontrol .i/ure 3&- ARM's ;ector .loatin/ Point

Man0 real-time +ontrol a--li+ations in the industrial and automoti%e 'ields 3ene'it 'rom the d0nami+ ran/e and -re+ision o' 'loatin/--oint o''ered 30 the ()M VF5"6. (utomoti%e -o&er train= anti-lo+k 3rakin/= tra+tion +ontrol= and a+ti%e sus-ension s0stems are e4am-les o' mission-+riti+al a--li+ations &here -re+ision and -redi+ta3ilit0 are essential reBuirements. In+or-oratin/ the ()M VF5"6 into a So1 desi/n +an redu+e de%elo-ment time and -ro%ide relia3le -er'orman+e. ,he %e+tor -ro+essin/ +a-a3ilit0 o' the ()M VF5"6 also o''ers in+reased -er'orman+e 'or ima/in/ a--li+ations= su+h as s+alin/= trans'orms= and 'ont /eneration used in -rintin/= 3! trans'orms= FF,= and /ra-hi+ 'ilterin/.

..7 Famil0 Summar0

.i/ure 3&- .amil, Summar, ,his ta3le +om-ares %arious +hara+teristi+s o' the ()M7,!MI= the ()M8,!MI= the ()M8E-S= and the ()M"6E inte/er units. (lthou/h these +ores &ill not 3e ne+essaril0 im-lemented as inte/er units= es-e+iall0 in the +ase o' the ()M"6E= it is use'ul to illustrate the 'eatures that make u- ea+h -rodu+t 'amil0. (s stated earlier= the /oal o' de%elo-in/ the ()M8 &as to dou3le the -er'orman+e o' the ()M7 &hile maintainin/ ar+hite+tural +om-ati3ilit0. ,his &as a+hie%ed 30 reor/anizin/ and &idenin/ the -i-eline and mi/ratin/ to a :ar%ard 3us ar+hite+ture. (lthou/h these +han/es did result in an in+rease in die area= the ()M8,!MI is an e4tremel0 small +ore &ith rou/hl0 "#6=666 transistors in all. ,his -hiloso-h0 +ontinued &ith the de%elo-ment o' the ()M"6E 'amil0. ,he -er'orman+e le%el o' this 'amil0 reBuires the use o' +a+hes to meet the needs o' mer/in/ a--li+ations. 5aired &ith the %e+tor 'loatin/ -oint +o-ro+essor= the result is a +om-rehensi%e solution 'or hi/h-end So1 im-lementations ne%er 3e'ore -ossi3le at this m@EMI5S ratio or sili+on o%erhead.

'. Some words about the ARM's AM(A architecture ) An open bus standard ,he OAd%an+ed Mi+ro-+ontroller (us Ar+hite+tureP on-+hi- 3us is 'reel0 a%aila3le 'rom ()M and o''ers an esta3lished= o-en s-e+i'i+ation that ser%es as a 'rame&ork 'or So1 desi/ns.

Cene'its o' a S0stem-on-1hi- ;So1< solution Ao& -o&er +onsum-tion Small sili+on area Ao& -rodu+tion +ost 'or lar/e Buantities

E4am-les in+lude (MC(: E5>("6 ;1on'i/ura3le So1< E57#68 ;M53< ()M7"66 ;5!(<

.i/ure 3&- 6&0.%% 2ireless <A3 ,he -ur-ose o' (MC( is to o''er -re-3uilt= tested= and -ro%en +om-onents 'or desi/ners to le%era/e their hard-earned kno&led/e into 'uture desi/ns. ,his method ena3les test methodolo/0 to 3e rea--lied &ith /reat +on'iden+e. Sin+e the release o' the (MC( s-e+i'i+ation= ()M has de%elo-ed a suite o' ena3lers to Bui+kl0 orient en/ineers on the desi/n-in o' this standard 3us -roto+ol= the (MC( !esi/n Kit. ,his desi/n kit is a li+ensa3le -rodu+t that ena3les So1 desi/ners to 3e+ome 'amiliar &ith the (MC( -roto+ol. ()M also has de%elo-ed a suite o' s0stem -eri-heral +om-onents +alled 5rime1ells. ,hese are -ro%en (MC(-+om-liant modules that +an 3e used Do''-the-shel'D 'or inte/ration in So1 desi/ns.

.i/ure 3%- ARM's AM(A architecture ,he desi/n o' the (MC( 3us s-e+i'i+ation is 'o+used on lo& -o&er +onsum-tion and hi/h -er'orman+e. ( t0-i+al (MC(-3ased So1 +onsists o' an ad%an+ed hi/h--er'orman+e s0stem 3us= or (:C= and an ad%an+ed lo& -o&er -eri-heral 3us= or (5C. Fi/ure 3" illustrates a sim-le im-lementation o' the (MC( 3us s+heme in a real-&orld a--li+ation.

$n the -er'orman+e +riti+al side o' the 3us is the ()M +ore= Memor0 1ontroller= ,est Inter'a+e 1ontroller ;,I1<= and the A1! 1ontroller. $n the lo& -o&er side o' the 3us is the Smart 1ard inter'a+e= audio +ode+= 9(),= and s0n+hronous serial -ort. ,his is an e4+ellent e4am-le o' ho& the (:C and (5C 3uses &ork in +on?un+tion to -ro%ide a +om-lete s0stem solution.

,he (MC( test methodolo/0 -ro%ides a me+hanism to /i%e an e4ternal tester a++ess to the on-+hi(MC( 3us. ,his ena3les the tester to take +ontrol o' the 3us and +he+k ea+h +om-onent se-aratel0.

*. +e,words(:C: ()M: (5C: (SI1: 15S): !S5: I5: A): MM9: M59: $EM: 51: )ISK: ),!: ),$S: ),,: So1: S5: S5S): ,(5: V1>: VSI(: (d%an+ed :i+h--er'orman+e Cus (d%an+ed )isk Mashines (d%an+ed 5eri-heral Cus (--li+ation S-e+i'i+ Inte/rated 1ir+uits 1urent 5ro/ram Status )e/ister !i/ital Si/nal 5ro+essor Intelle+tual 5ro-ert0 Aink )e/ister Memor0 Mana/mant 9nit Memor0 5rote+tion 9nit $ri/inal EBui-ment Manu'u+tures 5ro/ram 1ounter )edu+ed Instru+tion Set 1om-utin/ )eal ,ime !e3u/ )eal-,ime $-eratin/ S0stems )eal ,ime ,ra+e S0stem-on-1hiSta+k 5oint Sta+k 5oint States )e/ister ,est (++ess 5ort Virtual 1om-onent E4+han/e Virtual So+ket Inter'a+e (llian+e

#. Resourceshtt-:EE&&&.arm.+om htt-:EE&&&.arm.+omEdo+umentation htt-:EE&&&.arm.+omEa3outarmEmultimedia.html htt-:EE&&&.arm.+omEsu--ortEtrainin/Et0-e.686.html htt-:EEte+honline#.te+honline.+omE htt-:EE&&&.te+honline.+omE+ommunit0EedQresour+e htt-:EE&&&.te+honline.+omE+ommunit0EedQresour+eE+ourseRMi+ro-ro+essors htt-:EE&&&.te+honline.+omE+ommunit0EedQresour+eE+ourseE"367"