1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Statement List (STL) For S7-300 and S7-400 Programming Simatic S7

Preface, Contents Product Overview Structure and Components of Instructions and Statements
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SIMATIC S7
Adressing
Statement List (STL) for S7-300 and S7-400 Programming

Reference manual
Accumulator Operations and Address Register Instructions Bit Logic Instructions Timer Instructions Counter Instructions Load and Transfer Instructions Integer Math Instructions
This reference manual is part of the documentation package with the order number 6ES7810-4CA04-8BR0
Floating-Point Math Instructions Comparison Instructions Conversion Instructions Word Logic Instructions Shift and Rotate Instructions Data Block Instructions Jump Instructions Program Control Instructions 10/98 C79000-G7076-C565 Release 01 Appendix Glossary, Index
Safety Guidelines
This manual contains notices which you should observe to ensure your own personal safety, as well as to protect the product and connected equipment. These notices are highlighted in the manual by a warning triangle and are marked as follows according to the level of danger:
Danger
indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken.
Warning
indicates that death, severe personal injury or substantial property damage can result if proper precautions are not taken.
Caution
indicates that minor personal injury or property damage can result if proper precautions are not taken.
Note
draws your attention to particularly important information on the product, handling the product, or to a particular part of the documentation.
Correct Usage
Note the following:
Warning
This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended.
Trademarks
SIMATICR, SIMATIC HMIR
and SIMATIC NETR are registered trademarks of SIEMENS AG.
Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.
Copyright E Siemens AG 1998 All rights reserved
Disclaimer of Liability
The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved.
Siemens AG Bereich Automatisierungs- und Antriebstechnik Geschaeftsgebiet Industrie-Automatisierungssysteme Postfach 4848, D-90327 Nuernberg
We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.
E Siemens AG 1998 Technical data subject to change. C79000-G7076-C565
Siemens Aktiengesellschaft
Statement List (STL) for S7-300/S7-400
Preface
Purpose
This manual is your guide to creating user programs in the Statement List programming language STL. The manual also includes a reference section that describes the syntax and functions of the language elements of STL.
Audience
This manual is intended for S7 programmers, operators, and maintenance/service personnel. A working knowledge of automation procedures is essential.
Scope of the Manual
This manual is valid for release 5.0 of the STEP 7 programming software package.
Compliance with Standards
STL corresponds to the Instruction List language defined in the International Electrotechnical Commissions standard IEC 1131-3, although there are substantial differences with regard to the operations. For further details, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.
Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
iii
Preface
Requirements
To use this Statement List manual effectively, you should already be familiar with the theory behind S7 programs which is documented in the online help for STEP 7. The language packages also use the STEP 7 standard software, so you should be familiar with handling this software and have read the accompanying documentation.
Documentation STEP 7 Basic Information with
Purpose
Order Number
S S S
Basic information for technical per- 6ES7810-4CA04-8BA0 Working with STEP 7 V5.0, Getting Started sonnel describing the methods of implementing control tasks with Manual STEP 7 and the S7-300/400 proProgramming with STEP 7 V5.0 grammable controllers. Configuring Hardware and Communication Connections, STEP 7 V5.0 Provides reference information and 6ES7810-4CA04-8BR0 describes the programming languages LAD, FBD and STL and standard and system functions extending the scope of the STEP 7 basic information.
S From S5 to S7, Converter Manual

STEP 7 Reference with
S Ladder Logic (LAD)/Function Block Diagram (FBD)/Statement List (STL) for S7-300/400 manuals
S Standard and System Functions for

S7-300/400
Online Helps Help on STEP 7
Purpose Basic information on programming and configuraing hardware with STEP 7 in the form of an online help.
Order Number Part of the STEP 7 Standard software.
Reference helps on STL/LAD/FBD Reference help on SFBs/SFCs Reference help on Organization Blocks
Context-sensitive reference informa- Part of the STEP 7 Stantion. dard software.
Accessing the Online Help
You can display the online help in the following ways:
S Context-sensitive help about the selected object with the menu command
Help > Context-Sensitive Help, with the F1 function key, or by clicking the question mark symbol in the toolbar.
S Help on STEP 7 via the menu command Help > Contents.

References References to other documentation are indicated by reference numbers in slashes /.../. Using these numbers, you can check the exact title in the References section at the end of the manual.
iv
Preface
SIMATIC Customer Support Online Services
The SIMATIC Customer Support team offers you substantial additional information about SIMATIC products via its online services:
S General current information can be obtained:

on the Internet under http://www.ad.siemens.de/simatic/html_00/simatic via the Fax-Polling number 08765-93 02 77 95 00
S Current product information leaflets and downloads which you may find
useful are available: on the Internet under http://www.ad.siemens.de/support/html_00/ via the Bulletin Board System (BBS) in Nuremberg (SIMATIC Customer Support Mailbox) under the number +49 (911) 895-7100. To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) with the following parameter settings: 8, N, 1, ANSI; or dial via ISDN (x.75, 64 Kbps).
Additional Assistance
If you have other questions, please contact the Siemens representative in your area. The addresses are listed, for example, in catalogs and in Compuserve (go autforum). Our SIMATIC Basic Hotline is also ready to help:
S in Nuremberg, Germany
Monday to Friday 07:00 to 17:00 (local time): telephone: +49 (911) 8957000 or E-mail: simatic.support@nbgm.siemens.de
S in Johnson City (TN), USA

Monday to Friday 08:00 to 17:00 (local time): telephone: +1 423 4612522 or E-mail: simatic.hotline@sea.siemens.com
S in Singapore
Monday to Friday 08:30 to 17:30 (local time): telephone: +65 7407000 or E-mail: simatic@singet.com.sg The SIMATIC Premium Hotline is available round the clock worldwide with the SIMATIC card (telephone: +49 (911) 895-7777).
Courses for SIMATIC Products
Siemens offers a number of training courses to introduce you to the SIMATIC S7 automation system. Please contact your regional training center or the central training center in Nuremberg, Germany for details: Telephone: +49 (911) 895-3154.
Preface
Questionnaires on the Manual and Online Help
To help us to provide the best possible documentation for you and future STEP 7 users, we need your support. If you have any comments or suggestions relating to this manual or the online help, please complete the questionnaire at the end of the manual and send it to the address shown. Please include your own personal rating of the documentation.
vi
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure and Components of Instructions and Statements . . . . . . . . . . . . . . . . 2.1 2.2 3 Structure of a Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning of the CPU Register in Statements . . . . . . . . . . . . . . . . . . . . . . . . . iii 1-1 2-1 2-2 2-10 3-1 3-2 3-2 3-3 3-6 3-7 3-11 4-1 4-2 4-3 4-6 4-7 5-1 5-2 5-6 5-10 5-14 5-16 5-20 5-21 5-24 5-26
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 3.5 3.6 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Area-Internal Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . Area-Crossing Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator Operations and Address Register Instructions . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ENT and LEAVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incrementing and Decrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +AR1 und +AR2: Adding a Constant to Address Register 1 or Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Boolean Bit Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Logic Instructions and Relay Coil Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluating Conditions Using And, Or, and Exclusive Or . . . . . . . . . . . . . . . Nesting Expressions and And before Or . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instructions for Transitional Contacts: FP, FN . . . . . . . . . . . . . . . . . . . . . . . . Output of Boolean Logic String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set and Reset Instructions: S and R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assign Instruction (=) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Negating, Setting, Clearing, and Saving the RLO . . . . . . . . . . . . . . . . . . . . .
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Contents
Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 6.2 6.3 6.4 6.5 6.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location of a Timer in Memory and Components of a Timer . . . . . . . . . . . Loading, Starting, Resetting, and Enabling a Timer . . . . . . . . . . . . . . . . . . . Timer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Locations and Ranges for Timer Instructions . . . . . . . . . . . . . . . . . Choosing the Right Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1 6-2 6-3 6-5 6-7 6-17 6-18 7-1 7-2 7-3 7-5 7-6 7-7 7-8 7-10 8-1 8-2 8-3 8-6 8-7 8-9 8-11 8-12 9-1 9-2 9-6 10-1 10-2 10-6 10-7 10-9
Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting, Resetting, and Enabling a Counter . . . . . . . . . . . . . . . . . . . . . . . . . . Couting Up and Counting Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading a Count Value as Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading a Count Value in Binary Coded Decimal Format . . . . . . . . . . . . . . Counter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Locations and Ranges for Counter Instructions . . . . . . . . . . . . . . .
Load and Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading and Transferring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Status Word or Transferring to the Status Word . . . . . . . . . . . Loading Times and Counts as Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading Times and Counts in Binary Coded Decimal Format . . . . . . . . . . Loading and Transferring between Address Registers . . . . . . . . . . . . . . . . Loading Data Block Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 9.2 Four-Function Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding an Integer to Accumulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Floating-Point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 10.2 10.3 10.4 10.5 10.6 10.7 Four-Function Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forming the Absolute Value of a Floating-Point Number . . . . . . . . . . . . . . . Extended Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forming the Square / Square Root of a Floating-Point Number . . . . . . . . .
Forming the Natural Logarithm of a Floating-Point Number . . . . . . . . . . . . 10-11 Forming the Exponential Value of a Floating-Point Number . . . . . . . . . . . . 10-12 Forming Trigonometric Functions on Angles Acting as Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
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Contents
11
Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 11.2 11.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparing Two Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparing Two Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1 11-2 11-3 11-5 12-1 12-2 12-8
12
Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 12.2 12.3 12.4 Converting Binary Coded Decimal Numbers and Integers . . . . . . . . . . . . . Converting 32-Bit Floating-Point Numbers to 32-Bit Integers . . . . . . . . . . .
Reversing the Order of Bytes within Accumulator 1 . . . . . . . . . . . . . . . . . . . 12-13 Forming Complements and Negating Floating-Point Numbers . . . . . . . . . 12-14 13-1 13-2 13-3 13-6 14-1 14-2 14-6 15-1 15-2 15-2 15-3 16-1 16-2 16-3 16-4 16-5 16-6 16-8 17-1 17-2 17-3 17-7
13
Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 13.2 13.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 14.2 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Data Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 15.2 15.3 Opening Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Swapping Data Block Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading Data Block Lengths and Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 16.2 16.3 16.4 16.5 16.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unconditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditional Jump Instructions Founded on Result of Logic Operation . . . Conditional Jump Instructions Founded on BR, OV, or OS Bits of the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditional Jump Instructions Based on Result in the CC 1 and CC 0 Bits of the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 17.2 17.3 17.4 17.5 17.6 Parameter Assignment when Calling FCs and FBs . . . . . . . . . . . . . . . . . . . Calling Functions and Function Blocks with CALL . . . . . . . . . . . . . . . . . . . . Calling Functions and Function Blocks with CC and UC . . . . . . . . . . . . . . .
Working with Master Control Relay Functions . . . . . . . . . . . . . . . . . . . . . . . . 17-10 Master Control Relay Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 Ending Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
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Contents
Alphabetical Listing of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 A.2 Listing with (German) SIMATIC and International Mnemonics . . . . . . . . . . Alphabetical Listing with International Names . . . . . . . . . . . . . . . . . . . . . . . .
A-1 A-2 A-12 B-1 B-2 B-3 B-7 B-10 B-12 B-14 C-1 D-1
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1 B.2 B.3 B.4 B.5 B.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter and Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C D
Source Files - Examples and Reserved Keywords . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary-1 Index-1
Product Overview
What is Statement List?
Statement List (STL) is a textual programming language that can be used to create the code section of logic blocks. Its syntax for statements is similar to assembler language and consists of instructions followed by addresses on which the instructions act.
The Programming Language STL
Of all the programming languages with which you can program S7 controllers, STL is the closest to the machine code MC7 of the S7 CPU. This means that by using it to program S7 controllers, you can optimize the run time and the use of memory. The programming language STL has all the necessary elements for creating a complete user program. It contains a comprehensive range of instructions. A total of over 130 different basic instructions and a wide range of addresses are available. Functions and function blocks allow you to structure your STL program clearly.
The Programming Package
The STL programming package is an integral part of the STEP 7 Standard Software. This means that following the installation of your STEP 7 software, all the editor functions, compiler functions and test/debug functions for STL are available to you. Using STL, you can create your own user program as follows:
S With the Incremental Editor. The input of the local data structure is made
easier with the help of table editors.
S With a source file in the Text Editor. Text input is made easier with the
help of block templates. There are three programming languages in the standard software, STL, FBD, and LAD. You can switch from one language to the other almost without restriction and choose the most suitable language for the particular block you are programming. If you write programs in LAD or FBD, you can always switch over to the STL representation. If you convert LAD programs into FBD programs and vice versa, program elements that cannot be represented in the destination language are displayed in STL.
1-1
1-2
Structure and Components of Instructions and Statements

Chapter Overview
Section 2.1 2.2 Description Structure of a Statement Meaning of the CPU Register in Statements
2
Page 2-2 2-10
2-1
2.1
Structure of a Statement
Components of a Statement
With reference to structure, an instruction statement belongs to either one of the following two basic groups (see also Figure 2-1):
S A statement made up of an instruction alone (for example, NOT, see

Section 5.9)
S A statement made up of an instruction and an address (see Tables 2-1

through 2-5, and Table 2-9)
Statement group 1 Instruction alone Figure 2-1
Statement group 2 Instruction + address
Basic Groups of Statements
Address of an Instruction
The address of an instruction indicates a constant or the location where the instruction finds a value (data object) on which to perform an operation. The address can have a symbolic name or an absolute designation. The address can point to any of the following items (see also Tables 2-1 through 2-9):
S A constant, the value of a timer or counter, or an ASCII character string

to be loaded into accumulator 1 (for example, L +27, see Table 2-1)
S A bit in the status word of the programmable logic controller (for

example, A UO, see Table 2-2)
S A symbolic name (for example, A Motor.On, see Table 2-3) S A data block and a location within the data block area (for example,
L DB4.DBD10, see Table 2-4)
S A function (FC), function block (FB), integrated system function (SFC),

or integrated system function block (SFB) and the number of the function or block (see Table 2-5)
S An address identifier and a location within the memory area that is

indicated by the address identifier (for example, A I 1.0, or A I [AR1,P#4.3], see Table 2-9) Tables 2-1 through 2-9 show various statements that each include an instruction with an address.
2-2
Constant Values
Table 2-1 shows how you can use a constant value as the address of an instruction.
Table 2-1 Addresses That Point to a Value or Character String Statement Instruction Address Constant L L +27 END Load the integer 27 into accumulator 1. Load the ASCII characters END into accumulator 1. D Description i i
Locations in the Status Word
The address of a statement list instruction can refer to one or more bits in the status word of the programmable logic controller (see Section 2.2). The instruction checks and reacts to the signal state of a single bit in the status word (for example, A BR) or interprets the bit combination in two of the bits (for example, A UO).
Table 2-2 Addresses That Refer to a Bit in the Status Word Statement Instruction Address Bit in the Status Word A A BR UO The 1 or 0 in bit 8 of the status word is included in a Boolean logic combination. The instruction interprets the bit combination that it finds in bits CC 1 and CC 0 of the status word to see if a certain condition has been fulfilled. For example, a combination of 1 and 1 indicates unordered, that is, one of the values in a floating-point operation was not a valid floating-point number. Description
2-3
Symbolic Name
Table 2-3 shows how you use a symbolic name as the address of an instruction. You can only use symbolic names in STL statements once you have declared them: shared symbolic names should be entered in the symbol table and local names in a block.
Table 2-3 Addresses That Point to a Symbolic Name Statement Instruction Address Symbol A Motor.On Perform an And logic operation on the bit whose symbolic name is Motor.On. In this case, the symbolic name Motor.On can only represent a bit in the data block (D) area of memory or element of a structure MOTOR . Load the byte, word, or double word value, whose symbolic name is SPEED, into accumulator 1 . D Description i i
SPEED
A Data Block and a Location within the Data Block
Table 2-4 shows how you use a data block and a location within the data block as the address of an instruction.
Table 2-4 Addresses That Point to a Data Block and a Location within the Data Block Statement Instruction Address Data Block and Location L A DB4.DBD10 DB10.DBX4.3 Load data double word DBD10 from data block DB4 into accumulator 1. Perform an And logic operation on data bit DBX4.3 from data block DB10. Description Descr pt on
2-4
FCs, FBs, SFCs, and SFBs
Table 2-5 shows how you use a function (FC), function block (FB), integrated system function (SFC), or integrated system function block (SFB) and the number of the function or block as the address of an instruction.
Table 2-5 Addresses That Point to a Function, Function Block, System Function, or System Function Block Statement Instruction Address FC, FB, SFC, SFB and Number CALL CALL FB10, DB10 SFC43 D Description i ti
Call function block FB10 with instance data block DB10. Call integrated system function SFC43.
Address Identifiers
Some addresses include an address identifier and a location within the memory area indicated by the address identifier. An address identifier can be one of the following three basic types (see Tables 2-6 through 2-8):
S An address identifier that indicates the memory area and the size of a data
object in that area as follows (see Table 2-6): The memory area in which an instruction finds a value (data object) on which to perform an operation (for example, I for the process image input area of memory) The size of the value (data object) on which the instruction is to perform its operation (for example, B for byte, W for word, and D for double word)
S An address identifier that indicates a memory area but no size of a data

object in that area (for example, an identifier that indicates the area T for timer, C for counter, or DB or DI for data block, plus the number of that timer, counter, or data block, see Table 2-7)
S An address identifier that indicates the size of a data object but no

memory area. The memory area is encoded in the memory location that follows the address identifier (see Table 2-8).
2-5
Table 2-6
Address Identifier That Indicates Memory Area and Size of Data Object Instruction Memory Area Address Identifier Size of Data Object (If no size is indicated, a bit is implied.)
0.0 B 10 [MD2] B [DID4] [AR1, P#4.3] D [AR2, P#53.0]
Type of Addressing
Memory Location
Direct Direct Memory indirect Memory indirect Area-internal register indirect Area-internal register indirect
A L A L A T
I I I I I L
Table 2-7
Address Identifier That Indicates Memory Area, but No Size of Data Object Instruction Address Identifier: Memory Area
DB T DB C
Type of Addressing
Number or Location of Number

5 7 [LW2] [MW44]
Direct Direct Memory indirect Memory Indirect
OPN SP OPN S
Table 2-8
Address Identifier That Indicates Size of Data Object, but No Memory Area Instruction Size of Data Object (If no size is indicated, a bit is implied.) Memory Location
Type of Addressing
Area-crossing register indirect Area-crossing register indirect
A L B
[AR1, P#4.3] [AR1, P#100.0]
Table 2-9
Addresses That Include Address Identifier and Location Statement
Instruction
Address Address Identifier Location in Memory Area or Register

1.0 [MD2] 1
D Description i ti
A A L
I I C
Perform an And logic operation on input bit 1.0. Perform an And logic operation on the input bit whose exact location is in memory double word MD2. Load the count value of counter 1 into accumulator 1.
2-6
Working with Word or Double Word as Data Object
If you are working with an instruction whose address identifier indicates a memory area of your programmable logic controller and a data object that is either a word or a double word in size (see Table 2-6), you need to be aware of the fact that the memory location is always referenced as a byte location. This byte location is the number of the most significant byte within the word or double word. For example, the address in the statement shown in Figure 2-2 references four successive bytes in memory area M, starting at byte 10 (MB10) and going through byte 13 (MB13).
Statement: L MD10 Address identifier Byte location
Figure 2-2
Example of Memory Location Referenced as Byte Location
Figure 2-3 illustrates data objects of the following sizes:
S Double word: memory double word MD10 S Word: memory words MW10, MW11, and MW13 S Byte: memory bytes MB10, MB11, MB12, and MB13
When you use absolute addresses that are a word or a double word in width, make sure that you do not create any byte assignments that overlap.
0j15 MW10 MB10 MSB 31 MW11 16j15 MD10 Referencing a Memory Location as a Byte Location MB11 MB12 MW12 MB13 LSB 0
15
Figure 2-3
Memory Areas and their Functions
Most addresses in STL refer to memory areas. The following table lists the memory areas and describes the function of each area.
2-7
Table 2-10 Name of Area

Process image input
Memory Areas and Their Functions Access to Area Function Funct on of Area
At the beginning of the scan cycle, the operating system reads the inputs from the process and records the values in this area. The program can use these values in its cyclic processing. During the scan cycle, the program calculates output values and places them in this area. At the end of the scan cycle, the operating system reads the calculated output values from this area and sends them to the process outputs. This area provides storage for interim results calculated in the program.
via Units of the Following Size:

Input bit Input byte Input word Input double word Output bit Output byte Output word Output double word Memory bit Memory byte Memory word Memory double word Peripheral input byte Peripheral input word Peripheral input double word Peripheral output byte Peripheral output word Peripheral output double word
Abbrev.
I IB IW ID Q QB QW QD M MB MW MD PIB PIW PID PQB PQW PQD T
Process image output
Bit memory
I/O: external input I/O: external output Timer
This area enables your program to have direct access to input and output modules (that is, peripheral inputs and outputs).
Timers are function elements of STL programming. This area provides storage for timer cells. In this area, clock timing accesses time cells to update them by decrementing the time value and timer instructions access time cells. Counters are function elements of STL programming. This area provides storage for counters. Counter instructions access them here. This area contains data that can be accessed from any block. If you need to have two different data blocks open at the same time, you can open one with the statement OPN DB and one with the statement OPN DI. In this way, the CPU can distinguish which of the two data blocks your program wants to access while both data blocks are open. While you can use the OPN DI statement to open any data block, the principal use of this statement is to open instance data blocks that are associated with function blocks (FBs) and system function blocks (SFBs). For more information on FBs, SFBs, and instance data blocks, see the STEP 7 Online Help. This area contains temporary data that is used within a logic block (OB, FB, or FC). These data are also called dynamic local data. They serve as an intermediate buffer. When the logic block is finished, these data are lost. The data are contained in the local data stack (L stack).
Timer (T)
Counter
Counter (C)
Data block
Data block opened with the statement OPN DB: Data bit Data byte Data word Data double word Data block opened with the statement OPN DI: Data bit Data byte Data word Data double word Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word DIX DIB DIW DID L LB LW LD DBX DBB DBW DBD
Local data
2-8
Table 2-11 lists the maximum address ranges for various memory areas. For the address range possible with your CPU, refer to the technical data of the CPU. For an explanation of the functions of the memory areas, see Table 2-10.
Table 2-11 Memory Areas and Their Address Ranges Access to Area Name of Area
Process image input
via Units of the Following Size:

Input bit Input byte Input word Input double word Output bit Output byte Output word Output double word Memory bit Memory byte Memory word Memory double Word Peripheral input byte Peripheral input word Peripheral input double word Peripheral output byte Peripheral output word Peripheral output double word Timer (T) Counter (C) Data block opened with the statement OPN DB: Data bit Data byte Data word Data double word Data block opened with the statement OPN DI: Data bit Data byte Data word Data double word
Abbrev.
I IB IW ID Q QB QW QD M MB MW MD PIB PIW PID PQB PQW PQD T C
M i Maximum Address Add Range R

0.0 to 65,535.7 0 to 65,535 0 to 65,534 0 to 65,532 0.0 to 65,535.7 0 to 65,535 0 to 65,534 0 to 65,532 0.0 to 255.7 0 to 255 0 to 254 0 to 252 0 to 65,535 0 to 65,534 0 to 65,532 0 to 65,535 0 to 65,534 0 to 65,532 0 to 255 0 to 255
Process image output
Bit memory
I/O: external input I/O: external output Timer Counter Data block
DBX DBB DBW DBD
0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532
DIX DIB DIW DID L LB LW LD
0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532 0.0 to 65,535.7 0 to 65,535 0 to 65, 534 0 to 65,532
Local data
Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word
2-9
2.2
Meaning of the CPU Register in Statements
Accumulators
The two 32-bit accumulators are general purpose registers that you use to process bytes, words, and double words. You can load constants or values from the memory as addresses into the accumulator and perform logic operations on them. You can also transfer the result of an operation from accumulator 1 to a memory location. Figure 2-4 identifies the areas of an accumulator. The stack mechanism for accumulator administration is as follows:
S A load instruction always acts on accumulator 1 and saves the old

contents to accumulator 2.
S A transfer instruction does not change the accumulators (with the

exception of instructions TAR1 and TAR2).
S The TAK instruction swaps the contents of accumulators 1 and 2.

For information on accumulator administration for math instructions, see Section 9.1.
31 High byte
24
23 Low byte
16
15 High byte
8 7 Low byte
High word Figure 2-4 Areas of an Accumulator
Accumulator (1 or 2)
Low word
Nesting Stack
The nesting stack is a storage area that is one byte wide. This storage area is used by the nesting instructions A(, O(, X(, AN(, ON(, XN(. These instructions save the current result of logic operation (RLO) to the nesting stack and start a new logic string. The nesting stack can accommodate seven entries. A nesting stack entry consists of the RLO, BR, and OR bits of the status word, and a function code to indicate which of the Boolean logic operations is to be used (A, AN, O, ON, X, or XN). The ) instruction closes a nesting expression by performing the following functions:
S Fetches an entry from the nesting stack S Restores the OR and BR bits S Defines the new RLO by logically combining the current RLO (that is,
the RLO from the expression nested in parentheses) with the RLO of the stack entry according to the function code (see Section 5.4)
2-10
Figure 2-5 shows the structure of an entry in the nesting stack. Below Figure 2-5 you can see an explanation of the bits in the nesting stack byte.
27 0
26 0
25 BR
24 RLO
23
22
21
20
OR Function code
Figure 2-5
Structure of an Entry in the Nesting Stack
The nesting stack byte contains the following bits (see Figure 2-5):
S Non-assigned bits (bits 7 and 6 with signal state 0) S The stored binary result (BR) S The stored result of logic operation (RLO) S The stored OR bit in the functions A( and AN(
Zero is stored in all other functions
S The function code (in bits 2, 1 and 0)

Function code With the help of the function code, the instruction ) defines the function which is to be used for the combination of the current RLO (that is the RLO from the expression nested in parentheses) with the RLO of the nesting stack entry. Table 2-12 shows the bit combinations of the function code for each function type:
Table 2-12 Function Codes of Nesting Stack Byte Function Code 2 0 0 0 0 1 1 Function Code 1 0 0 1 1 0 0 Function Code 0 0 1 0 1 0 1
Instruction A( AN( O( ON( X( XN(
2-11
Nesting Stack with Entries and Pointer The nesting stack and the nesting stack pointer must be stored either in the interrupt stack or they must be fetched from it, when the batches change. The number in the nesting stack pointer indicates the number of entries available in the nesting stack (see Figure 2-6).
15 Nesting stack entry 7 Nesting stack entry 5 Nesting stack entry 3 Nesting stack entry 1 7 Nesting stack entry 6 Nesting stack entry 4 Nesting stack entry 2 Nesting stack pointer Rising addresses 0
Figure 2-6
Structure of a Nesting Stack with Entries and Pointer
Status Word
The status word contains bits that you can reference in the address of bit logic and word logic instructions. Figure 2-7 shows the structure of the status word. The sections that follow the figure explain the significance of bits 0 through 8.
215... ...29 28
BR
27
26
25
OV
24
OS
23
OR
22
STA
21
RLO
20
FC
CC 1 CC 0
Figure 2-7
Structure of the Status Word
First Check
Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-8). The signal state of 0 in the FC bit indicates that, following this point in your program, the next logic instruction begins a new logic string. (The bar over the FC indicates that it is negated.) Each logic instruction checks the signal state of the FC bit as well as the signal state of the location it addresses. If the FC bit is 0, the instruction stores the result of the signal state check in the result of logic operation bit of the status word (RLO bit, see next section) and sets the FC bit to 1. This process is called a first check (see Figure 2-8 and Section 5.6). If the signal state of the FC bit is equal to 1, an instruction combines the result of its signal state check on the contact it addresses with the value stored in the previous RLO bit (see Figure 2-8). A string of logic instructions always ends with an output instruction (S, R, or =, see Sections 5.7 and 5.8), a jump instruction related to the result of logic operation (JC, see Section 16), or one of the nesting instructions A(, O(, X(, AN(, ON(, or XN( (see Section 5.4). Such an output, jump instruction, or nesting instruction resets the FC bit to 0 (see Figure 2-8).
2-12
Result of Logic Operation
Bit 1 of the status word is called the RLO bit (RLO stands for result of logic operation, see Figure 2-7). This bit stores the result of a bit logic instruction or math comparison. For example, the second instruction in a string of bit logic instructions checks the signal state of a contact and produces a result of 1 or 0. Then the instruction combines this result with the value stored in the RLO bit of the status word according to the principles of Boolean logic (see First Check above and Chapter 5). The result of this logic operation is stored in the RLO bit of the status word, replacing the former value in the RLO bit. Each subsequent instruction in the string performs a logic operation on two values: the result produced when the instruction checks the contact, and the current RLO. You can set the RLO to 1 unconditionally by using the SET instruction; you can reset the RLO to 0 unconditionally by using the CLR instruction. You can use a Boolean bit logic instruction on a first check to assign the state of the contents of a Boolean bit memory location to the RLO. You can use the RLO to trigger jump instructions.
Statement List Program
Signal State Result of Check of Input (I) or Output (Q)
RLO Bit
FC Bit 0
Explanation
FC bit = 0 indicates that next instruction begins logic string Result of first check is stored in RLO bit. FC bit is set to 1.
A I 1.0
AN I 1.1
Result of check is combined with previous RLO according to AND truth table. FC bit remains 1. RLO is assigned to output coil. FC bit is reset to 0.
= Q 4.0
Figure 2-8
Effect of Signal State of FC Bit on Logic Instructions
Status Bit
The status bit (STA bit) stores the value of a bit that is referenced. The status of a bit instruction that has read access to the memory (A, AN, O, ON, X, XN) is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that has write access to the memory (S, R, =) is the same as the value of the bit to which the instruction writes or, if no writing takes place, the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access the memory. Such instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.
2-13
OR Bit
The OR bit is needed if you use the O instruction to perform a logical AND before OR operation. An AND function may contain the following instructions: A, AN A(, AN(, ), and NOT. The OR bit shows these instructions that a previously executed AND function has supplied the value 1, thus forestalling the result of the logical OR operation. Any other bit-processing command resets the OR bit (see Section 5.4). The overflow bit (OV bit) indicates a fault. It is set by a math instruction or a floating-point comparison instruction after a fault occurs (overflow, illegal operation, illegal floating-point number). This bit is set according to the result of the next math instruction or comparison instruction. The stored overflow bit (OS bit) is set together with the OV bit when a fault occurs. Because the OS bit remains set after the fault has been eliminated, it stores the OV bit status and indicates whether or not a fault occurred in one of the previously executed instructions. The following commands reset the OS bit: JOS (jump after stored overflow), the block call commands, and the block end commands. The CC 1 and CC 0 bits (condition codes) provide information on the following results or bits:
Overflow Bit
Stored Overflow Bit
Condition Code 1 and Condition Code 0
S Result of a math operation S Result of a comparison S Result of a digital operation S Bits that have been shifted out by a shift or rotate command
Tables 2-13 through 2-18 list the significance of CC 1 and CC 0 after your program executes certain instructions.
Table 2-13 CC 1 0 0 1 CC 1 and CC 0 after Math Instructions, without Overflow CC 0 0 1 0 Explanation Result = 0 Result < 0 Result > 0
Table 2-14 CC 1 0 0 1 1
CC 1 and CC 0 after Integer Math Instructions, with Overflow CC 0 0 1 0 1 Explanation Negative range overflow in +I and +D Negative range overflow in I and D Positive range overflow in +I, I, +D, D, NEGI, and NEGD Positive range overflow in I, D, /I, and /D Negative range overflow in +I, I, +D, and D Division by 0 in /I, /D, and MOD
2-14
Table 2-15 CC 1 0 0 1 1
CC 1 and CC 0 after Floating-Point Math Instructions, with Overflow CC 0 0 1 0 1 Gradual underflow Negative range overflow Positive range overflow Invalid floating-point number Explanation
Table 2-16 CC 1 0 0 1 1
CC 1 and CC 0 after Comparison Instructions CC 0 0 1 0 1 Explanation Accumulator 2 = accumulator 1 Accumulator 2 < accumulator 1 Accumulator 2 > accumulator 1 Accumulator 1 or accumulator 2 is an invalid floating-point number
Table 2-17 CC 1 0 1
CC 1 and CC 0 after Shift and Rotate Instructions CC 0 0 0 Explanation Last bit shifted out = 0 Last bit shifted out = 1
Table 2-18 CC 1 0 1
CC 1 and CC 0 after Word Logic Instructions CC 0 0 0 Explanation Result = 0 Result <> 0
2-15
Binary Result Bit
The binary result bit (BR bit) forms a link between the processing of bits and words. It is an efficient means of interpreting the result of a word operation as a binary result and integrates this result in a binary logic string. Viewed in this way, the BR bit represents a machine-internal memory bit to which the RLO is saved prior to a word operation that changes the RLO, so that the RLO will be available again after the operation to continue the interrupted bit string. For example, the BR bit makes it possible for you to write a function block (FB) or a function (FC) in statement list (STL) and then call the FB or FC from ladder logic (LAD, see the Reference Manual /233/). When writing a function block or function that you want to call from LAD, no matter whether you write the FB or FC in STL or LAD, you are responsible for managing the BR bit. The BR bit corresponds to the enable output (ENO) of a LAD box. You should use the SAVE instruction (in STL, see Section 5.9) or the (SAVE) coil (in LAD) to store an RLO in the BR bit according to the following criteria:
S Store an RLO of 1 in the BR bit for a case where the FB or FC is

executed without error.
S Store an RLO of 0 in the BR bit for a case where the FB or FC is

executed with error You should program these instructions at the end of the FB or FC so that these are the last instructions that are executed in the block. When you call a system function block (SFB) or a system function (SFC) in your program, the SFB or SFC indicates whether the CPU was able to execute the function with or without errors by providing the following information in the binary result bit:
S If an error occurred during execution, the BR bit is 0. S If the function was executed with no error, the BR bit is 1.
2-16
Addressing
Chapter Overview
Section 3.1 3.2 3.3 3.4 3.5 3.6 Immediate Addressing Direct Addressing Memory Indirect Addressing Address Registers Area-Internal Register Indirect Addressing Area-Crossing Register Indirect Addressing Description
3
Page 3-2 3-2 3-3 3-6 3-7 3-11
3-1
Addressing
3.1
Immediate Addressing
Description
With immediate addressing, the address is coded directly in the instruction; that is, it directly follows the value with which the instruction is to work (for example, Load). An instruction can also provide its own value (for example, SET, see Table 3-1).
Table 3-1 Immediate Addressing Example SET OW W#16#A320 L 27 L ABCD L B#(100,12) L C#0100 Set the RLO to 1. Or Word. Load the integer value 27 into accumulator 1. Load the ASCII characters ABCD into accumulator 1. Load the two bytes 100 and 12 into accumulator 1. Load the BCD value 0000 into accumulator 1. Description
Examples
3.2
Direct Addressing
Description
An instruction that uses direct addressing has the following two-part address that indicates the location of the value that the instruction is going to process:
S An address identifier (for example, IB for input byte) S An exact location within the memory area that is indicated by the address
identifier The address points directly to the location of the value.
Table 3-2 Direct Addressing Example A I 0.0 S L 20.0 = M 115.4 L IB0 L MW64 T DBD12 Description Perform an AND logic operation on input bit I 0.0. Set the local data bit L 20.0. Assign the RLO to memory bit M 115.4 Load input byte IB0 into accumulator 1. Load memory word MW64 into accumulator 1. Transfer the contents from accumulator 1 into data double word DBD12.
Examples
3-2
Addressing
3.3
Memory Indirect Addressing
Description
An instruction that uses memory indirect addressing has the following two-part address that indicates the location of the value that the instruction is going to process:
S An address identifier (for example, IB for input byte) S One of the following pointers:
A word that contains the number of a timer (T), counter (C), data block (DB), function (FC), or function block (FB) A double word that contains the exact location of a value within the memory area that is indicated by the address identifier The address indicates the location of the value or number indirectly via the pointer. This word or double word can be in one of the following areas:
S Bit memory (M) S Data block (DB) S Instance data block (DI) S Local data (L)
The advantage of memory indirect addressing is that you can modify the statement address dynamically during program execution.
Using the Right Syntax
When working with a memory indirect address that is stored in the data block area of memory, first you must open the data block by using the Open a Data Block (OPN) instruction. Then you can use the data word or data double word as an indirect address, as shown in the following example: OPN DB10 L IB [DBD20]
Examples
Table 3-3 Memory Indirect Addressing
Example A I [MD2] or A I [anna] = DIX [DBD2] OPN DB [LW2] O Q [LD3] or O Q [boxcar]
Description Perform an And logic operation on the input bit whose exact location is in memory double word MD2 or in the location designated by anna in the symbol table, as a reference to MD2. Assign the RLO bit to the instance data bit whose exact location is in data double word DBD2. Open the data block whose data block number is located in local word LW2. Perform an Or logic operation on the output bit that is located in a local data double word LD3 or in a local TEMP variable designated as boxcar.
3-3
Addressing
Pointer Format
There are two possible pointer formats: word and double word. The abbreviation for a pointer in word format ends in W (for example, DBW). Figure 3-1 shows the pointer format for a word. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-2 shows the pointer format for a double word.
15.. ..8 nnnn nnnn
7.. ..0 nnnn nnnn
Bits 0 to 15 (nnnn nnnn nnnn nnnn): number (range 0 to 65,535) of a timer (T), counter (C), data block (DB), function (FC), or function block (FB)
Figure 3-1
Word Pointer Format for Memory Indirect Addressing
The following two examples show how to work with the word pointer format:
STL L +5 T MW2 OPN DB[MW2]
Explanation Load the value 5 as an integer into accumulator 1. Transfer the contents of accumulator 1 to memory word MW2. Open data block 5.
STL OPN L T A DB10 +20 DBW10 T[DBW10]
Explanation Open data block DB10. Load the value 20 as an integer into accumulator 1. Transfer the contents of accumulator 1 to data word DBW10 Check the signal state of timer T 20.
3-4
Addressing
31.. ..24 23.. ..16 15.. ..8 0000 0000 0000 0 bbb bbbb bbbb
7.. bbbb b
..0 xxx
Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed byte Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit
Figure 3-2
Double Word Pointer Format for Memory Indirect Addressing
Note If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.
The following two examples show you how to work with the double word pointer format:
STL L T P#8.7 MD2
Explanation Load 2#0000 0000 0000 0000 0000 0000 0100 0111 (binary value) into accumulator 1. Store the exact location 8.7 in memory double word MD2. The controller checks input bit I 8.7 and assigns its signal state to output bit Q 8.7.
A I [MD2] = Q [MD2]
STL L T P#8.0 MD2
Explanation Load 2#0000 0000 0000 0000 0000 0000 0100 0000 (binary value) into accumulator 1. Store the exact location 8 in memory double word MD2. The controller loads input byte IB8 and transfers the contents to memory word MW8. The exact location 8 comes from memory double word MD2.
L IB [MD2] T MW [MD2]
3-5
Addressing
3.4
Address Registers
Explanation
Some types of indirect addressing in statement list programming require the use of certain registers in the CPU. These registers are described below.
Address Registers 1 and 2
Address registers 1 and 2 (AR1 and AR2) are 32-bit registers that accept an area-internal or area-crossing pointer for commands that use register-indirect addressing (see Sections 3.5 and 3.6).
Pointers
Pointers are used in register-indirect addressing (see Sections 3.5 and 3.6). The following two types are available:
S Area-internal: used for area-internal access to bits, bytes, words, and

double words in memory areas P, I, Q, M, DBX, DIX, and L
S Area-crossing: used for area-crossing access to bits, bytes, words, and

double words in memory areas P, I, Q, M, DBX, DIX, and L
3-6
Addressing
3.5
Area-Internal Register Indirect Addressing
Description
An instruction that uses area-internal register indirect addressing has the following two-part address that indicates the memory location of the value that the instruction is going to process:
S An address identifier (for example, LD for local data double word,

see Table 2-6)
S An address register and a pointer to specify byte and bit. The byte and bit
indicate an offset, which, when added to the contents of the register, indicate the memory location of the value that the instruction is to process. The address points to the memory location of the value indirectly via the address register plus offset. A statement that uses area-internal register indirect addressing does not change the value in the address register.
Calculating the Memory Location of the Address
The address of an instruction points to the value that the instruction is going to process. Where area-internal register indirect addressing is concerned, the address points to the memory location of the value indirectly via the address register plus offset. Figure 3-3 shows how you calculate the memory location for the address of the Assign (=) instruction in the following statement: = Q [AR1, P#1.1]
Byte Contents of address register AR1: 8.7 + Offset P#: Memory location: 1.1 output byte Q 10.0
Bit byte 8, bit 7 byte 1, bit 1 bytes: 9, bits: 8 (= 1 byte) (9 bytes + 1 byte = 10 bytes)
Figure 3-3
Calculating the Memory Location of Output Q [AR1, P#1.1]
You calculate the memory location of the address by adding the byte portion of the contents of the address register to the byte portion of the offset pointer and by adding the bit portion of the contents of the address register to the bit portion of the offset pointer. You calculate the byte portion of the memory location using decimal math and the bit portion using octal math (8 bits = 1 byte). There can be a carry between the bit and byte portions.
3-7
Addressing
Table 3-4
Area-Internal Register Indirect Addressing Example Description Perform an And logic operation on the input bit whose memory location is calculated by the contents of address register AR1 plus 4 bytes, plus 3 bits. Assign the RLO bit to the instance data bit whose memory location is in address register AR2. Load the input byte whose memory location is calculated by the contents of address register AR1 plus 100 bytes into accumulator 1. Transfer the contents of accumulator 1 into local data double word LD whose memory location is calculated by the contents of address register AR2 plus 56 bytes. With reference to addressing local data, please read the Warning below.
Examples
A I [AR1, P#4.3]
= DIX [AR2, P#0.0] L IB [AR1, P#100.0]
T LD [AR2, P#56.0]
Warning Possible overwriting of the data that is used by the compiler. When you use absolute addressing to access temporary local data, there is no guarantee that there will be no conflict between the data used by the compiler and the local data that you are attempting to access by means of absolute addressing. It is possible that you overwrite some of the data that the compiler uses. (For example, the compiler uses local data for transferring formal parameters.) Local data that the compiler needs are attached to the symbolic data that are defined by the person doing the programming. When accessing temporary local data, you are advised to choose symbolic addressing over absolute addressing.
3-8
Addressing
Pointer Format
Area-internal register indirect addressing has only one possible pointer format: double word. This double word contains an address encoded as a bit address. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-4 shows the pointer format for a double word.
31.. ..24 23.. ..16 15.. ..8 7.. 0000 0000 0000 0 bbb bbbb bbbb bbbb b Bit 31 = 0 to indicate area-internal register indirect addressing
..0 xxx
Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed bit Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit Figure 3-4 Double Word Pointer Format for Area-Internal Register Indirect Addressing
Note If you access a byte, word, or double word, be sure that the bit number of your pointer is 0.
3-9
Addressing
STL L P#8.7
Explanation Load a double word pointer to bit address location 8.7 into accumulator 1. Store a double word pointer to bit address location 8.7 in address register AR1. The CPU adds the offset (P#0.0) to the contents of address register AR1 (8.7) and uses this address as the location of an And bit logic instruction. The contents of AR1 remain unchanged. The CPU assigns the result of the And bit logic operation (RLO) to an address (Q 10.0). The CPU calculates this address by adding the contents of address register AR1 (8.7) and the offset (P#1.1).
LAR1
A I [AR1, P#0.0]
= Q [AR1, P#1.1]
STL L P#8.0
Explanation Load a double word pointer to bit address location 8.0 into accumulator 1. Store a double word pointer to bit address location 8.0 in address register AR2. The CPU loads input byte IB10 into accumulator 1. The CPU transfers the contents of accumulator 1 to memory word MW208. The location 208 comes from 8 (AR2) plus 200 (offset), which is 208.
LAR2
L IB [AR2, P#2.0] T MW [AR2, P#200.0]
3-10
Addressing
3.6
Area-Crossing Register Indirect Addressing
Description
An instruction that uses area-crossing register indirect addressing has the following two-part address that indicates the memory location of the value that the instruction is going to process:
S An address identifier that indicates the size of a data object (for example,
B for byte, see Table 2-8). The memory area is indicated in bits 24, 25, and 26 of the address register.
S An address register and a pointer that indicate an offset which, when

added to the contents of the address register, indicates the memory location of the value that is to be processed by the instruction. The pointer is indicated by P#byte.bit. The address points to the memory location of the value indirectly via the address register plus offset. A statement that uses area-crossing register indirect addressing does not change the value in the address register.
Calculating the Memory Location of the Address
The address of an instruction points to the value that the instruction is going to process. Where area-crossing register indirect addressing is concerned, the address points to the memory location of the value indirectly via the address register plus offset. Figure 3-5 shows how you calculate the memory location for the address of the Assign (=) instruction in the following statement: = [AR1, P#1.1]
Byte Contents of address register AR1: 8.7 + Offset P#: Memory location: 1.1 byte 10.0
Bit byte 8, bit 7 byte 1, bit 1 bytes: 9, bits: 8 (= 1 byte) (9 bytes + 1 byte = 10 bytes)
Figure 3-5
Calculating the Address [AR1, P#1.1]
You calculate the memory location of the address by adding the byte portion of the contents of the address register to the byte portion of the offset pointer and by adding the bit portion of the contents of the address register to the bit portion of the offset pointer. You calculate the byte portion of the memory location using decimal math and the bit portion using octal math (8 bits = 1 byte). There can be a carry between the bit and byte portions.
3-11
Addressing
Example
Table 3-5 provides examples of area-crossing register indirect addressing. The address must contain an additional area identification in bits 24, 25, and 26 of the pointer. The addressed information is in the address register.
Table 3-5 Area-Crossing Register Indirect Addressing Example A [AR1, P#4.3] Description Perform an And logic operation on the bit whose memory location is calculated by the contents of address register AR1, plus 4 bytes plus 3 bits. The memory area of the bit is indicated in bits 24, 25, and 26 of address register AR1. Assign the RLO bit to the bit whose memory location is in address register AR2. The memory area of the bit is indicated in bits 24, 25, and 26 of address register AR2. Load into accumulator 1 the byte whose memory location is calculated in address register AR1 plus 100 bytes. The memory area of the byte is indicated in bits 24, 25, and 26 of address register AR1. Transfer the contents of accumulator 1 into the double word whose memory location is calculated by the contents of address register AR2 plus 56 bytes. The memory area of the double word is indicated in bits 24, 25, and 26 of address register AR2.
= [AR2, P#0.0]
L B [AR1, P#100.0]
T D [AR2, P#56.0]
Table 3-6 lists the binary code in bits 24, 25, and 26 of the pointer that identifies the area.
Table 3-6 Area Identification for Area-Crossing Register Indirect Addressing Binary Contents of Bits 26, 25, and 24 000 001 010 011 100 101 111
Area Identification (Memory Area) P I Q M (I/O, external inputs and outputs) (process-image input) (process-image output) (bit memory)
DBX (data block) DIX (data block) (previous local data, that is, the local data of the previous incompleted block)
3-12
Addressing
Pointer Format
Area-crossing register indirect addressing has only one possible pointer format: double word. The abbreviation for a double word format ends in D (for example, DBD). Figure 3-6 shows the pointer format for a double word.
31.. ..24 23.. 1000 0rrr 0000 0
..8 7.. 3.. ..16 15.. ..0 bbb bbbb bbbb bbbb b xxx
Bit 31 = 1 to indicate area-crossing register indirect addressing Bits 24, 25, and 26 (rrr): area identification (memory area, see Table 3-6) Bits 3 to 18 (bbbb bbbb bbbb bbbb): byte number (range 0 to 65,535) of the addressed bit Bits 0 to 2 (xxx): bit number (range 0 to 7) of the addressed bit Figure 3-6 Double Word Pointer Format for Area-Crossing Register Indirect Addressing
Note If you access a byte, word, or double word, be sure that the bit number of your pointer is 0. You cannot access local data using area-crossing register indirect addressing!
3-13
Addressing
STL L P#I 8.7
Explanation Load a double word pointer to bit address location I 8.7 into accumulator 1. Store a double word pointer to bit address location I 8.7 in address register AR1. Load a double word pointer to bit address location Q 8.7 into accumulator 1. Store a double word pointer to bit address location Q 8.7 in address register AR2. The CPU adds the contents of address register AR1 (P#I 8.7) and the offset (P#0.0) and uses the address pointed to by the result (I 8.7) as the address of an And bit logic instruction. The contents of AR1 remain unchanged. The CPU assigns the result of the And bit logic operation (RLO) to an address (Q 10.0). The CPU calculates this address by adding the contents of address register AR2 (P#Q 8.7) and the offset (P#1.1) and dereferencing the pointer. The contents of AR2 remain unchanged.
LAR1
L P#Q 8.7
LAR2
A [AR1, P#0.0]
= [AR2, P#1.1]
STL L P#I 8.0
Explanation Load a double word pointer to bit address location I 8.0 into accumulator 1. Store a double word pointer to bit address location I 8.0 in address register AR2. Load a double word pointer to bit address location M 8.0 into accumulator 1. Store a double word pointer to bit address location M 8.0 in address register AR1. The CPU loads input byte IB10. The CPU transfers the contents to memory word MW208. Input byte 10 comes from 8 (AR2) plus 2 (offset). Memory word 208 comes from 8 (AR1) plus 200 (offset), which is 208.
LAR2
L P#M 8.0
LAR1
L B [AR2, P#2.0] T W [AR1, P#200.0]
3-14
Accumulator Operations and Address Register Instructions

Chapter Overview
Section 4.1 4.2 4.3 4.4 Overview ENT and LEAVE Incrementing and Decrementing +AR1 und +AR2: Adding a Constant to Address Register 1 or Address Register 2 Description
4
Page 4-2 4-3 4-6 4-7
4-1
Accumulator Operations
4.1
Overview
The following instructions are available to you for handling the contents of one or both accumulators:
Mnemonic Instruction Toggle Accumulator 1 with Accumulator 2 Explanation This instruction exchanges the contents of accumulator 1 with the contents of accumulator 2.
TAK PUSH with 2 ACCUs POP with 2 ACCUs PUSH with 4 ACCUs POP with 4 ACCUs ENT
Accumulator 1 to Accumulator 2 This instruction copies the contents of accumulator 1 to accumulator 2. Accumulator 2 to Accumulator 1 This instruction copies the contents of accumulator 2 to accumulator 1. Copy ACCU 3 to ACCU 4, ACCU 2 to ACCU 3, ACCU 1 to ACCU 2 Copy ACCU 2 to ACCU 1, ACCU 3 to ACCU 2, ACCU 4 to ACCU 3 Enter accumulator stack This instruction copies the contents of accumulator 3 to accumulator 4, the contents of accumulator 2 to accumulator 3 and the contents of accumulator 1 to accumulator 2. This instruction copies the contents of accumulator 2 to accumulator 1, the contents of accumulator 3 to accumulator 2 and the contents of accumulator 4 to accumulator 3. This instruction copies the contents of accumulator 3 to accumulator 4 and the contents of accumulator 2 to accumulator 3. This instruction copies the contents of accumulator 3 to accumulator 2 and the contents of accumulator 4 to accumulator 3. This instruction increases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255. This instruction decreases the contents of the low byte of the low word of accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255. This instruction adds the contents of the low word of accumulator 1 to address register 1 or 2. This instruction adds a constant to the contents of address register 1 or 2. This instruction does not carry out any function and does not influence the status bits. The instruction is only relevant to the programming device (PG) when a program is displayed. The address <number> is the ID of the instruction BLD and is generated by the programming device. These instructions do not carry out any function, nor do they influence the contents of the status word. The instructions NOP 1 and NOP 0 are required for decompiling. The instruction code contains a bit pattern with either 16 zeroes or 16 ones.
LEAVE
Leave accumulator stack
INC
Increment Accumulator 1
DEC
Decrement Accumulator 1
+AR1, +AR2 +AR1 P#Byte.Bit, +AR2 P#Byte.Bit BLD
Add Accumulator 1 to Address Register Add Constant to Address Register Program Display Instruction
NOP 0 NOP 1
Null Instruction 0 Null Instruction 1
For information on reversing the order of bytes in accumulator 1, see Section 12.3.
4-2
4.2
ENT and LEAVE
Description
With the instructions ENT (Enter Accumulator Stack) and LEAVE (Leave Accumulator Stack) you can carry out the following functions:
S The instruction ENT copies the contents of Accumulator 3 to Accumulator

4 and the contents of Accumulator 2 to Accumulator 3. If you program the ENT instruction directly before a load instruction, it SHIFTS Accumulator 2 and Accumulator 3 further in the stack.
S The instruction LEAVE copies the contents of Accumulator 3 to

Accumulator 2 and the contents of Accumulator 4 to Accumulator 3. If you program the LEAVE instruction directly before a shift and rotate instruction, which combines accumulators, then the LEAVE instruction will function like a math operation.
ENT
Figure 4-1 shows how the ENT instruction works.
ACCU 4 31 I II III IV 0
ENT 31 V
ACCU 4 0 VI VII VIII
ACCU 3 31 V VI VII 0 VIII 31 IX
ACCU 3 0 X XI XII
ACCU 2 31 IX X XI 0 XII 31 IX
ACCU 2 0 X XI XII
ACCU 1 31 XIII XIV XV XVI 0 31 XIII
ACCU 1 0 XIV XV XVI
Figure 4-1
Copying the contents of Accumulator 3 to Accumulator 4 and the contents of Accumulator 2 to Accumulator 3 in the ENT instruction ENT
4-3
LEAVE
Figure 4-2 shows how the LEAVE instruction works.
ACCU 4 31 I II III IV 0
LEAVE 31 I
ACCU 4 0 II III IV
ACCU 3 31 V VI VII 0 VIII 31 I
ACCU 3 0 II III IV
ACCU 2 31 IX X XI 0 XII 31 V
ACCU 2 0 VI VII VIII
ACCU 1 31 XIII XIV XV 0 XVI 31 XIII
ACCU 1 0 XIV XV XVI
Figure 4-2
Copying the contents of Accumulator 3 to Accumulator 2 and the contents of Accumulator 4 to Accumulator 3 in the LEAVE instruction
Example
The following program extract shows the use of the ENT instruction. The floating points in the data double words DBD0 and DBD4 should be added together. The sum should then be divided by the difference of the floating points of the data double words DBD8 and DBD12.
DBD0 + DBD4 DBD8 DBD12
DBD16 =
The quotient of the above division should be stored in DBD16. In this example, the purpose of the ENT instruction is to take the interim result (DBD0+DBD4), which is located in Accumulator 2 and save it in Accumulator 3. The subtraction command (-R) copies the interim result back to Accumulator 2 following the subtraction.
4-4
STL L L +R DBD0 DBD4
Explanation Load the value from data double word DBD0 in ACCU1 (the value must be in floating-point format). Copy the value from ACCU1 to ACCU2.Load the value from data double word DBD4 in ACCU1 (the value must be in floating-point format). Add the contents of ACCU1 and ACCU2 as floating-point numbers (32 bits, IEEE-FP) and store the result in ACCU1. Copy the value from ACCU1 to ACCU2. Load the value from data double word DBD8 to ACCU1. Copy the contents of ACCU3 to ACCU4. Copy the contents of ACCU2 (interim result) to ACCU3. Copy the contents of ACCU1 to ACCU2. Load the contents from data double word DBD12 to ACCU1. Subtract the contents of ACCU1 from the contents of ACCU2. Store the result in ACCU1. Copy the contents of ACCU3 to ACCU2. Divide the contents of ACCU 2 by the contents of ACCU1. Save the quotient in ACCU1. Transfer the result (ACCU1) to the data double word DBD16.
L ENT L R
DBD8
DBD12
/R T DBD16
4-5
4.3
Incrementing and Decrementing
Description
You can use the Increment Accumulator 1 (INC) and Decrement Accumulator 1 (DEC) instructions to perform the following functions:
S INC increases the contents of the low byte of the low word of
accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255.
S DEC decreases the contents of the low byte of the low word of
accumulator 1 by the 8-bit constant that is indicated in the instruction statement. The constant can be in the range of 0 to 255. The CPU always executes the INC and DEC instructions, regardless of the result of logic operation. These instructions do not affect the RLO nor do they change any of the bits in the status word. Note These instructions are not suitable for 16-bit or 32-bit math because no carry is made from the low byte of the low word of accumulator 1 to the high byte of the low word of accumulator 1. For 16-bit or 32-bit math, use the +I or +D instruction, respectively.
Example
The following sample program provides an example of how the INC instruction works within a loop triggered by a conditional jump.
STL
Explanation
Body of a loop operation

L T L INC T . . L <= SPB 1 MB10 MB10 1 MB10
Set the loop counter to 1. Load the contents of memory byte MB10 into accumulator 1. Increment the loop counter by 1. Transfer the contents of accumulator 1 to memory byte MB10. Instruction section which is processed five times. If the program has not run through the loop five times, then return to LOOP.
M1:
B#16#5 I M1
4-6
4.4
+AR1 und +AR2: Adding a Constant to Address Register 1 or Address Register 2
Description
Using the instructions +AR1 and +AR2 you can add a constant to the contents of address registers 1 and 2:
Table 4-1 Instruction +AR1 Adding to the Contents of Address Registers Address Function Adds the contents of the low word of accumulator 1 to the contents of address register 1. Adds the contents of the low word of accumulator 1 to the contents of address register 2. Adds a pointer constant to the contents of address register 1. Adds a pointer constant to the contents of address register 2.
+AR2
+AR1 +AR2
P#Byte.Bit: (range 0.0 to 4095.7)1 P#Byte.Bit: (range 0.0 to 4095.7)1
The bits 24, 25, and 26 of the address register remain unchanged. These bits indicate the memory area.
Note The address register 2 is used when multiple instances are being processed. Therefore, before programming the command +AR2, you must save the contents of AR2 and load them again later.
Examples
Below are sample statements that use the +AR1 and +AR2 instructions. Loading the pointer format into accumulator 1 and then using the +AR1 or +AR2 instruction, as shown in the first two statements below, enables you to select from a range of 0.0 to 8191.7.
Explanation Load a Add the address Because
STL L P#250.7 +AR1 TAR2 #SAVE_AR2 +AR2 P#126.7 . . L AR2 #SAVE_AR2
pointer constant (250.7) into accumulator 1.

contents of accumulator 1 (250.7) to the contents of register 1. multiple instances are using AR2 as base.
Add a pointer constant (126.7) to the contents of address register 2. Restore AR2.
4-7
4-8
Bit Logic Instructions

Chapter Overview
Section 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Boolean Bit Logic Bit Logic Instructions and Relay Coil Circuit Evaluating Conditions Using And, Or, and Exclusive Or Nesting Expressions and And before Or Instructions for Transitional Contacts: FP, FN Output of Boolean Logic String Set and Reset Instructions: S and R Assign Instruction (=) Negating, Setting, Clearing, and Saving the RLO Description
5
Page 5-2 5-6 5-10 5-14 5-16 5-20 5-21 5-24 5-26
5-1
5.1
Boolean Bit Logic
Explanation
Boolean bit logic applies to the following basic instructions:
S And (A) and its negated form, And Not (AN) S Or (O) and its negated form, Or Not (ON) S Exclusive Or (X) and its negated form, Exclusive Or Not (XN)
These instructions perform the following basic functions:
S They check the signal state of an address to establish whether an address

is activated 1, or not activated 0.
S They check the signal state of a timer or a counter to establish whether it

is set at 0 (value = 0) or 1 (value > 0). The FC bit determines the result of logic operation (RLO):
S If FC is 0, the result of the state check will remain unchanged and will be
stored in the RLO (start of a logic string).
S If FC is 1, the result of the state check will be combined with the logic
instruction (A, O, X) according to the truth table and will be stored in the RLO.
Truth Table at the Start of a Boolean Logic String
The result of logic operation can be determined with the help of the following truth table: Mnemonic A AN O ON X XN And And Not Or Or Not Exclusive Or Exclusive Or Not Instruction Status of Address 0 1 0 1 0 1 0 1 0 1 0 1 Result in RLO 0 1 1 0 0 1 1 0 0 1 1 0
5-2
Truth Table within the Boolean Logic String
After the second Boolean bit operation the RLO can be established with the help of the following table: Mnemonic A Instruction And RLO Before Instruction 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Status of Address 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Result in RLO 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1 1 0 1 1 0 1 0 0 1
AN
And Not
Or
ON
Or Not
Exclusive Or
XN
Exclusive Or Not
Addresses of Basic Functions (A, AN, O, ON, X, XN)
The address of an instruction can be a bit, a timer or a counter. The instruction accesses the contact with one of these addressing types: S The address identifier and the address within the memory area defined by the address identifier (see Tables 5-1 and 5-3). S Bit, timer or counter transferred as parameter (see Table 5-4). S Conditions, expressed in bits of the status word (see Table 5-8).
5-3
Table 5-1 Address ID I Q
Addresses: Direct and Indirect Addressing Maximum Address Range According to Addressing Type Direct 0.0 to 65,535.7 Memory Indirect [DBD] [DID] [LD] [MD] [DBD] [DID] [LD] [MD] [DBD] [DID] [LD] [MD] Register Indirect, Area-Internal [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0.0 to 8,191.7 0.0 to 8,191.7 0.0 to 8,191.7
0.0 to 65,535.7
DBX DIX L
0.0 to 65,535.7
Table 5-2
Addresses: Area-Crossing Register Indirect Addressing Address Identifier1 Maximum Address Range [AR1, P#byte.bit] [AR2, P#byte.bit] 0.0 to 8,191.7
I, Q, M, DBX, DIX, or L
1
The memory area is encoded in pointer bits 24, 25, and 26 (see Section 3.6). Addresses: Timers and Counters Maximum Address Range According to Addressing Type Address Ident Identifier f er Direct Memory Indirect [DBW] [DIW] [LW] [MW]
Table 5-3
T C
0 to 65,535
0 to 65,534
Table 5-4
Address: Bit, Timer, or Counter Transferred as Parameter Address Parameter Format A bit, timer, or counter transferred as parameter
Address Symbolic name
Table 5-5
Addresses of Boolean Bit Logic Instructions: Bits of the Status Word Bits of the Status Word 7 and 6: condition codes 1 and 0 (memory area) 7 and 6: condition codes 1 and 0 (memory area) 8: binary result (location) 5: overflow (location) 4: overflow, stored (location)
Memory Area or Reference to a Location >0, <0, <>0, >=0, <=0, ==0 UO BR OV OS
5-4
Change of Bits in the Status Word
Instruction A AN A( AN( O ON O( ON( X XN X( XN( = CLR FN FP NOT R S SAVE SET
OR x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
STA x x 1 1 x x 1 1 x x 1 1 x 0 x x 1 x x 1
RLO x x x x x x 0 x x x 1
FC 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0
5-5
5.2
Bit Logic Instructions and Relay Coil Circuit
Introduction
Bit logic instructions are also named relay logic instructions as they can execute commands which can replace the function of a relay logic circuit. The following explains how a relay logic circuit can be reproduced with STL commands.
Normally Open Contact
Figure 5-1 shows a relay logic circuit with normally open control relay contact between a power rail and a coil. The normal state of this contact is open. If the contact is not activated, it remains open. The signal state of the open contact is 0 (not activated). If the contact remains open, the power from the power rail cannot energize the coil at the end of the circuit. If the contact is activated (signal state of the contact is 1), power will flow to the coil.
Power Rail Normally Open Contact I 1.1
Coil
Q 4.0
Figure 5-1
Relay Logic Circuit with Normally Open Control Relay Contact
You can use an And (A) or an Or (O) instruction to check the signal state of a normally open control relay contact. If the normally open contact (I1.1 = 0) is open the check result is 0, if it is closed the result is 1.
5-6
Normally Closed Contact
Figure 5-2 shows the representation of a relay logic circuit with normally closed control relay contact between a power rail and a coil. The normal state of this contact is closed. If the contact is not activated, it remains closed. The signal state of the closed contact is 0 (not activated). If the contact remains closed, power from the power rail can cross the contact to energize the coil at the end of the circuit. Activating the contact (signal state of the contact is 1) opens the contact, interrupting the flow of power to the coil.
Power Rail Normally Closed Contact I 1.1
Coil
Q 4.0
Figure 5-2
Relay Logic Circuit with Normally Closed Control Relay Contact
You can use an And Not (AN) or an Or Not (ON) instruction to check the signal state of a normally closed control relay contact. If the normally closed contact is closed (I1.1 = 0) the check result is 1, if it is open the result is 0.
Power Flow in a Series Circuit
Figure 5-3 shows an example with a statement list that uses an AND instruction (A) to program two normally open contacts in series. Only when the signal state of both the normally open contacts is 1, can the state of output Q4.0 be set to 1 and the coil be energized.
Relay Logic Diagram
A I 1.0
I 1.0
A I 1.1
I 1.1
= Q 4.0
Q 4.0
Figure 5-3
Using the And Instruction to Program Contacts in Series
5-7
Power Flow in a Parallel Circuit
Figure 5-4 shows a statement list that uses an Or instruction (O) to program each of two normally open contacts connected in parallel to a coil. Only when the signal state of one of the normally open contacts is 1, can the state of output Q4.0 be set to 1 and the coil be energized.
Relay Logic Diagram Power Rail I 1.0 I 1.1
O I 1.0 O I 1.1 = Q 4.0 Q 4.0
Figure 5-4
Using the Or Instruction to Program Contacts in Parallel
Exclusive Or
The Exclusive Or (X) instruction in STL corresponds to a relay logic circuit, as in Figure 5-5, in which a normally closed contact and a normally open contact are connected. Q4.0 is 1 when I1.0 and I1.0 have different values.
Statement List Program Power Rail Contact I 1.0 Contact I 1.1
Relay Logic Diagram
X I 1.0 X I 1.1 = Q 4.0
Coil Q 4.0
Figure 5-5
Using the Exclusive Or instruction to Program Contacts in Parallel
5-8
AN, ON, XN
Similarly the following instructions can affect other actions:

AN: Affects the series connection of a normally closed contact..
Relay Logic Diagram

Power Rail
A I 1.0
I 1.0 Normally Open Contact I 1.1 Normally Closed Contact Q 4.0 Coil
AN I 1.1
= Q 4.0
ON: Affects the parallel connection of a normally closed contact.
Relay Logic Diagram

Power Rail
O I 1.0
ON I 1.1
= Q 4.0
XN: Affects the interconnected series connection of a normally closed contact and a normally open contact.
Relay Logic Diagram

Power Rail
X I 1.0
XN I 1.1
= Q 4.0
5-9
5.3
Evaluating Conditions Using And, Or, and Exclusive Or
Description
With the bit logic instructions you can check the bits of the status word CC 0, CC 1, BR, OV and OS. These can be influenced by the following instructions (Table 5-6).
Table 5-6 Instructions That Affect the CC, BR, OV, and OS Bits of the Status Word Instruction )I, *I, /I,<I, )D, *D, /D,<D, MOD ==I, <>I, <I, <=I, >I, >=I, ==D, <>D, <D, <=D,>D, >=D )R, *R,<R , /R, SQRT, SQR, LN, EXP, SIN, COS, TAN, ASIN, ACOS, ATAN ==R, <>R, <R, <=R, >R, >=R BTI, BTD, RND, RND*, RND), TRUNC, NEGI, NEGD SLW, SRW, SLD, SRD, SSI, SSD, RLD, RRD, RLDA, RRDA AW, OW, XOW, AD, OD, XOD ) SAVE JCB, JNB, SPS BEB, BE, BEA, CC, UC T STW Section in This Manual 9.1 11.2 10.1
Type of Instruction Integer Four-Function Math Integer Comparisons (Integer Math Instructions) Floating-Point Math
Floating-Point Comparisons Conversion Shift and Rotate Functions Word Logic Nesting Saving the RLO to BR Register Logic Control Program Control Transfer
11.3 12.1, 12.2, and 12.4 14.1 and 14.2 13.2 5.4 5.9 16.1 17.6 8.3
5-10
Relationship of a Result to 0
The combination of bits CC 1 and CC 0 in the status word can easily be checked using replacement addresses (for example, >0, ==0, <0, etc.). Table 5-7 shows the connection between different bit combinations and simple checking. For example, you can check the combination CC 1 = 0 and CC 0 = 1 in an And instruction with A <0.
Table 5-7 Combination States of CC 0 and CC 1 and Relevant Check Option
If the following signal combination is in the status word ... Signal State of CC 1 1 0 0 or 1 1 or 0 0 or 0 0 1 Signal State of CC 0 0 1 1 or 0 0 or 0 1 or 0 0 1
... the check can be carried out using
>0 <0 <>0
>=0
<=0 ==0 UO
STL L +10 //LOWER LIMIT L MW30
Explanation Load the integer 10 into accumulator 1 low as a lower limit. Load the value in memory word MW30 into accumulator 1 low, transferring the integer value 10 to accumulator 2 low. Is 10 less than or equal to the value in MW30? If yes, then set the RLO to 1; otherwise reset the RLO to 0. Load the integer 100 into accumulator 1 low as an upper limit, transferring the value from MW30 stored in accumulator 1 low to accumulator 2 low. Subtract 100 from the value in MW30. The result sets CC 1 and CC 0 with a bit combination that shows how the result compares to 0 (see Table 5-7). The RLO is not changed. According to the bit combination in CC 1 and CC 0, is the condition <= 0 fulfilled? Yes produces a 1; no produces a 0 (see Table 5-7). Combine this 1 or 0 with the RLO according to the And truth table, Store the result in the RLO bit. Write the value of the RLO to the signal state of output Q 4.0. The coil at output Q 4.0 is energized (has a signal state of 1) if the value in MW30 is greater than or equal to 10 and less than or equal to 100.
<=I
L +100 //UPPER LIMIT
U <=0
= Q 4.0
5-11
The Boolean bit logic instructions can also enable your program to react if the result of a floating-point math operation is illegal because one of the numbers is not a valid floating-point number (unordered, UO). The instruction checks the signal state of bits CC1 and CC0 of the status word (see Table 5-7).
Overflow and Binary Result
Some of the instructions listed in Table 5-6 can set the binary result bit (BR) or the overflow bits (OV and OS) of the status word to 1. You can use the A, AN, O, ON, X, and XN bit logic instructions together with the following memory areas to enable your program to react to an overflow or to a binary result bit that is set to 1.
STL L MW10 L MW20
Explanation Load the integer in MW10 into accumulator 1 low. Load the integer in MW20 into accumulator 1 low, transferring the value from MW10 to accumulator 2. Add the two integer values in the accumulators. Transfer the result from accumulator 1 low to MW30. Check the signal state at input I 0.0 for 1 or 0. Check the OV bit of the status word for 1 or 0. If the signal state of I 0.0 is 1 and there is a 1 in the OV bit of the status word (i.e., an overflow occurred during the last math operation), set the signal state of output Q 4.0 to 1; otherwise set it to 0.
+I T MW30 A I 0.0 A OV = Q 4.0
STL A BR = Q 4.0
Explanation Check the BR bit of the status word for 1 or 0. If there is a 1 in the BR bit of the status word, set the signal state of output Q 4.0 to 1; otherwise set it to 0.
5-12
Addressing the Bits of the Status Word
The Boolean bit logic instructions evaluate conditions by using the addresses shown in Table 5-8.
Table 5-8 Addresses of Boolean Bit Logic Instructions: Bits of the Status Word Bit(s) of Status Word 7 and 6: condition codes 1 and 0 (memory area) 7 and 6: condition codes 1 and 0 (memory area) 8: binary result (location) 5: overflow (location) 4: overflow, stored (location)
Memory Area or Reference to a Location >0, <0, <>0, >=0, <=0, ==0 UO BR OV OS
5-13
5.4
Nesting Expressions and And before Or
Description
You can use the And (A), Or (O), and Exclusive Or (X) instructions and their negated forms AN, ON, XN to perform Boolean logic operations on portions of a logic string that are enclosed in parentheses (nesting expressions). Parentheses around a portion of a logic string indicate that your program will perform the operations inside the parentheses before performing the logic operation indicated by the instruction that precedes the nesting expression. You can also combine And and Or statements in a Boolean logic string without using parentheses. By convention, the And statements are evaluated first and the results are then combined according to the Or truth table.
Result of Logic Operation
The instruction that opens a nesting expression stores the RLO from the preceding operation in the nesting stack. Later, the program will combine this stored RLO with the result produced by the logic combinations performed inside the parentheses.
Description The statements between A( and ) make up a normal Or combination. The result of the first check is stored in the RLO bit. According to the Or truth table, the result of check is combined with the RLO formed by the previous statement. This combination forms a new result that replaces the value in the RLO bit. A( copies the value currently in the RLO bit, stores it in the nesting stack, and ends the previous logic string. Therefore the next logic statement begins a new logic string, making a first check. The statements between A( and ) make up a normal Or combination. The result of the first check is stored in the RLO bit. According to the Or truth table, the result of check is combined with the RLO formed by the previous statement. This combination forms a new result that replaces the value in the RLO bit. The ) statement combines the RLO that is stored in the nesting stack (see the A( instruction above) with the current RLO according to the And truth table. This statement uses the And truth table because the ) ends a nesting expression that began with A. This logic combination forms a new RLO. This normal And statement combines the new RLO formed in the ) instruction above with the result of its check according to the And truth table. The Assign instruction (=, see Section 5.8) assigns the value of the RLO to the output coil.
STL A( O I 0.0 O M 10.0 )
A(
O I 0.2
O M 10.3
A M 10.1
= Q 4.0
5-14
And before Or
The following statement list uses the principle of And before Or to program a circuit. By convention, the program evaluates the And statements first. Then the program combines the results of the And operation according to the Or truth table. No parentheses are needed. The principle at work here is called And before Or.
STL A I 0.0 A M 10.0
Description The result of the first check is stored in the RLO bit. According to the And truth table, the result of check is combined with the RLO formed by the previous statement. This combination forms a new result that replaces the value in the RLO bit. The statement O copies the value currently in the RLO bit, stores it in the Or bit and ends the previous logic string. The statement O secures the RLO as one of the two values that it will use to carry out an Or operation, according to the principle And before Or. The result of the first check is stored in the RLO bit. In each And operation which follows an Or operation the newly formed RLO is combined with the Or bit. According to the And truth table, the result of check is combined with the RLO formed by the previous statement. This combination forms a new result that replaces the value in the RLO bit. In each And operation the newly formed RLO is combined with the Or bit. The first O operation fetches the stored RLO from the nesting stack and combines it with the current RLO. This operation results to a new value which is stored in the RLO bit as the result of an And before Or operation. (There is no special operation to end an And before Or operation. A special bit processor in the programmable controller finds the last A operation in an And before Or operation. The operation that follows the last A operation (e.g. =, S, R or O) ends the And before Or operation automatically with the estimation of the RLO.)
A I 0.2
A M 0.3
O M 10.1
The next O operation combines the result of the And before Or operation with the check result of the second O operation. The Assign instruction (=, see Section 5.8) assigns the value of the RLO to the output coil.
= Q 4.0
Output Q 4.0 is energized (its signal state is 1) if the result of either one or the other pair of And operations is 1 or if the result of the normal Or operation on M 10.1 is 1.
5-15
5.5
Instructions for Transitional Contacts: FP, FN
Description
You can use the Edge Positive (FP) and Edge Negative (FN) instructions like transition-sensing contacts in a relay circuit. These instructions detect and react to transitions in the result of logic operation. A transition from 0 to 1 is called a positive edge. A transition from 1 to 0 is called a negative edge (see Figure 5-6).
RLO 1 0 Figure 5-6
Positive Edge
Negative Edge
Time Representation of Positive and Negative Edges
Reacting to a Positive Edge
Figure 5-7 shows a statement list that enables your program to react to a positive edge transition. An explanation follows the figure.
Statement List A I 1.0 FP M 1.0 = Q 4.0 OB1 Scan Cycle No.: Figure 5-7 Signal State Diagram I 1.0 M 1.0 Q 4.0 1 2 3 4 5 6 7 8 9 1 0 1 0 1 0
Programming a Reaction to a Positive Edge Transition
If the programmable logic controller detects a positive edge at contact I 1.0, it energizes the coil at Q 4.0 for one OB1 scan cycle. The programmable logic controller stores the result of the logic operation performed by the A instruction in edge memory bit M 1.0 and compares it to the RLO from the previous scan cycle. (In the example in Figure 5-7, the RLO of the statement A I 1.0 just happens to be the same as the signal state of input I 1.0. This will not be the case for every program.) If the current RLO is 1 and the RLO from the previous scan cycle stored in memory bit M 1.0 is 0, then the FP statement sets the RLO to 1. The FP statement detects a positive edge at the contact (that is, the signal state of the RLO changed from 0 to 1). If there is no change in the RLO (current RLO and previous RLO stored in the edge memory bit are both equal to 0 or 1), then the FP statement resets the RLO to 0.
5-16
Table 5-9 OB1 Scan Cycle No. 1 2 3 4 5 6 7 8 9
Checking for Positive Edge Transition at Input I 1.0 Signal State at Input in Previous Cycle 0 (default value) 0 1 1 0 0 1 0 1 Signal State at Did the signal Input in state change Current Cycle from 0 to 1? 0 1 1 0 0 1 0 1 1 No Yes No No No Yes No Yes No Is the coil at Q 4.0 energized? No Yes No No No Yes No Yes No
Table 5-9 applies specifically to the statement list program shown in Figure 5-7. In general, you should consider the transitions detected by FP and FN to be transitions reflected in the RLO, not in the signal states of contacts. For example, a logic string can form an RLO that is not directly related to the signal state of a contact.
Reacting to a Negative Edge
Figure 5-8 shows a statement list that enables your program to react to a negative edge transition. An explanation follows the figure.
Statement List A I 1.0 FN M 1.0 = Q 4.0 OB1 Scan Cycle No.: Figure 5-8 Signal State Diagram I 1.0 M 1.0 Q 4.0 1 2 3 4 5 6 7 8 9 1 0 1 0 1 0
Programming a Reaction to a Negative Edge Transition
If the programmable logic controller detects a negative edge at contact I 1.0, it energizes the coil at Q 4.0 for one OB1 scan cycle. The programmable logic controller stores the result of the logic operation performed by the A instruction in edge memory bit M 1.0 and compares it to the RLO from the previous scan cycle (see Table 5-10). (In the example in Figure 5-8, the RLO of the statement A I 1.0 just happens to be the same as the signal state of input I 1.0. This will not be the case for every program.) If the current RLO is 0 and the RLO from the previous scan cycle stored in memory bit M 1.0 is 1, then the FN statement sets the RLO to 1.
5-17
The FN statement detects a negative edge at the contact (that is, the signal state of the RLO changed from 1 to 0). If there is no change in the RLO (current RLO and previous RLO stored in the edge memory bit are both equal to 0 or 1), then the FN statement resets the RLO to 0.
Table 5-10 OB1 Scan Cycle No. 1 2 3 4 5 6 7 8 9 Checking for Negative Edge Transition at Input I 1.0 Signal State at Input in Previous Cycle 0 (default value) 0 1 0 0 1 1 1 0 Signal State at Did the signal Input in state change Current Cycle from 1 to 0? 0 1 0 0 1 1 1 0 0 No No Yes No No No No Yes No Is the coil at Q 4.0 energized? No No Yes No No No No Yes No
Table 5-10 applies specifically to the statement list program shown in Figure 5-8. In general, you should consider the transitions detected by FP and FN to be transitions reflected in the RLO, not in the signal states of contacts. For example, a logic string can form an RLO that is not directly related to the signal state of a contact.
Addressed Bit
The location that the FP or FN instruction addresses is a bit. The instruction accesses the output through one of the following types of addresses:
S Address identifier (ID) and location within the memory area that is
indicated by the address identifier (see Tables 5-11 and 5-12)
S Bit transferred as a parameter (see Table 5-13)
5-18
Table 5-11 Address ID1 I2 Q3 M DBX DIX

1 2
Addresses of FP and FN: Direct and Indirect Addressing Maximum Address Range According to Addressing Type Direct Memory Indirect [DBD] [DID] [LD] [MD] Area-Internal Register Indirect [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0.0 to 8,191.7
0.0 to 65,535.7
See the Caution that follows this table. Because the operating system overwrites the process-image input table at the beginning of every scan cycle, the RLO stored by an FP or FN instruction that uses an input bit as its address is corrupted. See the Caution that follows this table. Using an output bit as the address of an FP or FN instruction is not recommended. If you want to influence an output, use the S, R, or = instruction.
Caution Corruption of stored result of logic operation. Can cause minor property damage. If you use an FP or FN instruction in your program, the memory bit that is the address of this instruction is used by FP or FN exclusively for its own storage purposes. Therefore you should not use any instruction that would change this bit. Otherwise you will corrupt the stored RLO. This caution applies to all the memory areas indicated in the address identifiers listed in Table 5-11.
Table 5-12
Addresses of FP and FN: Area-Crossing Register Indirect Addressing Address Range [AR1, P#byte.bit] [AR2, P#byte.bit] 0.0 to 8,191.7
Address Identifier1 I, Q, M, DBX, or DIX

1
The memory area is encoded in AR1 or AR2, respectively (see Section 3.6).
Table 5-13
Addresses of FP and FN: Bit Transferred as Parameter Address Parameter Format A bit transferred as parameter
5-19
5.6
Output of Boolean Logic String
Description
You can terminate a Boolean bit logic string by using one of the following three statement list instructions. Each of these instructions can influence a bit that represents the end of that string.
S Set (S): if the RLO was set to 1 in the previous command, S sets the
signal state of the contact or coil that the instruction addresses to 1;
S Reset (R): if the RLO was set to 1 in the previous command, R resets the
signal state of the contact or coil that the instruction addresses to 0;
S Assign (=): independently of the state of the RLO, the value of the RLO
is assigned to the location that the instruction addresses.
Terminating a Logic String
A logic string is terminated when the first-check bit (FC bit) is reset. When the value in the FC bit is 0, this indicates that the next instruction in the program is the first instruction of a new logic string (see Section 2.2, First Check). A Set (S), Reset (R), or Assign (=) instruction terminates a logic string by resetting the first-check bit (FC bit) to 0. (Conditional jump instructions also reset the FC bit to 0, see Sections 16.3 through 16.5.) Logic strings that are started with the instructions A(, AN(, O( etc. must be terminated with the ) instruction. Because these commands can also be used in the middle of a logic string, they represent an interruption in the string. That means that a new logic string is started before the old one is terminated. To continue the old logic string in the correct order after closing the commands to be carried out in brackets, the old FC bit (saved by opening the brackets) is restored again. You can therefore imagine program sections within brackets as a sort of intermediate calculation which, once completed, pick up the old thread again.
5-20
5.7
Set and Reset Instructions: S and R
Description
You can use the Set (S) instruction to set the signal state of an addressed bit to 1. (For information on the S instruction for setting an addressed counter to a specific value, see Section 7.2). You can use the Reset (R) instruction to reset the signal state of an addressed bit to 0. R can also reset an addressed timer or counter to 0 (see Sections 6.3 and 7.2). S and R terminate a logic string (see Section 5.6).
Setting a Bit
The S instruction sets the bit that it addresses to 1 if the result of logic operation from the previous statement is 1 and the master control relay (MCR) is energized (that is, its signal state is 1). If the MCR is not energized (its signal state is 0), the addressed bit is not changed. The S instruction terminates a logic string. Figure 5-9 illustrates how the S instruction holds the signal state of its addressed coil Q 4.0 at 1 until the R instruction changes the signal state to 0. The fact that the signal state of the addressed coil remains at 1 until an R instruction resets it to 0 indicates the static nature of the S instruction. In the relay logic diagram, if the normally open contact at input I 1.0 is activated (its signal state becomes 1), the contact closes. Power flows across the contact at I 1.0 and across the normally closed contact beneath it, energizing the coil at output Q 4.0 (the signal state of Q 4.0 becomes 1). When the coil is energized, the normally open contact at output Q 4.0 across from I 1.0 is closed. After that, regardless whether the contact at input I 1.0 is opened or closed, the coil at output Q 4.0 remains energized (at signal state 1). The coil keeps itself energized.
Statement List A I 1.0 S Q 4.0 A I 1.1 R Q 4.0
Relay Logic Diagram Power Rail I 1.0 Normally Open Contact 1 0 1 0 1 0 Normally Closed Contact Q 4.0 Coil Q 4.0 I 1.1
Signal State Diagrams I 1.0 I 1.1 Q 4.0
Figure 5-9
Setting and Resetting a Bit Statically
5-21
Resetting a Bit
The R instruction resets the bit that it addresses to 0 if the result of logic operation from the previous statement is 1 and the master control relay (MCR) is energized (that is, its signal state is 1). If the MCR is not energized (its signal state is 0), the addressed bit is not changed. The R instruction terminates a logic string. Figure 5-9 illustrates how the R instruction holds the signal state of its addressed coil Q 4.0 at 0 regardless of a change in signal state at the contact that triggered the reset (I 1.1). The fact that the signal state of the addressed coil remains at 0 until an S instruction resets it to 1 indicates the static nature of the R instruction. In the relay logic diagram, the coil at output Q 4.0 that was energized by the S instruction is de-energized (its signal state becomes 0) by closing the normally open contact at input I 1.1. Closing contact I 1.1 allows power to flow to the coil beneath it. This coil opens the normally closed contact above the coil at Q 4.0, interrupting the flow of power to the coil. Closing contact I 1.1 triggers the R instruction.
Referenced Address
The address that the S instruction references can be a bit. The address that the R instruction references can be a bit, a timer number, or a counter number. The addresses can be specified as follows:
indicated by the address identifier (see Tables 5-14 through 5-16)
S Bit, timer, or counter transferred as a parameter (see Table 5-17)

Table 5-14 Address ID I Q Addresses of S and R: Direct and Indirect Addressing Maximum Address Range According to Addressing Type Direct 0.0 to 65,535.7 Memory Indirect [DBD] [DID] [LD] [MD] [DBD] [DID] [LD] [MD] [DBD] [DID] [LD] [MD] Area-Internal Register Indirect [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0.0 to 8,191.7 0.0 to 8,191.7 0.0 to 8,191.7
0.0 to 255.7
DBX DIX L
0.0 to 65,535.7
5-22
Table 5-15
Addresses of S and R: Area-Crossing Register Indirect Addressing Maximum Address Range [AR1, P#byte.bit] [AR2, P#byte.bit] 0.0 to 8,191.7
Address Identifier1 I, Q, M, D, DBX, DIX, or L

1
The memory area is encoded in pointer bits 24, 25, and 26 (see Section 3.6).
Table 5-16
Addresses of R: Timers and Counters Maximum Address Range According to Addressing Type
Address Ident Identifier f er
Direct
Memory Indirect [DW] [DXW] [LW] [MW]
T1 C
0 to 65,535
0 to 65,534
The S instruction that sets an addressed bit to 1 does not apply to timers or counters. An S instruction used with a counter sets that counter to a specific value. Timers are started with instructions for specific types of timers (see Sections 6.2, 6.3 and 7.2).
Table 5-17
Address of S and R: Bit, Timer, or Counter Transferred as Parameter Address Parameter Format A bit, timer,1 or counter transferred as parameter

1
The S instruction does not apply to timers. Timers are started with instructions for specific types of timers (see Sections 6.2 and 6.3).
5-23
5.8
Assign Instruction (=)
Description
Each Boolean logic operation produces a result known as the result of logic operation (RLO). This RLO is either 1 or 0. In reference to contacts and coils, a 1 indicates power flow; a 0 indicates no power flow. You can use the Assign (=) instruction to copy the RLO from the previous statement in a logic string and assign the RLO as the signal state of the coil that the = instruction addresses. The = instruction terminates a logic string (see Section 5.6).
Setting or Resetting a Bit
The value that the = instruction assigns to the coil that it addresses can be 1 or 0, depending on the RLO of the statement that preceded the = statement. Unlike the instructions S and R, the nature of the = instruction is dynamic. It assigns the RLO as the signal state of the coil that the = instruction addresses. Figure 5-10 shows how this value changes as the RLO of the statement A I 1.0 changes. In Figure 5-10, the = instruction enables the input signal at the contact I 1.0 to energize or de-energize the coil represented by output Q 4.0 (that is, = sets or resets the bit represented by Q 4.0 by assigning the RLO of the previous statement).
Statement List A I 1.0 = Q 4.0
Relay Logic Diagram Power Rail I 1.1
Signal State Diagrams I 1.0
1 0 1 0 Q 4.0 Coil
Q 4.0
Figure 5-10
Setting and Resetting a Bit Dynamically
5-24
Addresses
The address that the = instruction addresses can be a bit. The instruction accesses the coil through one of the following addresses:
indicated by the address identifier (see Tables 5-18 and 5-19)
S Bit transferred as a parameter (see Table 5-20)

Table 5-18 Address ID I Q Addresses of =: Direct and Indirect Addressing Maximum Address Range According to Addressing Type Direct 0.0 to 65,535.7 Memory Indirect [DBD] [DID] [LD] [MD] [DBD] [DID] [LD] [MD] [DBD] [DID] [LD] [MD] Area-Internal Register Indirect [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0.0 to 8,191.7 0.0 to 8,191.7 0.0 to 8,191.7
0.0 to 65,535
DBX DIX L
0.0 to 65,535.7
Table 5-19
Addresses of =: Area-Crossing Register Indirect Addressing Maximum Range of Address Parameters [AR1, P#byte.bit] [AR2, P#byte.bit] 0.0 to 8,191.7
Address Identifier1 I, Q, M, DBX, DIX, or L

1
The memory area is encoded in the uppermost 8 bits of AR1 or AR2, respectively.
Table 5-20
Addresses of =: Bit Transferred as Parameter Address Parameter Format A bit transferred as parameter
5-25
5.9
Negating, Setting, Clearing, and Saving the RLO
Description
You can use one of the following instructions to change the result of logic operation (RLO) stored in the RLO bit in the status word of the programmable logic controller (see Section 5.8):
Mnemonic NOT SET CLR SAVE Instruction Negate RLO Set RLO Clear RLO Meaning Negating (inverting) the current RLO Setting the current RLO to 1 Resetting the current RLO to 0
Save RLO in BR Register Saving the current RLO to the bit of the status word
Because these instructions affect the RLO directly, they have no addresses.
Negating the RLO
You can use the Negate RLO (NOT) instruction in your program to negate (invert) the current RLO. If the current RLO is 0, NOT changes it to 1; if the current RLO is 1, NOT changes it to 0, provided the OR bit is not set. This instruction is useful for shortening your program, for example by changing from positive logic to negative logic (see the timer example in Section B.3).
Setting the RLO to 1
You can use the Set RLO (SET) instruction in your program if you need to set the RLO bit to 1 unconditionally. Figure 5-11 shows how the SET instruction works in a program.
Clearing the RLO to 0
You can use the Clear RLO (CLR) instruction in your program if you need to reset the RLO bit to 0 unconditionally. CLR also resets the FC, OR, and STA bits to 0. As a result, the logic string is ended. Figure 5-11 shows how the CLR instruction works in a program.
Saving the RLO
You can use the Save RLO in BR Register (SAVE) instruction in your program if you need to save the RLO for future use or if you want to influence the BR bit of the status word in the programmable logic controller, for example when you are programming function blocks (FBs) and functions (FCs) for ladder logic programming boxes.
Instruction BR NOT SET CLR SAVE x A1 Influence on the Bits of the Status Word A0 OV OS OR 0 0 STA 1 1 0 RLO x 1 0 FC 0 0
5-26
Applying SET and CLR
The program shown in Figure 5-11 illustrates an application of the SET and CLR instructions that set and reset a bit unconditionally.
Statement List SET = M 10.0 = M 15.1 = M 16.0 CLR = M 10.1 = M 10.2 Figure 5-11
Signal State 1 1 1
Result of Logic Operation (RLO) 1
0 0 0
Setting and Resetting a Bit Unconditionally Using SET and CLR
You could use the statements in the program shown in Figure 5-11 in a start-up organization block (OB). After you power up your programmable logic controller, it processes the start-up OB with all the instructions that it contains. After the programmable logic controller has executed all the instructions, the following memory bits have a specific signal state regardless of any conditions:
S The signal state of memory bits M 10.0, M 15.1, and M 16.0 is 1. S The signal state of memory bits M 10.1 and M 10.2 is 0.
5-27
5-28
Timer Instructions
Chapter Overview
Section 6.1 6.2 6.3 6.4 6.5 6.6 Overview Location of a Timer in Memory and Components of a Timer Loading, Starting, Resetting, and Enabling a Timer Timer Examples Address Locations and Ranges for Timer Instructions Choosing the Right Timer Description
6
Page 6-2 6-3 6-5 6-7 6-17 6-18
6-1
Timer Instructions
6.1
Overview
Definition
A timer is a function element of the STEP 7 programming language that implements and monitors timed sequences. The timer instructions enable your program to perform the following functions:
S Provide waiting times. For example, after an injection molding procedure,

the mold must remain closed for two seconds. Your program ensures that two seconds elapse before the part is released from the mold.
S Provide monitoring times. For example, the program monitors the speed
of a motor for 30 seconds after you press the start button.
S Generate pulses. For example, the program provides pulses that cause a
light to flash.
S Measure time. For example, the program can determine how long it takes
for a container to be filled.
Available Instructions
The statement list representation of the STEP 7 programming language provides the following timer instructions:
S Start timer as one of the following types:

Pulse (SP) Extended pulse (SE) On-delay (SD) Retentive on-delay (SS) Off-delay (SF)
S Reset timer (R) S Enable a timer to start (FR) S Load timer in one of the following formats:
Binary (L) Binary coded decimal (LC)
S Check the signal state of a timer and combine the result in a Boolean
logic operation (A, AN, O, ON, X, XN) (see Chapter 11). Figure 6-1 summarizes the instructions that use a timer word as address.
Start timer (SP, SE, SD, SS, SF) Enable timer (FR) Timer word Reset timer (R) Load timer (L, LC)
Check signal state of timer (A, O, X, AN, ON, XN) Figure 6-1
Instructions That Can Use a Timer Word as an Address
6-2
Timer Instructions
6.2
Location of a Timer in Memory and Components of a Timer
Area in Memory
Timers have an area reserved for them in the memory of your CPU. This memory area reserves one 16-bit word for each timer address. The statement list instruction set supports 256 timers. To find out how many timer words are available in your CPU, please refer to the CPU technical data. The following functions have access to the timer memory area:
S Timer instructions S Updating of timer words via clock timing. This function decrements a
given time value by one unit at the interval designated by the time base until the time value is equal to zero.
Time Value
Bits 0 through 9 of the timer word contain the time value in binary code. The time value specifies a number of units. Time updating decrements the time value by one unit at an interval designated by the time base. Decrementing continues until the time value is equal to zero. You can load a time value into the low word of accumulator 1 in binary, hexadecimal, or binary coded decimal (BCD) format. The time range is from 0 to 9,990 seconds. You can pre-load a time value using either of the following syntax formats:
S L W#16#wxyz
Where w = the time base (that is, the time interval or resolution) Where xyz = the time value in binary coded decimal format
S L S5T# aH_bbM_ccS_ddMS
Where a = hours, bb = minutes, cc = seconds, and dd = milliseconds The time base is selected automatically and the value is rounded to the next lower number with that time base. The maximum time value that you can enter is 9,990 seconds, or 2H_46M_30S.
6-3
Timer Instructions
Time Base
Bits 12 and 13 of the timer word contain the time base in binary code. The time base defines the interval at which the time value is decremented by one unit. The smallest time base is 10 ms; the largest is 10 s.
Table 6-1 Time Base and Its Binary Code Time Base 10 ms 100 ms 1s 10 s Binary Code for the Time Base 00 01 10 11
Because time values are stored with only one time interval, values that are not exact multiples of a time interval are truncated. Values that have too much resolution for the desired range are rounded down to achieve the desired range but not the desired resolution. Table 6-2 shows the possible resolutions and their corresponding ranges.
Table 6-2 Time Base Resolutions and Ranges Resolution 0.01 second 0.1 second 1 second 10 seconds Range 10MS to 9S_990MS 100MS to 1M_39S_900MS 1S to 16M_39S 10S to 2HR_46M_30S
Bit Configuration in Accumulator 1
When a timer is started, the contents of accumulator 1 are used as the time value. Bits 0 through 11 of accumulator 1 low hold the time value in binary coded decimal format (BCD format: each set of four bits contains the binary code for one decimal value). Bits 12 and 13 hold the time base in binary code (see Table 6-1). Figure 6-2 shows the contents of accumulator 1 low loaded with timer value 127 and a time base of 1 second. (See also Section 8.5.)
15... x x 1 0 0 0 0 1
...8 1
7... 0 0 1 2 0 0 1 7 1
...0 1
Time value in BCD (0 to 999) Time base 1 second Irrelevant: These bits are ignored when the timer is started. Figure 6-2 Contents of Accumulator 1 Low: Timer Value 127, Time Base 1 Second
6-4
Timer Instructions
6.3
Loading, Starting, Resetting, and Enabling a Timer

To start a timer in your statement list program, include three statements to trigger the following operations:
Description
S Check a signal state for 0 or 1 (for example, A I 2.1) S Load a time value and an accompanying time base (for example, L IW0) S Start a timer as one of the following types:
Pulse timer (SP, for example, SP T 1) Extended pulse timer (SE) On-delay timer (SD) Retentive on-delay (SS) Off-delay (SF) In your statement list program, a change in the result of logic operation (RLO) prior to a Start instruction statement starts a timer. A change in the RLO from 1 to 0 starts an offdelay timer (SF); a change from 0 to 1 starts any of the other timers. The programmed time and the Start timer statements must follow the logic operation directly that provides the condition for starting the timer. Section 6.4 provides examples of the five types of Start instructions for timers. Loading Loading a time value as an integer or as a BCD number is described in Sections 8.4 and 8.5. Because a timer runs down to zero from a set time, you must provide the timer with a starting time. When you start a timer in your program, the CPU looks in accumulator 1 for the starting time. The time range is from 0 to 9,990 seconds. Figure 6-3 provides an example for starting a pulse timer. A change in signal state from 0 to 1 at input I 2.1 starts the timer. Figure 6-3 refers to the following STL program:
Explanation I 2.1 S5T#00H02M23S00MS T 1 Check the signal state of input I 2.1. Load the starting time into accumulator 1. Start timer T1 as a pulse timer.
The Starting Time
Example of Starting a Timer
STL A L SP
Signal state diagram: I 2.1 Check I 2.1 for transition from 0 to 1. 1 0 1 0
Timer is started with the starting time given in accumulator 1. Figure 6-3 Starting a Pulse Timer
6-5
Timer Instructions
Resetting a Timer
You reset a timer by using the Reset (R) instruction. The CPU resets a timer when the result of logic operation is 1 immediately before the R instruction in your program. As long as the RLO that comes before an R instruction statement is 1, an A, O, or X instruction that checks the signal state of a timer produces a result of 0 and an AN, ON, or XN instruction that checks the signal state of a timer produces a result of 1. Resetting a timer stops the current timing function and resets the time value to 0.
Enabling a Timer for Restart
A change in the result of logic operation from 0 to 1 in front of an Enable instruction (FR) enables a timer. This change in signal state is always necessary to enable a timer. The CPU executes the FR instruction only on a positive signal edge. Timer enable is not required to start a timer, nor is it required for normal timer operation. An enable is used only to retrigger a running timer, that is, to restart the timer. This restarting is possible only when the start operation continues to be processed with an RLO of 1.
6-6
Timer Instructions
6.4
Timer Examples
Introduction
Statement list programming offers five types of timers to meet your automation needs. An example for each type is provided below.
Pulse Timer: SP
Figures 6-4 and 6-5 provide examples of a pulse timer. The numbers in squares in the figures are keyed to explanations that follow Figure 6-4. The figures refer to the following STL program:
STL A FR A L SP A R A = L T LC T I 2.0 T 1 I 2.1 S5T#0H2M23S0MS T 1 I 2.2 T 1 T 1 Q 4.0 T 1 MW10 T 1 MW12
Explanation Enable timer T 1.
Start timer T 1 as a pulse timer. Reset timer T 1. Check the signal state of timer T 1.
Load timer T 1.
RLO at Enable input RLO at Start input RLO at Reset input Timer response Check signal state of timer output. Load timer: L, LC
I 2.0 I 2.1 I 2.2
t Q 4.0
t = programmed start time Figure 6-4 Pulse Timer Example, Part 1
6-7
Timer Instructions
The following list describes the elements of Figures 6-4 and 6-5: A change in the RLO from 0 to 1 at the Start input starts the timer. The programmed time t then elapses. When an RLO of 0 is applied to the Start input, the timer is reset. Checking the signal state of output Q 4.0 of the timer results in a signal state of 1 for the entire duration of the timer operation. If an RLO of 1 is applied to the Reset input, the timer is reset. As long as a signal state of 1 remains at the Start input, a change in the RLO from 1 to 0 at the Reset input has no influence on the timer. A change in the RLO from 0 to 1 at the Start input with the Reset signal applied causes the timer to start momentarily but to reset immediately because of the Reset statement that follows directly in the program (shown as a pulse line in the timing diagram in Figure 6-4). No checking result is obtained for this pulse, provided that the sequence of writing the statements as they appear above is observed. A change in the RLO from 0 to 1 at the Enable input while the timer is running restarts the timer. The time that is programmed is used as the current time for the restart. A change in the RLO from 1 to 0 at the Enable input has no effect. If the RLO changes from 0 to 1 at the Enable input while the timer is not running and there is still an RLO of 1 at the Start input, the timer will also be started as a pulse with the time programmed. A change in the RLO from 0 to 1 at the Enable input while there is still an RLO of 0 at the Start input has no effect on the timer.
RLO at Enable input RLO at Start input RLO at Reset input Timer response Check signal state of timer output. Load timer: L, LC t = programmed start time Figure 6-5 Pulse Timer Example, Part 2 t Q 4.0 t I 2.0 I 2.1 I 2.2

6-8
Timer Instructions
Extended Pulse Timer: SE
Figures 6-6 and 6-7 provide examples of an extended pulse timer. The numbers in squares in the figures are keyed to explanations that follow Figure 6-6. The figures refer to the following STL program:
STL A FR A L SE A R A = L T LC T I 2.0 T 1 I 2.1 S5T#0H2M23S0MS T 1 I 2.2 T 1 T 1 Q 4.0 T 1 MW10 T 1 MW12
Start timer T 1 as an extended pulse timer. Reset timer T 1. Check the signal state of timer T 1. Load timer T 1 (binary coded).
Load timer T 1 (BCD coded).
RLO at Enable input I 2.0 RLO at Start input RLO at Reset input Timer response Check signal state of timer output Q 4.0 Load timer: L, LC t = programmed start time Figure 6-6 Extended Pulse Timer Example, Part 1 t I 2.1 I 2.2
6-9
Timer Instructions
The following list describes the elements of Figures 6-6 and 6-7: A change in the RLO from 0 to 1 at the Start input starts the timer. The programmed time t then elapses, regardless of a change in the RLO from 1 to 0 at the Start input. If the RLO changes from 0 to 1 before the time has elapsed, the timer is retriggered with the time that was programmed originally. Checking the signal state of the timer output produces a result of 1 for the entire duration of the timer operation. If an RLO of 1 is applied to the Reset input, the timer is reset. As long as a signal state of 1 remains at the Start input, a change in the RLO from 1 to 0 at the Reset input has no effect on the timer. A change in the RLO from 0 to 1 at the Start input with the Reset signal applied causes the timer to start momentarily but to reset immediately because of the Reset statement that follows directly in the program (shown as a pulse line in the timing diagram in Figure 6-6). No checking result is obtained for this pulse, provided that the sequence of writing the statements as they appear above is observed. A change in the RLO from 0 to 1 at the Enable input while the timer is running restarts the timer. The time that is programmed is used as the current time for the restart. A change in the RLO from 1 to 0 at the Enable input has no effect. If the RLO changes from 0 to 1 at the Enable input while the timer is not running and there is still an RLO of 1 at the Start input, the timer will also be started as a pulse with the time programmed. A change in the RLO from 0 to 1 at the Enable input while there is still an RLO of 0 at the Start input has no effect on the timer.
I 2.0 I 2.1 I 2.2

RLO at Enable input RLO at Start input RLO at Reset input Timer response Check signal state of timer output. Load timer: L, LC
t Q 4.0
t = programmed start time Figure 6-7 Extended Pulse Timer Example, Part 2
6-10
Timer Instructions
On-Delay Timer: SD
Figures 6-8 and 6-9 provide examples of an on-delay timer. The numbers in squares in the figures are keyed to explanations that follow Figure 6-8. The figures refer to the following STL program:
STL A FR A L SD A R A = L T LC T I 2.0 T 1 I 2.1 S5T#0H2M23S0MS T 1 I 2.2 T 1 T 1 Q 4.0 T 1 MW10 T 1 MW12
Start timer T 1 as an on-delay timer. Reset timer T 1. Check the signal state of timer T 1.
Load timer T 1.
RLO at Enable input I 2.0 RLO at Start input RLO at Reset input Timer response t Check signal state of timer output Q 4.0 Load Timer: L, LC t = programmed start time Figure 6-8 On-Delay Timer Example, Part 1 I 2.1 I 2.2 t
6-11
Timer Instructions
The following list describes the elements of Figures 6-8 and 6-9: A change in the RLO from 0 to 1 at the Start input starts the timer. The programmed time t then elapses. When an RLO of 0 is applied to the Start input, the timer is reset. Checking the signal state of output Q 4.0 of the timer results in a signal state of 1 when the time has elapsed and the Start input is 1. If an RLO of 1 is applied to the Reset input, the timer is reset. As long as a signal state of 1 remains at the Start input, a change in the RLO from 1 to 0 at the Reset input has no effect on the timer. A change in the RLO from 0 to 1 at the Start input with the Reset signal applied causes the timer to start momentarily but to reset immediately because of the Reset statement that follows directly in the program (shown as a pulse line in the timing diagram in Figure 6-8). No checking result is obtained for this pulse, provided that the sequence of writing the statements as they appear above is observed. A change in the RLO from 0 to 1 at the Enable input while the timer is running restarts the timer. The time that is programmed is used as the current time for the restart. A change in the RLO from 1 to 0 at the Enable input has no effect. If the RLO changes from 0 to 1 at the Enable input following normal operation of the timer, the timer is not affected A change in the RLO from 0 to 1 at the Enable input after the timer was reset and while there is still an RLO of 1 at the Start input starts the timer. The time that is programmed is used as the current time.
I 2.0 I 2.1 I 2.2

RLO at Enable input RLO at Start input RLO at Reset input Timer response
Check signal state Q 4.0 of timer output. Load timer: L, LC t = programmed start time Figure 6-9
On-Delay Timer Example, Part 2
6-12
Timer Instructions
Retentive On-Delay Timer: SS
Figures 6-10 and 6-11 provide examples of a retentive on-delay timer. The numbers in squares in the figures are keyed to explanations that follow Figure 6-10. The figures refer to the following STL program:
STL A FR A L SS A R A = L T LC T I 2.0 T 1 I 2.1 S5T#0H2M23S0MS T 1 I 2.2 T 1 T 1 Q 4.0 T 1 MW10 T 1 MW12
Start timer T 1 as a retentive on-delay timer. Reset timer T 1. Check the signal state of timer T 1.
Load timer T 1.
RLO at Enable input I 2.0 RLO at Start input RLO at Reset input Timer response t Check signal state of timer output Q 4.0 Load timer: L, LC t = programmed start time Figure 6-10 Retentive On-Delay Timer Example, Part 1 I 2.1 I 2.2
The following list describes the elements of Figures 6-10 and 6-11: A change in the RLO from 0 to 1 at the Start input starts the timer. The programmed time t then elapses regardless of a change in the RLO from 1 to 0 at the Start input. Checking the signal state of the timer output results in 1 if the time has elapsed.
6-13
Timer Instructions

The result of checking the signal state of output Q 4.0 changes to 0 only when the RLO at the Reset input is 1. If an RLO of 1 is applied to the Reset input, the timer is reset. As long as a signal state of 1 remains at the Start input, a change in the RLO from 1 to 0 at the Reset input has no influence on the timer. A change in the RLO from 0 to 1 at the Start input with the Reset signal applied causes the timer to start momentarily but to reset immediately because of the Reset statement that follows directly in the program (shown as a pulse line in the timing diagram in Figure 6-10). No checking result is obtained for this pulse, provided that the sequence of writing the statements as they appear above is observed. When the RLO at the Enable input changes from 0 to 1 while the timer is running and the RLO at the Start input of the timer is 1, the timer is restarted. The time that is programmed is used as the current time for the restart. A change in the RLO from 1 to 0 at the Enable input has no effect on the timer. The timer is not affected when the RLO at the Enable input changes from 0 to 1 following normal operation of the timer. When the RLO at the Enable input changes from 0 to 1 while the timer is running and the RLO at the Start input of the timer is 0, the timer is not affected. If the RLO at the Enable input changes from 0 to 1 when the timer is reset and the RLO at the Start input is still 1, the timer is restarted. The time that is programmed is used as the current time for the restart.
I 2.0 I 2.1
I 2.2
Retentive On-Delay Timer Example, Part 2
6-14
Timer Instructions
Off-Delay Timer: SF
Figures 6-12 and 6-13 provide examples of an off-delay timer. The numbers in squares in the figures are keyed to explanations that follow Figure 6-12. The figures refer to the following STL program:
STL A FR A L SF A R A = L T LC T I 2.0 T 1 I 2.1 S5T#0H2M23S0MS T 1 I 2.2 T 1 T 1 Q 4.0 T 1 MW10 T 1 MW12
Start timer T 1 as an off-delay timer. Reset timer T 1. Check the signal state of timer T 1.
Load timer T 1.
I 2.0 I 2.1

I 2.2 t t
Off-Delay Timer Example, Part 1
6-15
Timer Instructions
The following list describes the elements of Figures 6-12 and 6-13: A change in the RLO from 0 to 1 at the Start input causes a change from 0 to 1 at output Q 4.0 of the timer. A change in the RLO from 1 to 0 at the Start input starts the timer. The programmed time t then elapses. If an RLO of 1 reappears at the Start input, the timer is reset. Checking the signal state of output Q 4.0 of the timer results in a signal state of 1 if the RLO at the Start input is 1 and if the time has not yet elapsed. If an RLO of 1 is applied to the Reset input, the timer is reset. Checking the signal state of the timer then results in 0. A change in RLO from 1 to 0 at the Reset input has no influence on the timer. A 1 applied to the Reset input while the timer is not running has no effect on the timer. A change in the RLO from 1 to 0 at the Start input while the Reset signal is applied causes the timer to start momentarily but to reset immediately because of the Reset statement that follows directly in the program (shown as a pulse line in the timing diagram in Figure 6-12). Checking the signal state of the timer then results in 0. The timer is not affected if the RLO at the Enable input changes from 0 to 1 while the timer is not running. A change in the RLO from 1 to 0 also has no effect on the timer. If the RLO at the Enable input changes from 0 to 1 while the timer is running, the timer is restarted. The time that is programmed is used as the current time for the restart.

RLO at Enable input RLO at Start input RLO at Reset input Timer response Check signal state of timer output. Load timer: L, LC t = programmed start time Figure 6-13 Off-Delay Timer Example, Part 2 I 2.0 I 2.1 I 2.2
t Q 4.0
6-16
Timer Instructions
6.5
Address Locations and Ranges for Timer Instructions

Tables 6-3 and 6-4 show the address types, address locations, and address ranges for the timer instructions.
Table 6-3 Address Locations, Ranges, and Types for Timer Instructions Address Range According to Addressing Type Direct [DBW] [DIW] [LW] [MW] Memory Indirect
0 to 255
0 to 65,534
Table 6-4 Address Symbolic name
Timer Address transferred as Parameter Address Parameter Format Time transferred as parameter
6-17
Timer Instructions
6.6
Choosing the Right Timer

Figure 6-14 provides an overview of the five types of timers described in Section 6.4. This overview is intended to help you choose the right timer for your timing job.
Input signal
I 2.1
Output signal (Pulse timer)
Q 4.0
SP: t The maximum time that the output signal remains at 1 is the same as the programmed time value t. The output signal stays at 1 for a shorter period if the input signal changes to 0.
Output signal (Extended pulse timer)
Q 4.0
SE: t The output signal remains at 1 for the programmed length of time, regardless of how long the input signal stays at 1.
Output signal (On-delay timer)
Q 4.0
SD: t The output signal changes from 0 to 1 only when the programmed time has elapsed and the input signal is still 1.
Output signal (Retentive on-delay timer)
Q 4.0
SS: t The output signal changes from 0 to 1 only when the programmed time has elapsed, regardless of how long the input signal stays at 1.
Output signal (Off-delay timer)
Q 4.0
SF: t The output signal changes from 0 to 1 when the input signal changes from 0 to 1. The output signal remains at 1 for the programmed length of time. The time is started when the input signal changes from 1 to 0.
Figure 6-14
Choosing the Right Timer
6-18
Counter Instructions
Chapter Overview
Section 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Overview Setting, Resetting, and Enabling a Counter Couting Up and Counting Down Loading a Count Value as Integer Loading a Count Value in Binary Coded Decimal Format Counter Example Address Locations and Ranges for Counter Instructions Description
7
Page 7-2 7-3 7-5 7-6 7-7 7-8 7-10
7-1
7.1
Overview
Definition
A counter is a function element of the STEP 7 programming language that counts. Counters have an area reserved for them in the memory of your CPU. This memory area reserves one 16-bit word for each counter. The statement list instruction set supports 256 counters. To find out how many counters are available in your CPU, please refer to the CPU technical data. Counter instructions are the only functions with access to the memory area reserved for the counter.
The statement list representation of the STEP 7 programming language provides the following counter instructions:
S Set (S) S Reset (R) S Count up (CU) S Count down (CD) S Enable counter (FR) S Load counter in one of the following formats:
Binary (L) Binary coded decimal (LC)
S Check the signal state of a counter and combine the result in a Boolean
logic operation (A, AN, O, ON, X, XN). A signal state check with an A, O or X instruction will have the result 1, when the value of a counter is greater than 0. A signal state check with an A, O or X instruction will have the result 0, when the value of the counter is equal to 0. Figure 7-1 summarizes the instructions that use a counter word as their address.
Count Up (CU)
Reset a counter (R)
Set a counter (S)
Count Down (CD)
Counter word
Enable a counter (FR)
Check the signal state of a counter (A, AN, O, ON, X, XN) Figure 7-1
Load a count value (L, LC)
Instructions That Can Use a Counter Word as an Address
7-2
7.2
Setting, Resetting, and Enabling a Counter
Description
To set a counter in your statement list program, include three statements to trigger the following operations:
S Check a signal state for 0 or 1 (for example, A I 2.3) S Load a count value (for example, L C# 3) into the low word of
accumulator 1
S Set a counter with the count value you loaded (for example, S C 1). This
operation moves the count value from accumulator 1 to the counter word. In your statement list program, a change in the result of logic operation (RLO) from 0 to 1 prior to a Set (S) instruction statement sets a counter to the programmed count value. The programmed count value and the Set statements must follow the logic operation directly that provides the condition for setting the counter.
The Starting Count
You set a counter to a specific value by loading that value into the low word of accumulator 1 and, immediately thereafter, setting that counter. When you set a counter in your program, the CPU looks in accumulator 1 for the count value. Then the CPU transfers the count value from the accumulator to the counter word that you specified in your set statement (for example, S C 1). The range of the count value is 0 to 999.
Example of Setting a Counter
Figure 7-2 provides an example for setting a counter. A change in signal state from 0 to 1 at input I 2.3 sets the counter. The figure refers to the following program:
STL A L S I 2.3 C# 3 C 1
Explanation Check signal state of input I 2.3. If the signal state is 1, load count value 3 into accumulator 1. Set counter C 1 to a count value of 3. This operation moves the count value of 3 from the accumulator into counter word 1.
Signal state diagram: 1 0 Check I 2.3 for transition 1 0 from 0 to 1. I 2.3 Counter is set to the value given in the load instruction. Figure 7-2 Setting a Counter
7-3
Resetting a Counter
You reset a counter by using the Reset (R) instruction. The CPU resets a counter when the result of logic operation is 1 immediately before the R instruction in your program. As long as the RLO that comes before an R instruction statement is 1, an A, O, or X instruction that checks the signal state of a counter produces a result of 0 and an AN, ON, or XN instruction that checks the signal state of a counter produces a result of 1. When your program resets a counter, it clears the counter, that is, it resets it to a value of 0. If a counter is to be reset by a static signal at the Reset (R) and independently of the RLO of the other counter instructions, you need to write the Reset statement immediately after the Set, Count Up, or Count Down statement (see Section 7.3) and before the signal check or load operation. Programming for counters should adhere to the following sequence (see also the programming example in Section 7.6): 1. Count up 2. Count down 3. Set counter 4. Reset counter 5. Check signal state of counter 6. Load count value (Read count value)
Enabling a Counter for Restart
A change in the result of logic operation of the Enable instruction (FR) from 0 to 1 enables a counter. The CPU executes the FR instruction only on a positive signal edge. A counter enable is not required to set a counter, nor is it required for normal counting. An enable is only used to set a counter, or to count up or down, if a positive edge (transition from 0 to 1) in front of the corresponding count statement is needed, and if the RLO bit in front of the corresponding statement has a signal state of 1.
7-4
7.3
Couting Up and Counting Down
Description of Counting Up
In your statement list program, a change in the result of logic operation from 0 to 1 prior to a Count Up (CU) instruction statement increments the counter. Each time a positive edge change occurs in the RLO directly before a Count Up instruction, the count is incremented by one unit. When the count reaches its upper limit of 999, incrementing stops and any further change in the signal state at the Count Up input have no effect. No provisions are made for overflow (OV).
STL A I 0.1 CU C1
Explanation If there is a positive edge change at input I 0.1, counter C 1 is incremented by 1.
Description of Counting Down
In your statement list program, a change in the result of logic operation from 0 to 1 prior to a Count Down (CD) instruction statement decrements the counter. Each time a positive edge change occurs in the RLO directly before a Count Down instruction, the count is decremented by one unit. When the count reaches its lower limit of 0, decrementing stops and any further change in the signal state at the Count Down input have no effect. The counter does not count with negative values.
STL A I 0.2 CD C1
Explanation If there is a positive edge change at input I 0.2, counter C 1 is decremented by 1.
7-5
7.4
Loading a Count Value as Integer
Description
A count value is stored in a counter word in binary code. You can use the following instruction to read the binary count value out of a counter word and load it into the low word of accumulator 1: L <counter word> This type of loading is referred to as loading a counter value directly.
STL L C 1
Explanation Load accumulator 1 low directly with the count value of counter C 1 in binary format.
15 Counter word for C 1 Accumulator 1 low Figure 7-3 XXXXXX 15 000000
10 9
Count Value
10
Loading a Count Value into Accumulator 1 Using the L Instruction
You can use the value contained in the accumulator as a result of the L operation for further processing. You cannot transfer a value from the accumulator to the counter word. If you want to start a counter with a specific count value, you need to use the appropriate Set counter statement.
7-6
7.5
Loading a Count Value in Binary Coded Decimal Format
Description
A count value is stored in a counter word in binary code. You can use the following instruction to read the count value in binary coded decimal (BCD) format out of a counter word and load it into the low word of accumulator 1: LC <counter word> This type of loading is referred to as loading a count value in BCD format. The value contained in the low word of accumulator 1 as a result of the LC operation has the same format as is needed to set a counter.
STL LC C 1
Explanation Load accumulator 1 low directly with the count value of counter C 1 in binary coded decimal format.
Counter word for C 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count value Accumulator 1 low 15 14 13 12 0 0 0 0 102 (Hundreds) 101 (Tens) 100 (Ones) 11 10 9 8 7 Binary to BCD 6 5 4 3 2 1 0
Count in BCD format Figure 7-4 Loading a Count Value into Accumulator 1 Using the LC Instruction
The value contained in the accumulator as a result of the LC operation can be used for further processing, such as transferring the value to the outputs for a display.
7-7
7.6
Counter Example
Figure 7-5 provides an example of counting up, counting down, setting and resetting a counter, checking the signal state of a counter, and loading a count value. The example follows the programming sequence recommended in Section 7.2. The numbers in squares in the figure are keyed to explanations that follow the figure. Figure 7-5 refers to the statement list program that follows the explanatory list.
I 2.0 Enable I 2.1 Count Up I 2.2 Count Down I 2.3 Set I 2.4 Reset
Counter Response
Check signal state of counter output Q 4.0
MW10 Load MW12
0
Figure 7-5
Example of Counter Instructions
7-8
The following list describes the elements of Figure 7-5: A change in the RLO from 0 to 1 at the Set input sets the counter to a count value of 3. A transition from 1 to 0 at the Set input has no effect on the counter. A change in the RLO from 0 to 1 at the Count Down input decreases the counter by one. A transition from 1 to 0 at the Count Down input has no effect on the counter. The result of the signal state check statement A C 1 is 0 when the count value is 0. A change in the RLO from 0 to 1 at the Count Up input increases the counter by one. A transition from 1 to 0 at the Count Up input has no effect on the counter. If an RLO of 1 is applied at the Reset input, the counter is reset. Checking the signal state produces a result of 0. A change in the RLO from 1 to 0 at the Reset input has no effect on the counter. A change in the RLO from 0 to 1 at the Count Up input while the Reset signal is applied causes the counter to increase momentarily but to reset immediately because of the Reset statement that follows directly in the program. (The momentary increase is indicated by a pulse line in the timing diagram in Figure 7-5). Checking the signal state then produces a result of 0. A change in the RLO from 0 to 1 at the Enable input with Count Up and Count Down applied causes the counter to increase momentarily but then decrease immediately because of the Count Down statement that follows directly in the program. (The momentary increase is indicated by a pulse line in the timing diagram in Figure 7-5). A transition from 1 to 0 at the Enable input has no effect on the counter.

STL A FR A CU A CD A L S A R A = L T LC T I 2.0 C 1 I 2.1 C 1 I 2.2 C 1 I 2.3 C# 3 C 1 I 2.4 C 1 C 1 Q 4.0 C 1 MW10 C 1 MW12
Explanation Enable counter C 1. Count up (increment by 1). Count down (decrement by 1).
Set counter C 1. Reset counter C. Check the signal state of counter C 1. Load counter C 1 (binary coded)
Load counter C 1 (BCD coded).
7-9
7.7
Address Locations and Ranges for Counter Instructions

Table 7-1 shows the address types, address locations, and address ranges for the counter instructions.
Table 7-1 Address Locations, Ranges, and Types for Counter Instructions Address Range according to Addressing Type Direct [DBW] [DIW] [LW] [MW] Memory Indirect
0 to 65,535
0 to 65,534
7-10
Load and Transfer Instructions

Chapter Overview
Section 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Overview Loading and Transferring Reading the Status Word or Transferring to the Status Word Loading Times and Counts as Integers Loading Times and Counts in Binary Coded Decimal Format Loading and Transferring between Address Registers Loading Data Block Information Description
8
Page 8-2 8-3 8-6 8-7 8-9 8-11 8-12
8-1
8.1
Overview
The Load (L) and Transfer (T) instructions enable you to program an interchange of information between input or output modules and memory areas, or between memory areas. The CPU executes these instructions in each scan cycle as unconditional instructions, that is, they are not affected by the result of logic operation of a statement.
Definition
Information Interchange
The L and T instructions enable an interchange of information between the following modules or memory areas:
S Input and output modules and the following areas of memory:

Process-image input and output tables Bit memory Timers and counters Data areas
S Process-image input and output tables and the following areas of

memory: Bit memory Timers and counters Data areas
S Timers and counters and the following areas of memory:

Process-image input and output tables Bit memory Data areas
Method of Interchange
The L and T instructions provide information exchange via the accumulator. An L instruction statement writes (loads) the contents of its addressed source location into accumulator 1, shifting any information already contained there to accumulator 2. The old contents of accumulator 2 is overwritten. A T instruction statement copies the contents of accumulator 1 and writes them into the memory of its addressed destination. Because the T instruction only copies the information that is in accumulator 1, this information is still available to other instructions. The L and T instructions can handle information in bytes (8 bits), words (16 bits), and double words (32 bits). The accumulator has a total of 32 bits. Data with fewer than 32 bits is right justified in the accumulator. The remaining bits of the accumulator are padded with zeros.
LOAD Source
31 16 15 0
TRANSFER Destination
Accumulator 1
8-2
8.2
Loading and Transferring

You can use the Load (L) or Transfer (T) instruction to transfer information to or from accumulator 1 in chunks of the following sizes: S Byte (B, 8 bits) S Word (W, 16 bits) S Double word (D, 32 bits) A byte is loaded into the low byte of the low word of accumulator 1. A word is loaded into the low word of accumulator 1. Unused bytes are reset to 0 when loading into the accumulator.
Description
The L instruction can address constants of 8, 16, and 32 bits as well as ASCII characters. This type of addressing is called immediate addressing (see Section 3.1 and Table 8-1).
Addresses of L Instructions: Immediate Addressing Example L L +5 B#(1,10) Explanation Loads a 16-bit integer constant into accumulator 1. Loads a contact as 2 bytes into accumulator 1. (In this example, the 10 goes into the low byte of the low word of accumulator 1; the 1 goes into the high byte of the low word of accumulator 1, see Figure 2-4.) Loads a contact as 4 bytes into accumulator 1. (In this example, the 4 and the 5 go into the low and high byte of the low word of accumulator 1, respectively; the 10 and the 1 go into the low and high byte of the high word of accumulator 1, respectively, see Figure 2-4.) Loads a 32-bit integer constant into accumulator 1. Loads an 8-bit hexadecimal constant into accumulator 1. Loads a 16-bit hexadecimal constant into accumulator 1. Loads a 32-bit hexadecimal constant into accumulator 1. Loads a 16-bit binary constant into accumulator 1. Loads a 32-bit binary constant into accumulator 1. Loads 2 characters into accumulator 1. Loads 4 characters into accumulator 1. Loads a 16-bit count constant into accumulator 1. Loads a 16-bit S5TIME constant into accumulator 1. Loads a 32-bit IEEE floating point into accumulator 1. Loads a 32-bit pointer into accumulator 1. Loads a 32-bit pointer to a local variable (Start) into accumulator 1 Loads a pointer to a specified parameter in accumulator 1. (This instruction loads the relative address offset of the specified parameter. In order to determine the absolute offset in the instance data block of a function block with multiple instances, the contents of the AR2 register must be added to this value.)
Table 8-1 Address ".. B#(..,..)
B#(1,10,5,4)
L#.. 16#..
L L L L L L L L L L L L L L
L#+5 B#16#EF W#16#FAFB DW#16#1FFE_1ABC 2#1111_0000_1111_0000 2#1111_0000_1111_0000_ 1111_0000_1111_0000 AB ABCD C#1000 S5TIME#2S 1.0E+5 P#I1.0 P##Start P#ANNA
2#..
.. C#.. S5TIME#.. .. P#..
8-3
Table 8-1 Address D#.. T#.. TOD#..
, continuedAddresses of L Instructions: Immediate Addressing, continued Example L L L D#1994-3-15 T#0D_1H_1M_0S_0MS TOD#1:10:3.3 Explanation Loads a 16-bit date into accumulator 1. Loads a 32-bit time value into accumulator 1. Loads a 32-bit time-of-day value into accumulator 1.
Direct and Indirect Addressing
The L and T instructions can address a byte (B), word (W), or double word (D) in the following memory areas using direct and indirect addressing (see also Sections 3.2, 3.3, and 3.5):
S Process-image input and output (address identifiers IB, IW, I, QB, QW,
QD)
S External inputs and outputs (address identifiers PIB, PIW, PID, PQB,
PQW, PQD). External inputs can be addresses of L instructions only; external outputs can be addresses of T instructions only.
S Bit memory (address identifiers MB, MW, MD) S Data block (address identifiers DBB, DBW, DBD, DIB, DIW, DID) S Local data (temporary local data, address identifiers LB, LW, LD)
Table 8-2 lists the addresses for L and T instructions that use direct and indirect addressing.
Table 8-2 Address ID IB IW ID Addresses of L and T Instructions: Direct and Indirect Addressing Maximum Address Range according to Addressing Type Direct 0 to 65,535 0 to 65,534 0 to 65,532 Memory Indirect Area-Internal Register Indirect
QB QW QD PIB PIW PID (L only) PQB PQW PQD (T only)
0 to 65,535 0 to 65,534 0 to 65,532 0 to 65,535 0 to 65,534 0 to 65,532
[DBD] [DID] [LD] [MD]
[AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0 to 8,191
0 to 65,535 0 to 65,534 0 to 65,532
[DBD] [DID] [LD] [MD]
[AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0 to 8,191
8-4
Table 8-2 Address ID MB MW MD DBB DBW DBD DIB DIW DID LB LW LD
Addresses of L and T Instructions: Direct and Indirect Addressing Direct 0 to 255 0 to 254 0 to 252 0 to 65,535 0 to 65,534 0 to 65,532 0 to 65,535 0 to 65,534 0 to 65,532 0 to 65,535 0 to 65,534 0 to 65,532 [DBD] [DID] [LD] [MD] [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0 to 8,191 Memory Indirect [DBD] [DID] [LD] [MD] Area-Internal Register Indirect [AR1, P#byte.bit] 0 to 65,532 [AR2, P#byte.bit] 0 to 8,191
Area-Crossing Indirect Addressing
The L and T instructions can address a byte (B), word (W), or double word (D) using area-crossing register indirect addressing (see Section 3.6).
Table 8-3 Addresses of L and T Instructions: Area-Crossing Register Indirect Addressing Address Identifier1 B (byte), W (word), D (double word)
1
Address Range [AR1, P#byte.bit] [AR2, P#byte.bit] 0 to 8,191
The memory area is encoded in bits 24 through 31 of AR1 or AR2 (see Section 3.6).
Byte, Word, or Double Word as Parameter
For their address, the L and T instructions can also use a byte, word, or double word that is transferred as parameter.
Table 8-4 Address of L and T Instructions: Byte, Word, or Double Word Transferred as Parameter Address Parameter Format A byte, word, or double word transferred as parameter
8-5
8.3
Reading the Status Word or Transferring to the Status Word
Loading the Status Word
You can use the Load (L) instruction to load bits 0 through 8 of the status word (see Figure 8-1) into accumulator 1. Bits 9 through 31 of accumulator 1 are reset to 0. The instruction statement is shown in the example that follows Figure 8-1. Note For the S7-300 series CPUs, the statement L STW does not load the FC, STA, and OR bits of the status word. Only bits 1, 4, 5, 6, 7, and 8 are loaded into the corresponding bit positions of the low word of accumulator 1.
215...
...29
28
BR
27
26
25
OV
24
OS
23
OR
22
STA
21
20
CC 1 CC 0
RLO FC
Figure 8-1
Structure of the Status Word
STL L STW
Explanation Loads bits 0 to 8 of the status word into the low word of accumulator 1.
Transferring to the Status Word
You can use the Transfer (T) instruction to transfer the contents of accumulator 1 to the status word (see Figure 8-1). The instruction statement is shown in the following program excerpt.
STL T STW
Explanation Transfers the contents of accumulator 1 to the status word.
8-6
8.4
Loading Times and Counts as Integers
Loading a Time
A time value is stored in a timer word in binary code. You can use the following Load (L) instruction to read the binary time value out of a timer word and load it into the low word of accumulator 1: L <timer word> This type of loading is referred to as loading of a time value directly. The time value in the timer word is decremented from its starting value to 0 during the processing of the user program in the CPU. When you use the L instruction with a timer word as address, you get a value that lies between the starting time of the timer word and 0. The time that elapses from the moment a timer starts is calculated from the difference of the start time and the time being read currently.
STL L T 1
Explanation Load accumulator 1 low directly with the time of timer T 1 in binary code.
15 Timer word
10 9
Time
15 Accumulator 1 low 0000
10 9 00
Figure 8-2
Loading a Time Value into Accumulator 1 Using the L Instruction
You can use the value contained in the accumulator as a result of the L operation for further processing. You cannot transfer a value from the accumulator to the timer word. Note When you use the L instruction to read out a timer word, you get a value between 0 and 999. You do not get the time base that was loaded with the time value.
8-7
Loading a Count
A count value is stored in a counter word in binary code. You can use the following Load (L) instruction to read the binary count value out of a counter word and load it into the low word of accumulator 1: L <counter word> This type of loading is referred to as loading a counter value directly.
STL L C 1
Explanation Load accumulator 1 low directly with the count value of counter C 1 in binary format.
15 Counter word for C 1 Accumulator 1 low Figure 8-3 XXXXXX 15 000000
10 9
Count Value
10
You can use the value contained in the accumulator as a result of the L operation for further processing. You cannot transfer a value from the accumulator to the counter word. If you want to start a counter with a specific count value, you need to use the appropriate Set counter statement (see Section 7.2).
8-8
8.5
Loading Times and Counts in Binary Coded Decimal Format
Loading a Time in BCD Format
A time value is stored in a timer word in binary code. You can use the following Load (L) instruction to read the time value in binary coded decimal (BCD) format out of a timer word and load it into the low word of accumulator 1: LC <timer word> In addition to the time value, the time base is also loaded. The value which appears in the low word of Accumulator 1 as the result the LC instruction, has the format which is required to start a time. This type of loading is referred to as loading a time in BCD format. The time value in the timer word is decremented from its start value to 0. When you use the LC instruction with a timer word as address, you get a value that lies between the starting time of the timer word and 0. The time that elapses from the moment a timer starts is calculated from the difference of the start time and the time currentlybeing read.
STL LC T 1
Explanation Load accumulator 1 low with the time and time base of timer T 1 in BCD format.
15 14 13 12 11 10 9 Timer word Time base 15 14 13 12 11 Accumulator 1 low 0 0 Time base Figure 8-4 102 (Hundreds)
Time
Binary to BCD 0
101 (Tens)
100 (Ones)
The value contained in the accumulator as a result of the LC operation can be used for further processing, such as transferring the value to the outputs for a display. You cannot transfer a value from the accumulator to the timer word.
8-9
Loading a Count in BCD Format
A count value is stored in a counter word in binary code. You can use the following Load (L) instruction to read the count value in binary coded decimal (BCD) format out of a counter word and load it into the low word of accumulator 1: LC <counter word> This type of loading is referred to as loading a count value in BCD format. The value contained in the low word of accumulator 1 as a result of the LC operation has the same format as is needed to set a counter. A count value is stored in a counter word in binary code. You can load the time value into the low word of accumulator 1 in binary coded decimal format (BCD format, see Figure 8-5). You can use the LC instruction to read out a count value in BCD format.
STL LC C 1
Explanation Load accumulator 1 low directly with the count value of counter C 1 in binary coded decimal format.
15 14 13 Counter word for C 1 X X X
12 11 10 9 X X X
Count value Binary to BCD 15 14 13 12 Accumulator 1 low 0 0 0 0 102 (Hundreds) 101 (Tens) Count in BCD format 100 (Ones) 11 10 9 8 7 6 5 4 3 2 1 0
Figure 8-5
Loading a Count Value into Accumulator 1 Using the LC Innstruction
The value contained in the accumulator as a result of the LC operation can be used for further processing, such as transferring the value to the outputs for a display. You cannot transfer a value from the accumulator to the counter word.
8-10
8.6
Loading and Transferring between Address Registers
Description
Your program can use the following instructions to enable the CPU to exchange information between address registers or exchange the contents of the two registers: Instruction
LAR1
Explanation
Loads address register 1 with the contents of the area that the instruction addresses. If no address is indicated, LAR1 loads address register 1 with the contents of accumulator 1. LAR1 can also use AR2 as an address, that is LAR1 can load AR1 with the contents of AR2. Loads address register 2 with the contents of the area that the instruction addresses. If no address is indicated, LAR2 loads address register 2 with the contents of accumulator 1. Transfers the contents of address register 1 into the destination that the instruction addresses. If no address is indicated, TAR1 transfers the contents of address register 1 to accumulator 1. TAR1 can also use AR2 as an address, that is, TAR1 can transfer the contents of AR1 into AR2. Transfers the contents of address register 2 into the destination that the instruction addresses. If no address is indicated, TAR2 transfers the contents of address register 2 to accumulator 1. Exchanges the contents of AR1 and AR2.
LAR2
TAR1
TAR2
TAR
The LAR1 and LAR2 instructions can address constants of 32 bits. This type of addressing is called immediate addressing (see Section 3.1). The immediate address is used to load a 32-bit pointer immediately into the address register (see Table 8-5). LAR1 P#{area,} Byte{.Bit} with {area} = {I, Q, M, D, DX, L} Byte = 0 to 65,535 {.Bit} = 0 to 7
Table 8-5 LAR1 and LAR2: Immediate Addressing Example LAR1 LAR2 LAR1 P#I0.0 P#0.0 P##Start Description Loads the area-crossing pointer P#I0.0 into address register 1 Loads the area-internal pointer with the location 0 into address register 2 Loads an area-crossing pointer to the local variable (Start) into address register 1
8-11
Direct Addressing
You can use direct addressing with LAR1, LAR2, TAR1, and TAR2.
Table 8-6 Instruction LAR1 LAR2 TAR1 LAR1, LAR2, TAR1, TAR2: Direct Addressing Register As Address {BLANK}1) {BLANK}1 {BLANK}2) or AR2 {BLANK}2) or AR2 Address Identifier and Range DBD DID LD MD DBD DID LD MD
532 0 to 65 65,532
0 to 65,532
TAR2
1 2
{BLANK} If no address is indicated, LAR1/LAR2 loads the address register with the contents of accumulator 1. {BLANK} If no address is indicated, TAR1/TAR2 transfers the contents of the address register to accumulator 1.
8.7
Loading Data Block Information

You can use the Load (L) instruction to load the length or number of a data block into accumulator 1. Table 8-7 summarizes the addresses for this type of loading. For more information on on loading the length or number of a data block into accumulator 1 see Section 15.3.
Table 8-7 Address DBLG DILG DBNO DINO Loading the Length or Number of a Data Block into Accumulator 1 Explanation Loads the length in bytes of a shared data block into accumulator 1 Loads the length in bytes of an instance data block into accumulator 1 Loads the number of a shared data block into accumulator 1 Loads the number of an instance data block into accumulator 1
8-12
Integer Math Instructions

Chapter Overview
Section 9.1 9.2 Four-Function Math Adding an Integer to Accumulator 1 Description
9
Page 9-2 9-6
9-1
9.1
Four-Function Math
Description
Table 9-1 lists the statement list instructions that you can use to add, subtract, multiply, and divide integers (16 bits) and double integers (32 bits).
Table 9-1 Instruction +I Four-Function Math Instructions for Integers and Double Integers Size in Bits 16 Function Adds the contents of the low words of accumulators 1 and 2 and stores the result in the low word of accumulator 1. Subtracts the contents of the low word of accumulator 1 from the contents of the low word of accumulator 2 and stores the result in the low word of accumulator 1. Multiplies the contents of the low words of accumulators 1 and 2 and stores the result (32 bits) in accumulator 1. Divides the contents of the low word of accumulator 2 by the contents of the low word of accumulator 1. The result is stored in the low word of accumulator 1. Any whole remainder is stored in the high word of accumulator 1. Adds the contents of accumulators 1 and 2 and stores the result in accumulator 1. Subtracts the contents of accumulator 1 from the contents of accumulator 2 and stores the result in accumulator 1. Multiplies accumulator 1 by the contents of accumulator 2 and stores the result in accumulator 1. Divides the contents of accumulator 2 by the contents of accumulator 1. The result is stored in accumulator 1. Divides the contents of accumulator 2 by the contents of accumulator 1 and stores the remainder as a result in accumulator 1.
I I
16
16
/I
16
+D D D /D
32 32 32 32
MOD
32
Relationship of Math Operators to Accumulators
The function descriptions in Table 9-1 point out that the math operations combine the contents of accumulators 1 and 2. The result is stored in accumulator 1. The old contents of accumulator 1 is shifted to accumulator 2. The contents of accumulator 2 remains unchanged. In the case of CPUs with four accumulators, the contents of accumulator 3 is then copied into accumulator 2 and the contents of accumulator 4 into accumulator 3. The old contents of accumulator 4 remains unchanged.
9-2
Combining two Integers (16 bits) in CPUs with two Accumulators
The Add Accumulators 1 and 2 As Integer instruction (+I) tells the CPU to add the contents of the low word of accumulator 1 and the low word of accumulator 2 and store the result in the low word of accumulator 1. This operation overwrites the old contents of the low word of accumulator 1. The old contents of accumulator 2 and the high word of accumulator 1 remain unchanged (see Figure 9-1). A sample program follows the figure.
Accumulator contents before math operation Accumulator 2
31 16 15 0
Accumulator contents after math operation Accumulator 2
IV Accumulator 1
31 16 15
III +I
0
IV Accumulator 1 II
III
II
III + I
Figure 9-1
Adding Two Integers
Combining two Integers (16 bits) in CPUs with four Accumulators
The Add Accumulators 1 and 2 As Integer instruction (+I) tells the CPU to add the contents of the low word of accumulator 1 and the low word of accumulator 2 and store the result in the low word of accumulator 1. This operation overwrites the old contents of the low word of accumulator 1. It then copies the contents of accumulator 3 to accumulator 2 and the contents of accumulator 4 to accumulator 3. Accumulator 4 and the high word of accumulator 1 remain unchanged (see Figure 9-2).

31 16 15 0
Accumulator contents after math operation Accumulator 4
VIII Accumulator 3
31 16 15
VII
VIII Accumulator 3
0
VII
VI Accumulator 2
31 16 15
VIII Accumulator 2
0
VII
IV Accumulator 1
31 16 15
III +I
0
VI Accumulator 1 II
II
III + I
Figure 9-2
Adding two Integers in CPUs with four Accumulators
9-3
STL L L MW10 DBW12
Explanation Load the value of memory word MW10 into accumulator 1. Load the value of data word DBW12 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. The CPU interprets the contents of the low words of accumulators 1 and 2 as 16-bit integers, adds them, and stores the result in the low word of accumulator 1. Transfer the contents of the low word of accumulator 1 (the result) to data word DBW14.
+I
DBW14
Evaluating the Bits in the Status Word
The math instructions affect the following bits of the status word:
S CC 1 and CC 0 S OV S OS
Valid Result
A hyphen () entered in a bit column of the table means that the bit in question is not affected by the result of the integer math operation. You can use the instructions in Table 9-5 to evaluate these bits of the status word
Table 9-2 Signal State of Bits in the Status Word for Integer Math Result in Valid Range
Bits of Status Word Valid Range g for an Integer g (16 Bits) and Double Integer (32 Bits) Result CC 1 CC 0 OV OS 0 (zero) I: -32,768 v Result t 0 (negative number) D: -2,147,483,648 v Result t 0 (negative number) I: 32,767 w Result u0 (positive number) D 2,147,483,647 w Result u0 (positive number) 0 0 1 0 1 0 0 0 0
Table 9-3
Signal State of Bits in the Status Word for Integer Math Result That Is Not in Valid Range Bits of Status Word CC 1 CC 0 1 0 0 1 OV 1 1 OS 1 1
Invalid Result
Range g Not Valid for a Double Integer g Result (32 Bits) I: Result u D: Result u 32,767 (positive number) 2,147,483,647 (positive number)
I: t 32,768 (negative number) D: Result t -2,147,483,648 (negative number)
9-4
Table 9-4
Signal State of Bits in the Status Word for Double Integer Math Instructions +D, /D, and MOD Bits of Status Word Instruction Instruct on CC 1 CC 0 0 1 0 1 OV 1 1 OS 1 1
+D: Result = -4,294,967,296 /D or MOD: Division by 0 has occurred.
Table 9-5
Instructions That Evaluate the CC 1, CC 0, OV, and OS Bits Reference to Bit of the Status Word or Jump Label Bits in Status Word That Are Evaluated (indicated by an X) Section in This Manual 5.3 16.4 16.4 16.5 16.5 16.5 16.5 16.5 16.5 16.5
Instruction
A,O,X,AN,ON,XN JO JOS JUO JZ JN JP JM JMZ JPZ
>0, <0, <>0, >=0, <=0, CC 1, CC 0, OV, OS ==0, UO, OV, OS <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> OV OS CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0
9-5
9.2
Adding an Integer to Accumulator 1
Add 16 and 32-Bit Integer Constants
You can use the Add Integer Constant instruction to add an integer constant to the contents of the low word of accumulator 1. Table 9-6 lists the possibilities. These instructions do not affect the status word bits.
Table 9-6 Instruction +
Adding an Integer to Accumulator 1 Address + integer Function Adds a 16-bit integer constant to the contents of the low word of accumulator 1. The result is stored in accumulator 1. The old contents of the low word of this accumulator are overwritten. Accumulator 2 and the high word of accumulator 1 remain unchanged. Adds a 32-bit integer constant to the contents of accumulator 1. The result is stored in accumulator 1. The old contents of this accumulator are overwritten. Accumulator 2 remains unchanged.
+ L#double integer
Examples
Below are two programs with Add Integer Constant instructions.
STL L L +I + T MW10 MW20 5 MW14
Explanation Load the value in MW10 into accumulator 1. Load the value in MW20 into accumulator 1. Add the 16-bit values in accumulator 1 and 2. Add a minus 5 to the result of the +I statement. Transfer the new result to MW14.
STL L L +D + T MD10 MD16 L#1 MD24
Explanation Load the value in MD10 into accumulator 1. Load the value in MD16 into accumulator 1. Add the 32-bit values in accumulator 1 and 2. Add a minus 1 to the result of the +D statement. Transfer the new result to MD24.
9-6
Floating-Point Math Instructions

Chapter Overview
Section 10.1 10.2 10.3 10.4 10.5 10.6 10.7 Four-Function Math Forming the Absolute Value of a Floating-Point Number Extended Math Instructions Forming the Square / Square Root of a Floating-Point Number Description
10
Page 10-2 10-6 10-7 10-9 10-11 10-12 10-13
Forming the Natural Logarithm of a Floating-Point Number Forming the Exponential Value of a Floating-Point Number Forming Trigonometric Functions on Angles Acting as Floating-Point Numbers
10-1
10.1 Four-Function Math
Description
Table 10-1 lists the statement list instructions that you can use to add, subtract, multiply, and divide 32-bit IEEE floating-point numbers. Because IEE 32-bit floating-point numbers belong to the data type called REAL, the mnemonic abbreviation for these instructions is R.
Table 10-1 Four-Function Math Instructions for IEEE 32-Bit Floating-Point Numbers Function Adds the IEEE 32-bit floating-point numbers in accumulators 1 and 2 and stores the 32-bit result in accumulator 1. Subtracts the IEEE 32-bit floating-point number in accumulator 1 from the IEEE 32-bit floating-point number in accumulator 2 and stores the 32-bit result in accumulator 1. Multiplies the IEEE 32-bit floating-point number in accumulator 1 by the IEEE 32-bit floating-point number in accumulator 2 and stores the 32-bit result in accumulator 1. Divides the IEEE 32-bit floating-point number in accumulator 2 by the IEEE 32-bit floating-point number in accumulator 1. The 32-bit result is stored in accumulator 1.
Instruction +R -R
R
/R
Relationship of Math Instructions to Accumulators
The function descriptions in Table 10-1 point out that the math instructions combine the contents of accumulators 1 and 2. The result is stored in accumulator 1. The old contents of accumulator 1 is shifted to accumulator 2. The contents of accumulator 2 remains unchanged. In the case of CPUs with four accumulators, the contents of accumulator 3 is copied into accumulator 2 and the contents of accumulator 4 into accumulator 3. The old contents of accumulator 4 remains unchanged.
10-2
Result of Combining Two Integers in CPUs with Two Accumulators
The Add Accumulators 1 and 2 As Real instruction (+R) tells the CPU to add the contents of accumulator 1 and accumulator 2 and store the result in accumulator 1. This operation overwrites the old contents of accumulator 1. The old contents of accumulator 2 remain unchanged (see Figure 10-1). A sample program follows Figure 10-2.

31 16 15 0
Accumulator contents after math operation Accumulator 2 II +R Accumulator 1 II + I
II Accumulator 1
31 16 15 0
Figure 10-1
Adding Two IEEE Floating-Point Numbers
The same pattern applies to the remaining floating-point math instructions.

Table 10-2 Result of Instructions with Denormalized Numbers in CPUs with Two Accumulators Input Value Result Accumulator 1 Accumulator 2 Accumulator 1 Accumulator 2 a a a a b b b b a -a 0 FFFF b b b b
Instruction +R -R *R +R
10-3
Result of Combining Two Integers in CPUs with Two Accumulators
The Add Accumulators 1 and 2 As Real instruction (+R) tells the CPU to add the contents of accumulator 1 and accumulator 2 and store the result in accumulator 1. This instruction overwrites the old contents of accumulator 1. Next the contents of accumulator 3 is copied into accumulator 2 and the contents of accumulator 4 is copied into accumulator 3 (see Figure 10-2).
Accumulator contents before math instruction Accumulator 4
31 16 15 0
Accumulator contents after math instruction Accumulator 4 IV Accumulator 3
IV Accumulator 3
31 16 15 0
III Accumulator 2
31 16 15 0
IV Accumulator 2 II +R
0
II Accumulator 1
31 16 15
Accumulator 1 II + I
I Figure 10-2
Adding Two IEEE Floating-Point Numbers in CPUs with four Accumulators
The same pattern applies to the remaining floating-point math instructions. Example
STL L L MD100 DBD4 Explanation Load the value in memory double word MD100 into accumulator 1. Load the value in data double word DBD4 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. (The values in these double words must be in floating-point format.) The CPU interprets the contents of accumulators 1 and 2 as 32-bit IEEE floating-point numbers, adds them, and stores the result in accumulator 1. Transfer the contents of accumulator 1 (the result) to data double word DBD16. (DBD16 = MD100 + DBD4)
+R
DBD16
Bits Affected by the Math Instructions
The math instructions do affect the following bits of the status word: S CC 1 and CC 0 S OV S OS You can use the instructions in Table 10-5 to evaluate these bits of the status word. Table 10-3 shows the signal states of the status word bits for floating-point math results that fall within the valid range. A hyphen () entered in a bit column of the table means that the bit in question is not affected by the result of the floating-point math instruction.
10-4
Table 10-3
Signal State of Bits in the Status Word for Floating-Point Math Result in Valid Range Bits of Status Word
Valid Val d Range for a Float Floating ng-Po Point nt Result (32 B Bits) ts) +0, -0 (zero) -3.402823E+38 t Result t -1.175494E38 (negative number) +1.175494E38 t Result t 3.402823E+38 (positive number)
CC 1 CC 0 0 0 1 0 1 0
OV 0 0 0
OS
Table 10-4
Signal State of Bits in the Status Word for Floating-Point Math Result That Is Not in Valid Range Bits of Status Word CC 1 CC 0 0 0 0 1 0 0 1 0 OV 1 1 1 1 OS 1 1 1 1
g Not Valid for a Floating-Point g Range Result (32 Bits) -1.175494E38 t Result t -1.401298E45 (negative number) Underflow +1.401298E45 t Result t +1.175494E38 (positive number) Underflow Result t -3.402823E+38 (negative number) Overflow Result u -3.402823E+38 (positive number) Overflow
Table 10-5
Instructions That Evaluate the CC 1, CC 0, OV, and OS Bits of the Status Word Reference to Bit of Status Word or Jump Label Bits in Status Word That Are Evaluated (indicate d by an X) Section in This Manual 5.3 16.4 16.4 16.4 16.5 16.5 16.5 16.5 16.5 16.5
Instruction
A,O,X,AN,ON,XN JO JOS JUO JZ JN JP JM JMZ JPZ
>0, <0, <>0, >=0, <=0, CC 1, CC 0, OV, OS ==0, UO, OV, OS <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> OV OS CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0
10-5
10.2 Forming the Absolute Value of a Floating-Point Number
Description
You can use the Absolute Value of a Real instruction (ABS) to form the absolute value of an IEEE 32-bit floating-point number in accumulator 1. An absolute value is a non-negative number equal in numerical value to a given real number. For an absolute value, a sign (+ or -) is not relevant. For example, 5 is the absolute value of +5 or -5.
Example
The following program provides an example of the ABS instruction:
STL L L /R DBD0 +12.3E+00
Explanation Load the value in data double word DBD0 into accumulator 1. Load the value +12.3E+00 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. The CPU divides the contents of accumulator 2 by the contents of accumulator 1 and stores the result in accumulator 1. Transfer the contents of accumulator 1 (the result) to memory double word MD20. (MD20 = DBD0 / 12.3) Negate the IEEE floating-point number in accumulator 1 (see Section 12.4). Transfer the result from accumulator 1 to memory double word MD24. (MD24 = [1] MD20) The CPU forms the absolute value of the IEEE floating-point number in accumulator 1. Transfer the absolute value from accumulator 1 to memory double word MD28. (MD28 = ABS[MD20])
MD20
NEGR T MD24 ABS T MD28
10-6
10.3 Extended Math Instructions
Description
Table 10-6 lists the STL instructions which can be used for extended math instructions on floating-point numbers.

Table 10-6 Extended Math Instructions for IEEE 32-Bit Floating-Point Numbers Function Instruction SQRT SQR LN Calculates the square root of the 32 bit IEEE floating-point number in ACCU1 and stores the 32 bit result in ACCU1. Calculates the square of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. Calculates the natural logarithm of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. EXP SIN Calculates the exponential value of the 32 bit IEEE floating-point number to base E and stores the 32-bit result in ACCU1. Calculates the sine of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. Calculates the cosine of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. COS TAN Calculates the tangent of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. ASIN Calculates the arc sine of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. ACOS ATAN Calculates the arc cosine of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1. Calculates the arc tangent of the 32 bit IEEE floating-point number in ACCU1 and stores the 32-bit result in ACCU1.
Relationship of Extended Math Instructions to Accumulators
The extended math instructions only work in conjunction with accumulator 1. The value to which the operation is applied is expected in accumulator 1. The result is stored in accumulator 1; the old contents of accumulator 1 is overwritten. The contents of accumulator 2, accumulator 3 and accumulator 4 remain unchanged.
10-7
Effect of Extended Math Instructions on the Bits in the Status Word
The CPU executes the four-function math instructions listed in Table 10-1, without regard to, and without affecting the result of logic operation. The extended math instructions do affect the following bits of the status word:
To evaluate these bits, you can use the instructions in Table 10-7 (Section 10.1) and see Section 5.3.

Instruction Reference to Bit of Bits in Status Word Status Word or Jump That Are Evaluated Label (indicated by an X) CC 1, CC 0, OV, OS OV OS Section in This Manual 5.3 A, O, X, AN, ON, XN >0, <0, <>0, >=0, <=0, ==0, UO, OV, OS JO <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> 16.4 16.4 16.4 16.5 16.5 16.5 16.5 16.5 16.5 JOS JUO JZ CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 CC 1 and CC 0 JN JP JM JMZ JPZ
Table 10-7
Extended Math Instructions for 32-Bit IEEE Floating-Point Numbers
10-8
10.4 Forming the Square / Square Root of a Floating-Point Number
Description
The instruction SQR (square) calculates the square of the 32 bit IEEE floating-point number in accumulator 1 and stores the 32-bit result in accumulator 1. The operation SQR overwrites the old contents of accumulator 1; the contents of accumulator 2, accumulator 3, and accumulator 4 remain unchanged. The instruction SQRT (square root) calculates the square root of the 32 bit IEEE floating-point number in accumulator 1 and stores the 32-bit result in accumulator 1. The input value must be greater or equal to zero. The instruction SQRT overwrites the old contents of accumulator 1; the contents of accumulator 2, accumulator 3, and accumulator 4 remain unchanged. This instruction gives a positive result when all the addresses are greater than zero (0). The only exception: the Square Root of -0 is -0.
Table 10-8 Effects of Instruction SQR on Bits CC 1, CC 0, OV and OS CC 1 1 1 1 0 0 1 CC 0 1 0 0 0 0 1 OV 1 1 0 1 0 1 OS 1 1 1 1
Effects on Bits CC 1, CC 0, OV and OS of the Status Word
Result in Accumulator 1 + qNaN + Infinite (Overflow) + Valid + Not valid (Underflow) + Null - qNaN
Example
The following program extract is an example of how the instruction SQR is used.

STL Explanation OPN DB17 L DBD0 Open data block DB17. (It is assumed that it contains the input value and will store the result). Load the value in data double word DBD0 into accumulator 1. (The value in this double word must be in floating-point format.) SQR Calculate the square of the 32 bit IEEE floating-point number. Store the result in accumulator 1. Check that the status bit OV is 0. AN OV JC OK ... If operation SQR has no errors, jump tothe label OK (In the event of an error an appropriate reaction takes place at this point.) OK: T DBD4 Transfer the result of accumulator 1 to data double word DBD4. Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
10-9
Table 10-9
Effects of Instruction SQRT on Bits CC 1, CC 0, OV and OS CC 1 1 1 1 0 0 0 1 CC 0 1 0 0 0 0 0 1 OV 1 1 0 1 0 0 1 OS 1 1 1 1
Result in Accumulator 1 + qNaN + Infinite (Overflow) + Valid + Not valid (Underflow) + Zero -Zero - qNaN
Example
The following program extract is an example of how the instruction SQRT is used.
STL L MD10 SQRT AN OV JC OK ... OK: T MD20
Explanation Load the value in memory double word MD10 into accumulator 1. (The value must be in floating-point format.) Form the square root of the 32 bit IEEE floating-point number in accumulator 1. Store the result in accumulator 1. Check that the status bit OV is 0. If operation SQR has no errors, jump to the label OK. (In the event of an error an appropriate reaction takes place at this point.) Transfer the result (accumulator 1) in the memory double word MD20.
10-10
10.5 Forming the Natural Logarithm of a Floating-Point Number
Description
The instruction LN (natural logarithm) calculates the natural logarithm of the floating-point number in accumulator 1 and stores the 32-bit result in accumulator 1. The input value must be greater than zero (0). The instruction LN overwrites the old contents of accumulator 1; the contents of accumulator 2, accumulator 3, and accumulator 4 remain unchanged.
Table 10-10 shows the effects that the instruction LN has on the signal state of bits CC 1, CC 0, OV and OS of the status word. A hyphen (-) entered in a bit column of the table means that the bit in question is not affected by the result of the floating-point math instruction.
Table 10-10 Effects of Instruction LN on Bits CC 1, CC 0, OV and OS CC 1 1 1 1 0 0 0 0 0 0 1 CC 0 1 0 0 0 0 0 0 1 1 1 OV 1 1 0 1 0 0 1 0 1 1 OS 1 1 1 1 1 1
Result in Accumulator 1 + qNaN + Infinite (Overflow) + Valid + Not valid (Underflow) + Zero -Zero - Not valid (Underflow) - Valid - Infinite (Overflow) - qNaN
Example
The following program extract is an example of how the instruction LN is used.

Explanation

STL L MD10 LN Load the value from memory double word MD10 into accumulator 1. (The value must be in floating-point format.) Form the natural logarithm of the 32 bit IEEE floating-point number in accumulator 1. Store the result in accumulator 1. Check that the status bit OV is 0. AN OV JC OK ... If operation SQR has no errors, jump to the label OK. (In the event of an error an appropriate at this point.) reaction takes place OK: T MD20 Transfer the result from accumulator 1 to memory double word MD20. Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01
10-11
10.6 Forming the Exponential Value of a Floating-Point Number
Description
The instruction EXP (exponential value to base E) calculates the exponential value of the 32 bit IEEE floating-point number in accumulator 1 to base E (=2.71828) and stores the 32-bit result in accumulator 1. The input value must be greater than zero (0). The operation EXP overwrites the old contents of accumulator 1; the contents of accumulator 2, accumulator 3, and accumulator 4 remain unchanged.
Table 10-11 shows the effects that the instruction EXP has on the signal state of bits CC 1, CC 0, OV and OS of the status word. A hyphen (-) entered in a bit column means that the bit in question is not affected by the result of the floating-point math instruction.
Table 10-11 Effects of Instruction EXP on Bits CC 1, CC 0, OV and OS of the Status Word CC 1 1 1 1 0 0 1 CC 0 1 0 0 0 0 1 OV 1 1 0 1 0 1 OS 1 1 1 1
Result in Accumulator 1 + qNaN + Infinite (Overflow) + Valid + Not Valid (Underflow) + Zero - qNaN
Example
The following program extract is an example of how the instruction EXP is used.
Explanation

STL L MD10 EXP Load the value from memory double word MD10 into accumulator 1. (The value must be in floating-point format.) Form the exponential value on basis E of the 32 bit IEEE floating-point number in accumulator 1. Store the result in accumulator 1. Check that the status bit OV is 0. AN OV JC OK ... If operation EXP has no errors, jump to the label OK. (In the event of an error an appropriate reaction takes place at this point.) Transfer the result from accumulator 1 to memory double word MD20. OK: T MD20
10-12
10.7 Forming Trigonometric Functions on Angles Acting as Floating-Point Numbers

Description Using the following instructions you can form trigonometric functions on angles acting as 32 bit IEEE floating-point numbers. The 32-bit result is stored in accumulator 1; the contents of accumulator 2, accumulator 3 and accumulator 4 remain unchanged.
Instr. SIN ASIN Function Form the sine of the floating-point number of an angle expressed in radians. Store the angle as a floating-point number in ACCU1. Form the arc sine of a floating-point number in ACCU1. The result is an angle expressed in radians. The value will be in the following range: p / 2 v cosecant (ACCU 1) v + p / 2,when p = 3.14... Form the cosine of the floating-point number of an angle expressed in radians. Store the angle as a floating-point number in ACCU1. Form the arc cosine of a floating-point number in ACCU1. The result is an angle expressed in radians. The value will be in the following range: 0 v secant (ACCU 1) v + p, when p = 3.14... Form the tangent of the floating-point number of an angle expressed in radians. Save the angle as a floating-point number in ACCU1. Form the arc tangent of a floating-point number in ACCU1. The result is an angle expressed in radians. The value will be in the following range: p / 2 v cotangent (ACCU 1) v + p / 2, when p = 3.14...
COS ACOS
TAN ATAN
Table 10-12 shows the effect that the instructions SIN, ASIN, COS, ACOS and ATAN have on the signal state of bits CC 1, CC 0, OV and OS in the status word. Table 10-13 shows how TAN affects these bits. A hyphen () means that the bit in question is not affected by the instruction.
Table 10-12 Effects of Instructions SIN, ASIN, COS, ACOS and ATAN CC 1 1 1 0 0 0 0 0 1 CC 0 1 0 0 0 0 0 1 1 OV 1 0 1 0 0 1 0 1 OS 1 1 1 1
Result in Accumulator 1 + qNaN + Valid + Infinite (Overflow) + Zero -Zero - Not valid (Underflow) - Valid - qNaN
10-13
Table 10-13
Effects of Instruction TAN on Bits CC 1, CC 0, OV and OS CC 1 1 1 1 0 0 0 0 0 0 1 CC 0 1 0 0 0 0 0 0 1 1 1 OV 1 1 0 1 0 0 1 0 1 1 OS 1 1 1 1 1 1
Result in Accumulator 1 + qNaN + Infinite (Overflow) + Valid + Not valid (Underflow) + Zero -Zero -Not valid (Underflow) -Valid - Infinite (Overflow) - qNaN
Example
The following program extract is an example of how the instruction SIN is used.
Explanation

STL L MD10 SIN Load the value from memory double word MD10 into accumulator 1. (The value must be in floating-point format.) Form the sine of the 32 bit IEEE floating-point number into accumulator 1. Store the result in accumulator 1. T MD20 Transfer the result from accumulator 1 into memory double word MD20.
Example
The following program extract is an example of how the instruction ASIN is used.
Explanation

STL L MD10 ASIN Load the value from memory double word MD10 into accumulator 1. (The value must be in floating-point format.) Form the cosecant of the 32 bit IEEE floating-point number in accumulator 1. Store the result in accumulator 1. Check that the status bit OV is 0. AN OV JC OK ... If operation ASIN has no errors, jump to the label OK. (In the event of an error an appropriate reaction takes place at this point.) OK: T MD20 Transfer the result from accumulator 1 into memory double word MD20.
10-14
Evaluating the Bits in the Status Word
The extended math instructions affect the following bits in the status word:
Valid Result
A hyphen () entered in a bit column of the table means that the bit in question is not affected by the result of the floating-point math instruction.

Valid Range for a Floating-Point Result (32 Bits) Bits of Status Word OV 0 0 0 CC 1 CC 0 0 0 1 0 1 0 OS +0, -0 (zero) -3.402823E+38 t Result t -1.175494E38 (negative number) +1.175494E38 t Result t 3.402823E+38 (positive number) Table 10-15 Signal States of the Bits in the Status Word: Calculation Result with Floating-Point Numbers outside the Valid Range Bits of Status Word OV 1 1 1 1
Table 10-14
Inverse Functions for 32 Bit IEEE Floating-Point Numbers and Valid Ranges for the Value Input

Valid Range for a Floating-Point Result (32 Bits) -1.175494E38 t Result t -1.401298E45 (negative number) Underflow CC 1 CC 0 0 0 0 1 0 0 1 0 OS 1 1 1 1 +1.401298E45 t Result t +1.175494E38 (positive number) Underflow Result t -3.402823E+38 (negative number) Overflow Result u -3.402823E+38 (positive number) Overflow

Valid Range for a Floating-Point Result (32 Bits) Bits of Status Word OV 1 1 CC 1 CC 0 1 1 1 1 OS 1 1 There is no valid 32-bit IEEE floating-point number in ACCU 1. Instruction not permitted: the input value in ACCU 1 is outside the valid range.
Table 10-16
Signal States of the Bits in the Status Word: The Input Value Represents an Invalid Number or is outside the Valid Range
10-15
10-16
Comparison Instructions
Chapter Overview
Section 11.1 11.2 11.3 Overview Comparing Two Integers Comparing Two Floating-Point Numbers Description
11
Page 11-2 11-3 11-5
11-1
11.1 Overview
You can use the Compare instructions to compare the following pairs of numeric values:
S Two integers (16 bits) S Two double integers (32 bits) S Two real numbers (IEEE floating-point, 32 bits)
You load the numeric values into accumulators 1 and 2. A Compare instruction compares the value in accumulator 2 to the value in accumulator 1 according to the criteria listed in Table 11-1. The result of the comparison is a binary digit, that is, either a 1 or a 0. A 1 indicates that the result of the comparison is true; a 0 indicates that the result of the comparison is false (see Table 11-2). This result is stored in the result of logic operation bit (RLO bit, see Section 3.4). You can use this result in your program for further processing. When the CPU executes a Compare instruction, it also sets bits in the status word. Other statement list instructions can evaluate the bits of the status word. The CPU executes Compare instructions without regard to the result of logic operation.
Table 11-1 Criteria for Comparisons Comparison Criterion is equal to Symbol(s) for Instruction ==I ==D ==R <>I <>D <>R >I >D >R <I <D <R >=I >=D >=R <=I <=D <=R Integer (16 bits) g ( ) Double integer (32 bits) Real number (floating-point, 32 bits) Type of Numeric Value in Accumulator 1
Type of Numeric Value in Accumulator 2
is not equal to
Integer (16 bits) g ( ) Double integer (32 bits)
is greater than
is less than Real number (floating-point, 32 bits) is greater than or equal to
is less than or equal to
11-2
11.2 Comparing Two Integers
Description
The Compare Integer instructions compare two single integers (16 bits each) and the Compare Double Integer instructions compare two double integers (32 bits each) according to the criteria listed in Table 11-2. A sample program follows Table 11-3.
Compare Integer and Compare Double Integer Instructions Explanation Explanat on The integer in the low word of accumulator 2 is equal to the integer in the low word of accumulator 1. The double integer in accumulator 2 is equal to the double integer in accumulator 1. The integer in the low word of accumulator 2 is not equal to the integer in the low word of accumulator 1. The double integer in accumulator 2 is not equal to the double integer in accumulator 1. The integer in the low word of accumulator 2 is greater than the integer in the low word of accumulator 1. The double integer in accumulator 2 is greater than the double integer in accumulator 1. The integer in the low word of accumulator 2 is less than the integer in the low word of accumulator 1. The double integer in accumulator 2 is less than the double integer in accumulator 1. The integer in the low word of accumulator 2 is greater than or equal to the integer in the low word of accumulator 1. The double integer in accumulator 2 is greater than or equal to the double integer in accumulator 1. The integer in the low word of accumulator 2 is less than or equal to the integer in the low word of accumulator 1. The double integer in accumulator 2 is less than or equal to the double integer in accumulator 1.
Table 11-2 Instruction Instruct on ==I ==D <>I <>D >I >D <I <D >=I >=D <=I <=D
11-3
Setting Bits CC 1 and CC 0 of the Status Word
A Compare Integer or Compare Double Integer instruction sets certain combinations in the CC 1 and CC 0 bits to indicate what condition has been fulfilled (see Table 11-3).
Table 11-3 Condition Settings of Bits CC 1 and CC 0 after a Compare Instruction Signal states of CC 1 and CC 0: CC 1 ACCU 2 > ACCU 1 ACCU 2 < ACCU 1 ACCU 2 = ACCU 1 ACCU 2 <> ACCU 1 1 0 0 0 or 1 1 or 0 0 or 0 CC 0 0 1 0 1 or 0 0 or 0 1 or 0 Possible check with the instructions A, O, X, AN, ON, XN >0 <0 ==0 <>0
ACCU 2 >= ACCU 1
>=0
ACCU 2 <= ACCU 1
<=0
Example
The following sample program shows how the Compare instructions for integers (16 bits) work.
STL L MW10 L IW0
Explanation Load the contents of memory word MW10 into accumulator 1. Load the contents of input word IW0 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Compare the value in the low word of accumulator 2 to the value in the low word of accumulator 1 to see if they are equal. Output Q 4.0 will be energized if MW10 and IW0 are equal. Compare the value in the low word of accumulator 2 to see if it is greater than the value in the low word of accumulator 1.
==I
= >I
Q 4.0
= <I
Q 4.1
Output Q 4.1 will be energized if MW10 is greater than IW0. Compare the value in the low word of accumulator 2 to see if it is less than the value in the low word of accumulator 1.
Q 4.2 Output Q 4.2 will be energized if MW10 is less than IW0.
11-4
11.3 Comparing Two Floating-Point Numbers

Description The Compare Floating-Point Number instructions compare two 32-bit IEEE floating-point numbers according to the criteria listed in Table 11-4. Because IEE 32-bit floating-point numbers belong to the data type called REAL, the mnemonic abbreviation for these instructions is R.
Table 11-4 Instruction Instruct on ==R <>R >R <R >=R <=R Compare Real Instructions (IEEE 32-bit Floating-Point Numbers) Explanation Explanat on The IEEE 32-bit floating-point number in accumulator 2 is equal to the IEEE 32-bit floating-point number in accumulator 1. The IEEE 32-bit floating-point number in accumulator 2 is not equal to the IEEE 32-bit floating-point number in accumulator 1. The IEEE 32-bit floating-point number in accumulator 2 is greater than the IEEE 32-bit floating-point number in accumulator 1. The IEEE 32-bit floating-point number in accumulator 2 is less than the IEEE 32-bit floating-point number in accumulator 1. The IEEE 32-bit floating-point number in accumulator 2 is greater than or equal to the IEEE 32-bit floating-point number in accumulator 1. The IEEE 32-bit floating-point number in accumulator 2 is less than or equal to the IEEE 32-bit floating-point number in accumulator 1.
Setting Bits of the Status Word
A Compare Real number instruction sets certain combinations in the CC 1, CC 0, OV, and OS bits of the status word to indicate what condition has been fulfilled.
Table 11-5 Settings of Bits of the Status Word after a Compare Real Instruction (IEEE 32-bit Floating-Point Numbers) CC 1 0 0 or 1 1 0 1 or 0 0 or 0 1 CC 0 0 1 or 0 0 1 0 or 0 1 or 0 1 OV 0 0 0 0 0 OS not applicable not applicable not applicable not applicable not applicable
Condition == <> > < >=
<= UO
0 1
not applicable 1
11-5
Evaluating the Bits of the Status Word
Other statement list instructions can evaluate the bits of the status word (see Section 5.3 and Table 11-6).
Table 11-6 Instructions That Evaluate the CC 1, CC 0, OV, and OS Bits of the Status Word Reference to Bits of the Status Word or Jump Section in Label this Manual >0, <0, <>0, >=0, <=0, ==0, UO, OV, OS <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> <jump label> 5.3 16.4 16.5 16.5 16.5 16.5 16.5 16.5
Instruction A,O,X,AN,ON,XN JUO JZ JN JP JM JMZ JPZ
Example
The following sample program shows how the Compare Real number instructions work.
STL L MD24 L +1.00E+00
Explanation Load the contents of memory double word MD24 into accumulator 1. Load the value 1 as a 32-bit floating-point number into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Compare the value in accumulator 2 to see if it is greater than the value in accumulator 1. Output Q 4.1 will be energized if MD24 is greater than 1. Compare the value in accumulator 2 to see if it is less than the value in accumulator 1. Output Q 4.2 will be energized if MD24 is less than 1.
>R = Q 4.1 <R = Q 4.2
11-6
Conversion Instructions
Chapter Overview
Section 12.1 12.2 12.3 12.4 Description
12
Page 12-2 12-8 12-13 12-14
Converting Binary Coded Decimal Numbers and Integers Converting 32-Bit Floating-Point Numbers to 32-Bit Integers Reversing the Order of Bytes within Accumulator 1 Forming Complements and Negating Floating-Point Numbers
12-1
12.1 Converting Binary Coded Decimal Numbers and Integers
Description
You can use the following instructions to convert binary coded decimal numbers and integers to other types of numbers: Mnemonic BTI Instruction BCD to Integer Function This instruction converts a binary coded decimal value in the low word of accumulator 1 to a 16-bit integer. This instruction converts a binary coded decimal value in accumulator 1 to a 32-bit integer. This instruction converts a 16-bit integer in the low word of accumulator 1 to a binary coded decimal value. This instruction converts a 16-bit integer in the low word of accumulator 1 to a 32-bit integer. This instruction converts a 32-bit integer in accumulator 1 to a binary coded decimal value. This instruction converts a 32-bit integer in accumulator 1 to a 32-bit IEEE floating-point number (real number).
BTD
BCD to Double Integer Integer to BCD
ITB
ITD
Integer to Double Integer Double Integer to BCD Double Integer to Real
DTB
DTR
12-2
BCD to Integer: BTI
The BCD to Integer (BTI) instruction converts a three-place binary coded decimal number (BCD number, see Figure 12-1) in the low word of accumulator 1 to a 16-bit integer. The BCD number can be in the range of -999 to +999. The result of the conversion is stored in the low word of accumulator 1.
15 14 13 12 S S S S 102 Hundreds 101 Tens Value of the BCD number These bits are not used during the transfer. Sign: 0000 stands for positive, 1111 stands for negative. 100 Ones 11 10 9 8 7 6 5 4 3 2 1 0
Figure 12-1
Structure of a Binary Coded Decimal Number to Be Converted to Integer
If a place of a BCD number is in the invalid range of 10 to 15, a BCDF error occurs during an attempted conversion. In this case, one of the following occurrences takes place:
S The CPU goes into the STOP mode. BCD Conversion Error is entered
in the diagnostic buffer with event ID number 2521.
S If OB121 is programmed, it is called.

The following sample program includes a BTI instruction. Figure 12-2 shows how this instruction works.
STL L MW10 BTI T MW20 Explanation Load the BCD value in memory word MW10 into accumulator 1. Convert the BCD value to a 16-bit integer and store the result in accumulator 1. Transfer the result to memory word MW20.
+ 15... L MW10 BTI T MW20 MW20 0 0 0 0 MW10 0 0 0 0
9 ...8 1 0 0 1 7...
5 ...0 0 1 0 1 +915 BCD
0 0 0 1
BCD to integer 0 0 1 1 1 0 0 1 0 0 1 1 +915 integer
Figure 12-2
Using the BTI Instruction to Convert a BCD Number to a 16-Bit Integer
12-3
BCD to Double Integer: BTD
The BCD to Double Integer (BTD) instruction converts a seven-place binary coded decimal number (BCD number, see Figure 12-3) in accumulator 1 to a 32-bit integer. The BCD number can be in the range of -9,999,999 to +9,999,999. The result of the conversion is stored in accumulator 1. If a place of a BCD number is in the invalid range of 10 to 15, a BCDF error occurs during an attempted conversion. In this case, either one of the following occurrences takes place:
S The CPU goes into the STOP mode. BCD Conversion Error is entered
in the diagnostic buffer with event ID number 2521.
S If OB121 is programmed, it is called.

31... SSSS 106 105 104 103 102 101 100 ...16 15... ...0
Value of the BCD number These bits are not used during the transfer. Sign: 0000 stands for positive, 1111 stands for negative.
Figure 12-3
Structure of a 32-Bit BCD Number to Be Converted to Double Integer
The following sample program includes a BTD instruction. Figure 12-4 shows how this instruction works.
STL L MD10 Explanation Load the BCD value in memory double word MD10 into accumulator 1. Convert the BCD value to a 32-bit integer and store the result in accumulator 1. Transfer the result to memory double word MD20.
BTD T MD20
+ 31... L MD10 BTD T MD20 MD20 MD10
1 ...0 157821
...16 15...
0000 0000 0001 0101 0111 1000 0010 0001 BCD to integer 0000 0000 0000 0010 0110 1000 0111 1101
+157821
Figure 12-4
Using the BTD Instruction to Convert a BCD Number to a 32-Bit Integer
12-4
Integer to BCD: ITB
The Integer to BCD (ITB) instruction converts a 16-bit integer in the low word of accumulator 1 to a three-place binary coded decimal number. The BCD number can be in the range of -999 to +999. The result of the conversion is stored in the low word of accumulator 1. If the integer is too large to be represented in BCD format, no conversion takes place and the overflow (OV) and stored overflow (OS) bits of the status word (see Section 3.4) are set to a signal state of 1. The following sample program includes an ITB instruction. Figure 12-5 shows how this instruction works.
STL L MW10
Explanation Load the 16-bit integer value in memory word MW10 into accumulator 1. Convert the 16-bit integer to a BCD value and store the result in accumulator 1. Transfer the result to memory word MW20.
ITB T MW20
15... L MW10 ITB T MW20 MW20 1 1 1 1 0 1 0 0 MW10 1 1 1 1 1 1 1 0
...8
7... 0 1 1 0 0 0 1 1
...0 -413 integer
Integer to BCD 0 0 0 1 0 0 1 1 -413 BCD
Figure 12-5
Using the ITB Instruction to Convert a 16-Bit Integer to a BCD Number
12-5
Integer to Double Integer: ITD
The Integer to Double Integer (ITD) instruction converts a 16-bit integer in the low word of accumulator 1 to a 32-bit integer. The result of the conversion is stored in accumulator 1. The following sample program includes an ITD instruction. Figure 12-6 shows how this instruction works.
Explanation Load the 16-bit integer value in memory word MW10 into accumulator 1. Convert the 16-bit integer value to a 32-bit integer and store the result in accumulator 1. Transfer the result to memory double word MD20. 15... ...0 -10 integer
STL L MW10
ITD T MD20
L MW10 ITD
MW10
1111 1111 1111 0110
31... T MD20 Figure 12-6 MD20
Integer (16-bit) to integer (32-bit) ...16 15...
...0 0110 -10 integer
1111 1111 1111 1111 1111 1111 1111
Using the ITD Instruction to Convert a 16-Bit Integer to a 32-Bit Integer
Double Integer to BCD: DTB
The Double Integer to BCD (DTB) instruction converts a 32-bit integer in accumulator 1 to a seven-place binary coded decimal value. The BCD number can be in the range of -9,999,999 to +9,999,999. The result of the conversion is stored in accumulator 1. If the double integer is too large to be represented in BCD format, no conversion takes place and the overflow (OV) and stored overflow (OS) bits of the status word (see Section 3.4) are set to a signal state of 1. The following sample program includes a DTB instruction. Figure 12-7 shows how this instruction works.
STL L MD10
Explanation Load the 32-bit integer in memory double word MD10 into accumulator 1. Convert the 32-bit integer to a BCD value and store the result in accumulator 1. Transfer the result to memory double word MD20. 31... ...16 15... ...0 -701 integer
DTB T MD20
L MD10 DTB T MD20
MD10
1111 1111 1111 1111 1111 1101 0100 0011 Integer to BCD
MD20
1111 0000 0000 0000 0000 0111 0000 0001 0 0 0 0 7 0 1
-701 BCD
Figure 12-7
Using the DTB Instruction to Convert a 32-Bit Integer to a BCD Number
12-6
Double Integer to Real: DTR
The Double Integer to Real (DTR) instruction converts a 32-bit integer in accumulator 1 to a 32-bit IEEE floating-point number (real number). If necessary, the instruction rounds the result. The result of the conversion is stored in accumulator 1. The following sample program includes an DTR instruction. Figure 12-8 shows how this instruction works.
STL L MD10
Explanation Load the 32-bit integer in memory double word MD10 into accumulator 1. Convert the 32-bit integer to a 32-bit IEEE floating-point value and store the result in accumulator 1. Transfer the result to memory double word MD20.
DTR
MD20
L MD10 DTR
MD10
0000 0000 0000 0000 0000 0001 1111 0100 Integer (32-bit) to IEEE floating-point 31 30... 22... ...0
+500 integer
T MD20
MD20
0 100 0011 1 111 1010 0000 0000 0000 0000 8-bit exponent 1 bit Sign of the mantissa
+500 IEEE
23-bit mantissa
Figure 12-8
Using the DTR Instruction to Convert a 32-Bit Integer to an IEEE 32-Bit Floating-Point Number
For a summary of the number conversions, see Figure 12-13 at the end of Section 12.2.
12-7
12.2 Converting 32-Bit Floating-Point Numbers to 32-Bit Integers
Description
You can use any of the following instructions to convert a 32-bit IEEE floating-point number in accumulator 1 to a 32-bit integer (double integer). The individual instructions differ in their method of rounding. Mnemonic RND Instruction Round Function This instruction rounds the converted number to the nearest whole number. If the fractional part of the converted number is midway between an even and an odd result, the instruction chooses the even result. This instruction rounds the converted number to the smallest whole number greater than or equal to the floating-point number that is converted. This instruction rounds the converted number to the largest whole number less than or equal to the floating-point number that is converted. This instruction converts the whole number part of the floating-point number.
RND+
Round to Upper Double Integer
RND-
Round to Lower Double Integer
TRUNC Truncate
The result of the conversion is stored in accumulator 1. If the number to be converted is not a floating-point number or is a floating-point number that cannot be represented as a 32-bit integer, no conversion takes place and an overflow is indicated.
12-8
Round: RND
The Round (RND) instruction converts a 32-bit IEEE floating-point number in accumulator 1 to a 32-bit integer (double integer) and rounds it to the nearest whole number. If the fractional part of the converted number is midway between an even and an odd result, the instruction chooses the even result. The following sample program includes an RND instrruction. Figure 18-9 shows how this instruction works.
STL L MD10
Explanation Load the 32-bit IEEE floating-point value in memory double word MD10 into accumulator 1. Convert the 32-bit floating-point number to a 32-bit integer, round to the nearest whole number, and store the result in accumulator 1. Transfer the result to memory double word MD20.
RND
MD20
31 30... L MD10 RND T MD20 MD20 MD10
22...
...0 +100.5 IEEE
0 100 0010 1 100 1001 0000 0000 0000 0000 IEEE to integer (32-bit) 0000 0000 0000 0000 0000 0000 0110 0100
+100 integer
31 30... L MD10 RND T MD20 MD20 MD10
22...
...0 -100.5 IEEE
-100 integer
Figure 12-9
Using the RND Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer
12-9
Round to Upper Double Integer: RND+
The Round to Upper Double Integer (RND+) instruction converts a 32-bit IEEE floating-point number in accumulator 1 to a 32-bit integer (double integer). The instruction rounds the converted number to the smallest whole number greater than or equal to the floating-point number that is converted. The following sample program includes an RND+ instruction. Figure 12-10 shows how this instruction works.
STL L MD10
Explanation Load the 32-bit IEEE floating-point value in memory double word MD10 into accumulator 1. Convert the 32-bit floating-point number to a 32-bit integer. Round to the smallest whole number greater than or equal to the floating-point number that is converted and store the result in accumulator 1. Transfer the result to memory double word MD20.
RND+
MD20
31 30... L MD10 RND+ T MD20 MD20 MD10
22...
...0 +100.5 IEEE
+101 integer
31 30... L MD10 RND+ T MD20 MD20 MD10
22...
...0 -100.5 IEEE
-100 integer
Figure 12-10
Using the RND+ Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer
12-10
Round to Lower Double Integer: RND-
The Round to Lower Double Integer (RND-) instruction converts a 32-bit IEEE floating-point number in accumulator 1 to a 32-bit integer (double integer). The instruction rounds the converted number to the largest whole number less than or equal to the floating-point number that is converted. The following sample program includes an RND- instruction. Figure 12-11 shows how this instruction works.
STL L MD10
Explanation Load the 32-bit IEEE floating-point value in memory double word MD10 into accumulator 1. Convert the 32-bit floating-point number to a 32-bit integer. Round to the largest whole number less than or equal to the floating-point number that is converted and store the result in accumulator 1. Transfer the result to memory double word MD20.
RND
MD20
31 30... L MD10 RND T MD20 MD20 MD10
22...
...0 +100.5 IEEE
+100 integer
31 30... L MD10 RND T MD20 MD20 MD10
22...
...0 -100.5 IEEE
-101 integer
Figure 12-11
Using the RND Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer
12-11
Truncate: TRUNC
The Truncate (TRUNC) instruction converts a 32-bit IEEE floating-point number in accumulator 1 to a 32-bit integer (double integer). The instruction converts the whole number part of the floating-point number. The following sample program includes a TRUNC instruction. Figure 12-12 shows how this instruction works.
STL L MD10
Explanation Load the 32-bit IEEE floating-point value in memory double word MD10 into accumulator 1. Convert the 32-bit floating-point number to a 32-bit integer. Round to the largest whole number less than or equal to the floating-point number that is converted and store the result in accumulator 1. Transfer the result to memory double word MD20.
TRUNC
MD20
31 30... L MD10 TRUNC T MD20 MD20 MD10
22...
...0 +100.5 IEEE +100 integer
31 30... L MD10 TRUNC T MD20 MD20 MD10
22...
...0 -100.5 IEEE -100 integer
Figure 12-12
Using the TRUNC Instruction to Convert an IEEE 32-Bit Floating-Point Number to a 32-Bit Integer
Summary of Number Conversions
Figure 12-13 summarizes number conversions and rounding (see also Sections 12.1 and 12.2).
BCD 3-place 7-place
BTI ITB BTD DTB
Integer 16-bit 32-bit ITD DTR RND, RND+, RND, TRUNC
Floating 32-bit IEEE
Figure 12-13
Overview of Number Conversions and Rounding
12-12
12.3 Reversing the Order of Bytes within Accumulator 1
Description
You can use the following Change Bit Sequence in Accumulator 1 instructions to reverse the order of bytes in the low word of accumulator 1 or in the entire accumulator:
S Change Byte Sequence in Accumulator 1, 16 bits (CAW) S Change Byte Sequence in Accumulator 1, 32 bits (CAD)
CAW CAW inverts the order of bytes in the low word of accumulator 1 (see Figure 12-14).
31... L MD10 CAW T MD20 MD20 MD10
...16 15...
...0
0101 1111 1010 0000 1111 1010 0101 0000
0101 1111 1010 0000 0101 0000 1111 1010
Figure 12-14
Using CAW to Reverse Byte Order in the Low Word of Accumulator 1
CAD
CAD inverts the byte order in all of accumulator 1 (see Figure 12-15).
31... L MD10 MD10
...16 15...
...0
0101 1111 1010 0000 1111 1010 0101 0000
CAD
T MD20 Figure 12-15
MD20
0101 0000 1111 1010 1010 0000 0101 1111
Using CAD to Reverse Byte Order in Accumulator 1
12-13
12.4 Forming Complements and Negating Floating-Point Numbers
Description
Forming the ones complement of a number in the accumulator inverts the number bit by bit, that is, zeros are replaced by ones and ones are replaced by zeros. Forming the twos complement of an integer in the accumulator also inverts the number bit by bit, that is, zeros are replaced by ones and ones are replaced by zeros. Then a +1 is added to the contents of the accumulator. Forming the twos complement of an integer is the same as multiplying the number by a -1. Negating a real number inverts the sign bit. You can use one of the following instructions to form the complement of an integer or to invert the sign of a floating-point number:
Mnemonic INVI Instruction Ones Complement Integer Function This instruction forms the ones complement of the 16-bit value in the low word of accumulator 1. The result is stored in the low word of accumulator 1 (see Figure 12-16). This instruction forms the ones complement of the 32-bit value in accumulator 1. The result is stored in accumulator 1. This instruction forms the twos complement of the 16-bit value in the low word of accumulator 1, that is, it multiplies it by -1. The result is stored in the low word of accumulator 1 (see Figure 12-17). In the status word (see Section 3.4), NEGI sets the CC 1, CC 0, OV and OS bits. This instruction forms the twos complement of the 32-bit value in accumulator 1, that is, it multiplies it by -1. The result is stored in accumulator 1. In the status word (see Section 3.4), NEGI sets the CC 1, CC 0, OV and OS bits. This instruction inverts the sign bit of the 32-bit IEEE floating-point value in accumulator 1 (see Figure 12-18).
INVD
Ones Complement Double Integer Twos Complement Integer
NEGI
NEGD
Twos Complement Double Integer
NEGR
Negate FloatingPoint Number
12-14
Statement List Program L DBW30 INVI T DBW32 Load the value of data word DBW30 into the low word of accumulator 1. Form the ones complement of the value in the low word of accumulator 1. Transfer the contents of the low word of accumulator 1 to data word DBW32. Bit Patterns L DBW30 INVI T DBW32 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 0
Ones Complement Integer 0 1 1 0 0 0 1 1 1
Figure 12-16
Forming the Ones Complement of a 16-Bit Integer
Statement List Program L DBW40 NEGI T DBW42 Load the value of data word DBW40 into the low word of accumulator 1. Form the twos complement of the value in the low word of accumulator 1. Transfer the contents of the low word of accumulator 1 to data word DBW42. Bit Patterns L DBW40 NEGI T DBW42 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 0 23,864 integer
Twos Complement Integer 0 1 1 0 0 1 0 0 0 -23,864 integer
Figure 12-17
Forming the Twos Complement of a 16-Bit Integer
12-15
Decimal value 10.0 Hexadecimal 4 value Bits 31 28 27 1 24 23 2 20 19 0 16 15 0 12 11 0 8 7 0 4 3 0 0
0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign of Mantissa: s (1 bit)
Exponent: e (8 bits) e = 27 + 21 = 130 1.f 2ebias = 1.25 23 = 10.0 [1.25 2(130127) = 1.25 23 = 10.0]
Mantissa or fraction: f (23 bits) f = 22 = 0.25
Statement List Program L DBD62 NEGR T DBD66 Load the value of data double word DBD62 into accumulator 1. Invert the sign of the value in accumulator 1. Transfer the contents of accumulator 1 to data double word DBD66.
L DBD62 0 1 0 0 0 0 0 1 0 0 1 0 NEGR T DBD66 1 1 0 0 0 0 0 1 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Negate Floating-Point Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign of Mantissa (0 = positive, 1 = negative) Figure 12-18 Inverting the Sign of a Floating-Point Number
12-16
Word Logic Instructions

Chapter Overview
Section 13.1 13.2 13.3 Overview 16-Bit Word Logic Instructions 32-Bit Word Logic Instructions Description
13
Page 13-2 13-3 13-6
13-1
13.1 Overview
Description
Word logic instructions combine pairs of words (16 bits) or double words (32 bits) bit by bit according to Boolean logic. Each word or double word must be in one of the two accumulators.
Accumulator Administration
For words, the contents of the low word of accumulator 2 is combined with the contents of the low word of accumulator 1. The result of the combination is stored in the low word of accumulator 1, overwriting the old contents. For double words, the contents of accumulator 2 is combined with the contents of accumulator 1. The result of the combination is stored in accumulator 1, overwriting the old contents.
Influence on Bits of the Status Word
If the result of the logic combination is 0, the CC 1 bit of the status word is reset to 0. If the result of the logic combination is not 0, CC 1 is set to 1. In any case, the CC 0 and OV bits of the status word are reset to 0.
The following instructions are available for performing word logic operations: Mnemonic AW OW XOW Instruction And Word Or Word Exclusive Or Word Function Combines two words bit by bit according to the And truth table Combines two words bit by bit according to the Or truth table Combines two words bit by bit according to the Exclusive Or truth table Combines two double words bit by bit according to the And truth table Combines two double words bit by bit according to the Or truth table Combines two double words bit by bit according to the Exclusive Or truth table
AD
And Double Word
OD
Or Double Word
XOD
Exclusive Or Double Word
Constants as Addresses
An AW, OW, or XOW instruction can use a 16-bit constant as its address. The instruction combines the contents of the low word of accumulator 1 with the 16-bit constant. An AD, OD, or XOD instruction can use a 32-bit constant as its address.
13-2
13.2 16-Bit Word Logic Instructions
Description
The And Word, Or Word, and Exclusive Or Word instructions (AW, OW, XOW) combine pairs of words (16 bits) bit by bit according to Boolean logic. Mnemonic AW Instruction And Word RLO Before Logic Operation 0 0 1 1 0 0 1 1 0 0 1 1 Address 0 1 0 1 0 1 0 1 0 1 0 1 Result in RLO 0 0 0 1 0 1 1 1 0 1 1 0
OW
Or Word
XOW
Exclusive Or Word
Relationship to Accumulators
For the instructions that combine 16-bit words, the contents of the low word of accumulator 2 is combined with the contents of the low word of accumulator 1. The result of the logic combination is stored in the low word of accumulator 1, overwriting the old contents. The contents of the high word of accumulator 1 and both words of accumulator 2 remain unchanged (see Figure 13-1).
Accumulator contents before word logic operation Accumulator 2 31 16 15 III IV Accumulator 1 31 16 15 II I 0 Accumulator contents after word logic operation Accumulator 2 Combination AW, OW, XOW IV Accumulator 1 II III c. I c = combined with III
Figure 13-1
Combining the Contents of the Low Words of Accumulators 2 and 1
13-3
Example of an AW Instruction
The following sample program includes an AW instruction. Figure 13-2 shows how this instruction works.
STL L MW10 L MW20
Explanation Load the contents of memory word MW10 into accumulator 1. Load the contents of memory word mW20 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. The contents of the low word of accumulator 2 are combined bit by bit with the contents of the low word of accumulator 1 according to the AND truth table. The result is stored in the low word of accumulator 1. Transfer the contents of accumulator 1 to memory word MW24.
AW
MW24
15... MW10 MW20 0 1 1 0 1 1 0 0 0 1 1 0 0 1
...8 1 0
7... 1 0 1 1 1 0 0 1 1 0 0 1 1 1
...0 0 1
AND bit by bit MW24 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0
Figure 13-2
Combining Two Words Using the AW Instruction
Combining Accumulator and Constant
An AW, OW, or XOW instruction can use a 16-bit constant as its address. The instruction combines the contents of the low word of accumulator 1 with the 16-bit constant that is indicated in the instruction statement. The result of the combination is stored in the low word of accumulator 1. Accumulator 2 and the high word of accumulator 1 remain unchanged (see Figure 13-3).
Accumulator contents before word logic operation Accumulator 2 31 16 15 IV III Accumulator 1 31 16 15 II I 0 Accumulator contents after word logic operation Accumulator 2 Combination IV III
AW2#, OW2#, Accumulator 1 XOW2# II I c. 2# c = combined with
Figure 13-3
Combining the Low Word of Accumulator 1 with a 16-Bit Constant
13-4
Example of an AW Instruction with Constant
The following sample program includes an AW instruction that makes a logic combination with a 16-bit constant that is indicated in the instruction statement. Figure 13-4 shows how this instruction works.
STL L MW10 AW 2#1010_1010_0101_0101
Explanation Load the contents of memory word MW10 into accumulator 1. The contents of the low word of accumulator 1 are combined bit by bit with 1010_1010_0101_0101 according to the AND truth table. The result is stored in the low word of accumulator 1. Transfer the contents of accumulator 1 to memory word MW24.
MW24
15... MW10 Value of AW statement 0 1 1 0 1 1 0 0 0 1 1 0 0 1
...8 1 0
7... 1 0 1 1 1 0 0 1 1 0 0 1 1 0
...0 0 1
AND Bit by Bit MW24 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0
Figure 13-4
Using an AW Instruction with a 16-Bit Constant
13-5
13.3 32-Bit Word Logic Instructions
Description
The And Double Word, Or Double Word, and Exclusive Or Double Word instructions (AD, OD, XOD) combine pairs of words (32 bits) bit by bit according to Boolean logic. Mnemonic AD Instruction And Double Word RLO Before Logic Operation 0 0 1 1 0 0 1 1 0 0 1 1 Address 0 1 0 1 0 1 0 1 0 1 0 1 Result in RLO 0 0 0 1 0 1 1 1 0 1 1 0
OD
Or Double Word
XOD
Exclusive Or Double Word
Relationship to Accumulators
For the instructions that combine double words, the contents of accumulator 2 is combined with the contents of accumulator 1. The result of the logic combination is stored in accumulator 1, overwriting the old contents. The contents of accumulator 2 remains unchanged (see Figure 13-5).
Accumulator contents before word logic operation Accumulator 2 31 16 15 IV III Accumulator 1 31 16 15 II I 0 Combination AD, OD, XOD IV Accumulator 1 IV c. II III c. I c = combined with III Accumulator contents after word logic operation Accumulator 2
Figure 13-5
Combining the Contents of Accumulators 2 and 1
13-6
Example of an AD Instruction
The following sample program includes an AD instruction. Figure 13-6 shows how this instruction works.
STL L MD10 L MD20
Explanation Load the contents of memory double word MD10 into accumulator 1. Load the contents of memory double word mD20 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. The contents of accumulator 2 are combined bit by bit with the contents of accumulator 1 according to the AND truth table. The result is stored in accumulator 1. Transfer the contents of accumulator 1 to memory double word MD24.
AD
MD24
31... MD10 MD20
...16 15...
...0
0110 1001 1000 0001
1000 0000 1010 0111
1010 1010 1010 1010 0101 0101 0101 0101 AND bit by bit
MD24
0010 1000 1000 0000 0000 0000 0000 0101
Figure 13-6
Using an AD Instruction
Combining Accumulator and Constant
An AD, OD, or XOD instruction can use a 32-bit constant as its address. The instruction combines the contents of accumulator 1 with the 32-bit constant that is indicated in the instruction statement. The result of the combination is stored in accumulator 1. Accumulator 2 remains unchanged (see Figure 13-7).
Accumulator contents before word logic operation Accumulator 2 31 16 15 IV III 0 0 Combination AD, OD, XOD DW#16# IV Accumulator 1 IIc.DW#16#Ic.DW#16# c=combined with Figure 13-7 Combining Accumulator 1 with a 32-Bit Constant III Accumulator contents after word logic operation Accumulator 2
Accumulator 1 31 16 15 II I
13-7
Example of an AD Instruction with Constant
The following sample program includes an AD instruction that makes a logic combination with a 32-bit constant that is indicated in the instruction statement. Figure 13-8 shows how this instruction works.
STL L MD10 AD DW#16#AAAA_5555
Explanation Load the contents of memory double word MD10 into accumulator 1. The contents of accumulator 1 are combined bit by bit with DW#16#AAAA_5555 according to the AND truth table. The result is stored in accumulator 1. Transfer the contents of accumulator 1 to memory double word MD24.
MD24
31... MD10 Value of AD statement
...16 15...
...0
0110 1001 1000 0001 1000 0000 1010 0111 1010 1010 1010 1010 0101 0101 0101 0101 AND bit by bit
MD24
0010 1000 1000 0000 0000 0000 0000 0101 Using an AD Instruction with a 32-Bit Constant
Figure 13-8
13-8
Shift and Rotate Instructions

Chapter Overview
Section 14.1 14.2 Shift Instructions Rotate Instructions Description
14
Page 14-2 14-6
14-1
14.1 Shift Instructions
Shift Instructions
You can use the Shift instructions to move the contents of the low word of accumulator 1 or the contents of the whole accumulator bit by bit to the left or the right. Shifting by n bits to the left multiplies the contents of the accumulator by 2n; shifting by n bits to the right divides the contents of the accumulator by 2n. For example, if you shift the binary equivalent of the decimal value 3 to the left by 3 bits, you end up with the binary equivalent of the decimal value 24 in the accumulator. If you shift the binary equivalent of the decimal value 16 to the right by 2 bits, you end up with the binary equivalent of the decimal value 4 in the accumulator. The number that follows the shift instruction or a value in the low byte of the low word of accumulator 2 indicates the number of bits by which to shift. The bit places that are vacated by the shift instruction are either filled with zeros or with the signal state of the sign bit (a 0 stands for positive and a 1 stands for negative). The bit that is shifted last is loaded into the CC 1 bit of the status word (see Figure 2-7). The CC 0 and OV bits of the status word are reset to 0. You can use jump instructions to evaluate the CC 1 bit. The shift operations are unconditional, that is, their execution does not depend on any special conditions. They do not affect the result of logic operation.
Shift Functions: Unsigned Numbers
The following instruction shift the contents of the low word of accumulator 1 bit by bit to the left or right:
S Shift Left Word (SLW, 16 bits) S Shift Right Word (SRW, 16 bits)
The following instructions shift the entire contents of accumulator 1 bit by bit to the left or right:
S Shift Left Double Word (SLD, 32 bits) S Shift Right Double Word (SRD, 32 bits)
In all cases, the free bit positions are filled with a 0,
Shift Left Word: SLW
The following sample program and Figure 14-1 provide an example of how the SLW instruction works. Table 14-1 provides a summary of all the Shift instructions.
STL L SLW T MW10 6 MW20
Explanation
Load the contents of memory word MW10 into the low word of accumulator 1. Shift the bits of the low word in accumulator 1 six places to the left. Transfer the contents of the low word of accumulator 1 to memory word MW20.
14-2
15... 0 0 0 0 1 1 1
...8 1
7... 0 1 0 1 0 1 0
...0 1
6 places 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0
These five bits are lost. The bit that is shifted out last is stored in the CC 1 bit of the status word. Figure 14-1
The vacated places are filled with zeros.
Shifting Bits of the Low Word of Accumulator 1 Six Bits to the Left
Shift Right Double Word (32 Bits): SRD
The following sample program and Figure 14-2 provide an example of how the SRW instruction works. Table 14-1 provides a summary of all the Shift instructions.
STL L L +3 MD10
Explanation Load the value +3 into accumulator 1. Load the contents of memory double word MD10 into accumulator 1. The old contents of accumulator 1 (+3) is moved to accumulator 2. Shift the bits in accumulator 1 three places to the right. Transfer the contents of accumulator 1 to memory double word MD20.
SRD T MD20
31...
...16 15...
...0
1111 1111 0101 0101 1010 1010 1111 1111 3 places 0001 1111 1110 1010 1011 0101 0101 1111 111 The vacated places are filled with zeros.
The bit that is shifted out last is stored in the CC 1 bit of the status word.
These two bits are lost.
Figure 14-2
Shifting Bits of Accumulator 1 Three Bits to the Right
14-3
Shift Functions: Signed Numbers
The Shift Sign Integer (SSI, 16 bits) instruction shifts the contents of the low word of accumulator 1 bit by bit to the right, including sign, as described in the overview of this chapter: The Shift Sign Double Integer (SSD, 32 bits) instruction shifts the entire contents of accumulator 1 bit by bit to the right, including sign. The shift bit is copied into the free bit positions.
Shift Sign Integer: SSI
The following sample program and Figure 14-3 provide an example of how the SSI instruction works. Table 14-1 provides a summary of all the Shift instructions.
STL L MW10 4
Explanation Load the contents of memory word MW10 into the low word of accumulator 1. Shift the bits in the low word of accumulator 1, including sign, four places to the right. Transfer the contents of the low word of accumulator 1 to memory word MW20.
SSI T
MW20
15... 1 0 1 0 1 1 1
...8 1
7... 0 0 0 0 1 0 1
...0 0
Sign bit 1 1 1 1 1 0 1
4 places 0 1 1 1 1 0 0 0 0 1 0 1 0
The vacated places are filled with the signal state of the sign bit.
The bit that is shifted out last is stored in the CC 1 bit of the status word.
These three bits are lost.
Figure 14-3
Shifting Bits of the Low Word of Accumulator 1 Four Bits to the Right with Sign
14-4
Table 14-1
Overview of Shift Instructions
Instruction
Area Affected
Direction
Indication of Number of Places to Shift In the instruction statement In the low byte of the low word of accumulator 2 In the instruction statement In the low byte of the low word of accumulator 2 In the instruction statement In the low byte of the low word of accumulator 2 In the instruction statement In the low byte of the low word of accumulator 2 In the instruction statement In the low byte of the low word of accumulator 2 In the instruction statement In the low byte of the low word of accumulator 2
Filler for Vacated Places 0 0 0 0 0 0 0 0 Sign bit Sign bit Sign bit Sign bit
Shift Range1 n=0 to 15 0 to 2552 n=0 to 32 0 to 2553 n=0 to 15 0 to 2552 n=0 to 32 0 to 2553 n=0 to 15 0 to 2554 n=0 to 32 0 to 2555
SLW n SLW SLD n SLD SRW n SRW SRD n SRD SSI n SSI SSD n SSD
Low word of accumulator 1 Low word of accumulator 1 Accumulator 1 Accumulator 1 Low word of accumulator 1 Low word of accumulator 1 Accumulator 1 Accumulator 1 Low word of accumulator 1 Low word of accumulator 1 Accumulator 1 Accumulator 1
Left Left Left Left Right Right Right Right Right Right Right Right
1 2 3 4 5
If the number of bits by which to shift or rotate is 0, the instruction is executed like a NOP. For shift numbers greater than 16, the result of the shift function is W#16#0000 and CC 1 = 0. For shift numbers greater than 32, the result of the shift function is DW#16#0000_0000 and CC 1 = 0. For shift numbers greater than 15, the result of the shift function is W#16#0000 and CC 1 = 0 or W#16#FFFF and CC 1 = 1 depending on the sign (0 or 1). For shift numbers greater than 31, the result of the shift function is DW#16#0000_0000 (CC 1 = 0) or DW#16#FFFF_FFFF (CC 1 = 1) depending on the sign of the number of bits to be shifted.
14-5
14.2 Rotate Instructions
Description
You can use the Rotate instructions to rotate the entire contents of accumulator 1 bit by bit to the left or to the right. The Rotate instructions trigger functions that are similar to the shift functions described in Section 14.1. However, the vacated bit places are filled with the signal states of the bits that are shifted out of the accumulator. The number that follows the rotate instruction or a value in the low byte of the low word of accumulator 2 indicates the number of bits by which to rotate. Depending on the instruction, rotation takes place via the CC 1 bit of the status word (see Section 2.2). The CC 0 bit of the status word is reset to 0. The following Rotate instructions are available:
S Rotate Left Double Word (RLD) S Rotate Right Double Word (RRD) S Rotate Accumulator 1 Left via CC 1 (RLDA) S Rotate Accumulator 1 Right via CC 1 (RRDA)
If the number of bits that are rotated is 0, then the instruction is carried out as a Null Operation (NOP).
Table 14-2 Instruction RLD n RLD RRD RRD RLDA RRDA Overview of the Rotate Instructions Rotate via CC 1? No No No No Yes Yes Direction Left Left Right Right Left Right Indication of Number of Places to Shift In the instruction statement In the low byte of the low word of accumulator 2 In the instruction statement In the low byte of the low word of accumulator 2 Shift Range n=0 to 32 0 to 255 0 to 32 0 to 255 1 (fixed) 1 (fixed)
14-6
Rotate Left Double Word: RLD
Table 14-2 provides a summary of all the Rotate instructions. The following sample program and Figure 14-4 provide an example of how the RLD instruction works.
STL L MD10
Explanation Load the contents of memory double word MD10 into accumulator 1. Rotate the bits in accumulator 1 three places to the left. Transfer the contents of accumulator 1 to memory double word MD20.
RLD 3 T MD20
31...
...16 15...
...0
1111 0000 1010 1010 0000 1111 0000 1111 3 places
111
1000 0101 0101 0000 0111 1000 0111 1111
The three bits that are shifted out are inserted in the vacated places.
The last bit shifted is also stored in CC 1.
Figure 14-4
Rotating Bits of Accumulator 1 Three Bits to the Left
Rotate Right Double Word: RRD
The following sample program and Figure 14-5 provide an example of how the RRD instruction works.
STL L L +3 MD10
Explanation Load the value +3 into accumulator 1. Load the contents of memory double word MD10 into accumulator 1. The old contents of accumulator 1 (+3) is moved to accumulator 2. Rotate the bits in accumulator 1 three places to the right. Transfer the contents of accumulator 1 to memory double word MD20.
RRD T MD20
14-7
31...
...16 15...
...0
1010 1010 0000 1111 0000 1111 0101 0101 3 places
1011 0101 0100 0001 1110 0001 1110 1010 101 The three bits that are shifted out are inserted in the vacated places.
Figure 14-5
Rotating Bits of Accumulator 1 Three Bits to the Right
Rotate Accumulator 1 Left via CC 1: RLDA

CC1 X 31...
Figure 14-6 shows an example of how the RLDA instruction works.
...16 15...
...0
1010 1010 0000 1111 0000 1111 0101 0101 1 place
1010 0100 0001 1110 0001 1110 1010 101X
The signal state of the CC 1 bit is loaded into the vacated bit place.
Figure 14-6
Rotating Accumulator 1 One Bit to the Left via the CC 1 Bit of the Status Word
Rotate Accumulator 1 Right via CC 1: RRDA
The RRDA instruction works in a manner similar to the RLDA instruction. The only difference is in the direction of the rotation.
14-8
Data Block Instructions

Chapter Overview
Section 15.1 15.2 15.3 Opening Data Blocks Swapping Data Block Registers Loading Data Block Lengths and Numbers Description
15
Page 15-2 15-2 15-3
15-1
15.1 Opening Data Blocks
Description
You can use the Open a Data Block (OPN) instruction to open a data block as a shared data block or as an instance data block. The program itself can accomodate one open shared data block and one open instance data block at the same time.
Addressing Format
Tables 15-1 and 15-2 lists the addresses and their ranges for the OPN instruction.
Table 15-1 Data Block A Area Addresses of the Open a Data Block Instruction OPN Maximum Address Range according to Addressing Type Direct [DBW] [DIW] [LW] [MW] Memory Indirect
DB DI
1 to 65,535
1 to 65,534
Table 15-2
Addresses of the Open a Data Block Instruction OPN Transferred as Parameter Type of DB Opened DBpara DIpara Address Parameter Format BLOCK_DB
15.2 Swapping Data Block Registers
Description
You can use the Exchange Shared DB and Instance DB (CDB) instruction to exchange data block registers. A shared data block becomes an instance data block and vice versa.
15-2
15.3 Loading Data Block Lengths and Numbers
Description
You can use the following instructions to load the length (in bytes) or the number of a shared data block or an instance data block into accumulator 1:
S Load Length of Shared DB in Accumulator 1 (L DBLG) S Load Number of Shared DB in Accumulator 1 (L DBNO) S Load Length of Instance DB in Accumulator 1 (L DILG) S Load Number of Instance DB in Accumulator 1 (L DINO)
Examples The following sample program illustrates how you can use the L DBLG instruction to jump to the label ERR if the length of a data block is 50 bytes or more. The statement at the label ERR calls FC10, which you have programmed as an appropriate reaction if the length of the data block in question is 50 bytes or more.
STL OPN DB40 L L DBLG +50
Explanation Open shared data block DB40. Load the length of the open data block into accumulator 1. Load the integer +50 into accumulator 1. The old contents of accumulator 1 (the length of the open data block) are moved to accumulator 2. Compare the contents of accumulator 2 (the length of the open data block) to the contents of accumulator 1 (+50). ERR If the length of the data block is greater than or equal to +50, jump to the label ERR. If the length of the data block is less than +50, continue to the next instruction statement. The program continues with an And instruction.
>=I
JC
A = BEU
I 0.0 M 1.0
End the current block, regardless of the result of logic operation. ERR: CALL FC10 FC10 contains an appropriate reaction in the event that the length of DB40 is 50 bytes or more.
15-3
The following sample program illustrates how you can use the L DBNO instruction to check the data block that is presently open in your program to see if it falls into a particular range of data blocks, for example, data block DB190 to data block DB250.
STL L DBNO
Explanation Load into accumulator 1 the number of the data block that is presently open. Load the integer +190 as lower limit into accumulator 1. The old contents of accumulator 1 (the number of the open data block) are moved to accumulator 2. Compare the contents of accumulator 2 (the number of the open data block) to the contents of accumulator 1 (+190). ERR If the number of the data block is less than +190, jump to the label ERR. If the number of the data block is not less than +190, continue to the next instruction statement. Load into accumulator 1 the number of the data block that is presently open. Load the integer +250 as upper limit into accumulator 1. The old contents of accumulator 1 (the number of the open data block) are moved to accumulator 2. Compare the contents of accumulator 2 (the number of the open data block) to the contents of accumulator 1 (+250). ERR If the number of the data block is greater than +250, jump to the label ERR. If the number of the data block is not greater than +250, continue to the next instruction statement. Set the RLO to 1. Assign the RLO to memory bit M 1.0. End the current block, regardless of the result of logic operation.
+190
<I
JC
DBNO
+250
>I
JC
SET = M 1.0 BEU
ERR: CALL FC10 FC10 contains an appropriate reaction in the event that the number of the data block that is currently open does not fall into the range of DB190 to DB250.
15-4
Jump Instructions
Chapter Overview
Section 16.1 16.2 16.3 16.4 16.5 16.6 Overview Unconditional Jump Instructions Conditional Jump Instructions Based on Result of Logic Operation Description
16
Page 16-2 16-3 16-4 16-5 16-6 16-8 Conditional Jump Instructions Based on BR, OV, or OS Bits of the Status Word Conditional Jump Instructions Based on Result in the CC 1 and CC 0 Bits of the Status Word Loop Control
16-1
Logic Control Instructions
16.1 Overview
Instructions
You can use the following Jump and Loop instructions to control the flow of logic, enabling your program to interrupt its linear flow to resume scanning at a different point. The address of a Jump or Loop instruction is a label.
Instruction Explanation Unconditional jump instructions JU JL JC JCN JCB JNB JBI JNBI JO JOS JZ JN JP JM JMZ JPZ JUO LOOP Jump Unconditional Jump to List Conditional jump instructions, condition based on RLO Jump if RLO = 1 Jump if RLO = 0 Jump if RLO = 1 WITH BR Jump if RLO = 0 WITH BR Conditional jump instructions, condition based on result in CC 1 and CC 0 Jump If BR = 1 Jump If BR = 0 Jump If OV = 1 Jump If OS = 1 Conditional jump instructions, condition based on result in CC 1 and CC 0 Jump If Zero Jump If Not Zero Jump If Plus Jump If Minus Jump If Minus or Zero Jump If Plus or Zero Jump If Unordered Loop control Jump if the contents of Accumulator 1 > 0
Although the Master Control Relay instructions also control the flow of logic in a program, they are not included in this chapter. For information on MCR instructions, see Sections 17.4 and 17.5.
Jump Label
A jump label can be the address of a jump instruction or serve as a marker for the destination of a jump instruction. It consists of a maximum of four characters. The first character must be a letter of the alphabet; the other characters can be letters or numbers (for example, SEG3:). When used as a destination marker, the jump label must be closed with a colon. In this case, a statement must follow the jump label (for example, SEG3: NOP 0).
16-2
16.2 Unconditional Jump Instructions

Description You can use the following jump instructions to interrupt the normal flow of your program unconditionally:
S Jump Unconditional (JU) S Jump to List (JL)

Jump Unconditional: JU A Jump Unconditional (JU) instruction in your program interrupts the normal flow of logic control and causes the program to jump to a label (the address of the JU instruction). The label marks the point at which the program should continue. The jump is made regardless of any condition. The Jump to List (JL) instruction is a jump distributor. It is followed by a series of unconditional jumps to labels (see Figure 16-1). Access to the list is in accumulator 1.
Jump to List: JL
Start Load destination: 0 = Jump to SEG0 1 = Jump to SEG1 2 = Jump to GEM 3 = Jump to SEG3 >3 = Jump to LIST
=0
Selection according to Segment Number (jump distributor) =1 =2 =3
L JL >3 JU JU
MB100 LIST SEG0 SEG1 COMM SEG3 COMM
Seg. 0
Seg. 1
Seg. 3
JU JU LIST: SEG0: JU
Jump distributor with length of four
Program Segment 0 JU Common Program SEG1: Program Segment 1 JU SEG3: Program Segment 3 COMM: Common Program COMM COMM
End
Figure 16-1
Controlling the Flow of Logic Control Using the Jump to List Instruction JL
16-3
16.3 Conditional Jump Instructions Founded on Result of Logic Operation

Description The following jump instructions interrupt the flow of logic in your program based on the result of logic operation (RLO) produced by the previous instruction statement:
S Jump If RLO = 1 (JC) S Jump If RLO = 0 (JCN) S Jump If RLO = 1 with BR (JCB): The RLO is saved in the BR bit of the
status word.
S Jump If RLO = 0 with BR (JNB): The RLO is saved in the BR bit of the
status word. Irrespectively of the jump, the following status word bits are described: OR :=0 STA :=1 RLO :=1 FC :=0
Start
I 1.0 = 1 and I 1.1 = 1?
No RLO=1 A Program Section B IF RLO=0 A I1.0 I1.1
Yes RLO=0 Erase MB10
JCN COMM L T 0 MB10 Common Program Section B
COMM: Common Program
End
Figure 16-2
Controlling the Flow of Logic Control Using the Jump If RLO = 0 Instruction JCN
16-4
16.4 Conditional Jump Instructions Founded on BR, OV, or OS Bits of the Status Word
Description The following jump instructions interrupt the flow of logic in your program based on the signal state of a bit in the status word (see Section 2.2). S Jump If BR = 1 with BR (JBI) or Jump If BR = 0 (JNBI) S Jump If OV = 1 ( JO) or Jump If OS = 1 (JOS) The JBI and JNBI instructions reset the OR and FC bits of the status word to 0 and set the STA bit to 1. The JOS instruction resets the OS bit to 0.
Start
Reset OS Bit ODEL: Calculate <MW10>=<MW12>+<MW14><MW16>
JOS ODEL L L + L MW12 MW14 I
Reset OS Bit
Calculate MW16 I MW10 T Section C No Erase <MB10> Result <MW10> v 0 No Section A <MW20> = 10 Section B <MW30> = 17 SECC: Yes
Overflow stored?
Yes
JOS SECC* JPZ SECB L T JU SECB: L T JU L T COMM: Common Program +10 MW20 COMM +17 Section B MW30 COMM 0 MW10 Section C Section A
Common Program
End Figure 16-3
* In this case, do not use the JO instruction. The JO instruction would check only the previous I instruction if an overflow occurred.
Controlling the Flow of Logic Control Using the Jump If OS = 1 Instruction JOS, JP
16-5
16.5 Conditional Jump Instructions Based on Result in the CC 1 and CC 0 Bits of the Status Word
Description
The following jump instructions interrupt the flow of logic in your program based on the result of a calculation:
S Jump If Zero (JZ) S Jump If Not Zero (JN) S Jump If Plus (JP, that is, greater than zero) S Jump If Minus (JM, that is, less than zero) S Jump If Minus or Zero (JMZ, that is, less than or equal to zero) S Jump If Plus or Zero (JPZ, that is, greater than or equal to zero, see
Figure 16-4)
S Jump If Unordered (JUO, that is, if one of the numbers in a floating-point

math operation is not a valid floating-point number)
CC 1 and CC 0 in the Status Word
The status word bits CC 1 and CC 0 are described, irrespectively of the result of the previous operation. The signal states of the CC 1 and CC 0 bits of the status word indicate the conditions shown in Table 16-1.
Table 16-1 Signal State CC 1 0 1 or 0 1 0 0 or 1 0 or 0 1 CC 0 0 0 or 1 0 1 0 or 0 0 or 1 1 Result of Calculat Calculation on =0 <>0 >0 <0 >=0 Jump Instruct Instruction on Tr Triggered ggered JZ JN JP JM JPZ Relationship of CC 1 and CC 0 to Conditional Jump Instructions
<=0 UO (unordered)
JMZ JUO
16-6
Start
Reset OSBit ODEL: Calculate <MW10>=<MW12>+<MW14><MW16>
JOS ODEL L L + L MW12 MW14 I
Reset OSBit
Calculate MW16 I MW10 T Section C No Erase <MB10> Result <MW10> >=0? Yes
Overflow stored?
Yes
JOS SECC* JPZ SECB L T JU +10 MW20 COMM +17 Section B T MW30 COMM 0 MW10 Section C Section A
No Section A <MW20> = 10 Section B
SECB:
JU <MW30> = 17 SECC: L T COMM:
Common Program Common Program * In this case, do not use the JO instruction. The JO instruction would check only the previous I instruction if an overflow happened.
End
Figure 16-4
Controlling the Flow of Logic Control Using the Jump If Plus or Zero Instruction JPZ
16-7
16.6 Loop Control
Description
You can use the Loop (LOOP) instruction to call a program segment multiple times (see Figure 16-5). The Loop instruction decrements the low word of accumulator 1 by 1. Then the value in the low word of accumulator 1 is tested. If it is not 0, a jump is executed to the label indicated in the address of the Loop instruction; otherwise the next instruction is executed.
Providing a Label as Address
You provide the Loop instruction with a label so it knows the point to which it should return in the program. For example, the Loop instruction in the program shown in Figure 22-5 has the label NEXT as its address. This label tells the instruction to return to the statement T MB10 in th program. At this point, the program processes Section A. The Loop instruction returns to the label as many times as you tell it to. You provide this information in the low word of accumulator 1. One way to do this is to set up a loop counter and load it into the accumulator.
Start
Initialize Loop Counter
L Program Section A NEXT: T
+5 MB10
Initialize Loop Counter
Section A Decrement Loop Counter by 1 L MB10
LOOP NEXT Yes Loop Counter <> 0? No End Figure 16-5 Using the Loop Instruction to Call a Program Segment Multiple Times
16-8
Setting Up a Loop Counter
You provide the Loop instruction with a value that indicates how many times you want LOOP to call a particular program segment. The Loop instruction interprets the loop counter as a WORD data type. Table 16-2 provides information about the two possible formats for a loop counter.
Table 16-2 Value Type Integer Word Possible Format for a Loop Counter Value Range 1 to 65,535 (positive value only) W#16#0001 to W#16#FFFF Data Type WORD WORD Memory Area I, Q, M, D, L I, Q, M, D, L
Using the Loop Instruction Efficiently
In order to avoid running a loop more times than is necessary, you need to be aware of the following characteristics of the Loop instruction:
S If you initialize the loop counter with a 0, the loop is executed 65,535
times.
S You should avoid initializing the loop counter with a negative number.
16-9
16-10
Program Control Instructions

Chapter Overview
Section 17.1 17.2 17.3 17.4 17.5 17.6 Description Parameter Assignment when Calling FCs and FBs Calling Functions and Function Blocks with CALL Calling Functions and Function Blocks with CC and UC Working with Master Control Relay Functions Master Control Relay Instructions Ending Blocks
17
Page 17-2 17-3 17-7 17-10 17-11 17-16
17-1
17.1 Parameter Assignment when Calling FCs and FBs
Terms
When calling blocks that require parameters the terms formal parameters and actual parameters play an important role. A formal parameter is a parameter whose name and data type are assigned and declared (for example, as INPUT, OUTPUT parameters) when the block is created. When a block is called in the Incremental Editor (for example CALL SFC31), STEP 7 automatically displays a list of all the formal parameters. The next step is to assign actual parameters to the formal parameters. An actual parameter is a parameter which functions and function blocks use during the actual run time of the user program. The following diagram shows the call of SFC31 QRY_TINT (Query Time-of-Day Interrupt) in STL. STL Representation
CALL SFC 31 OB_NO := 10 RET_VAL:= MW 22 STATUS := MW 100
Actual parameters Formal parameters
17-2
17.2 Calling Functions and Function Blocks with CALL
Description
You can use the Call (CALL) instruction to call functions (FCs) and function blocks (FBs) that you have created for your program or that you have received as standard functions and standard function blocks from Siemens. The Call instruction calls the FC or FB that you indicate as an address regardless of the result of logic operation or any other condition. When you use the Call instruction to call a function block, you must supply the function block with an instance data block (instance DB) or declare it as a local instance. The instance data block stores all the static variables and actual parameters of the function block. If you need information on how to program a function or a function block, or how to work with their parameters, see the STEP 7 Online Help.
Formal Parameters and Actual Parameters
When calling a function (FC) or a function block (FB), you must assign corresponding actual parameters to the declared formal parameters. The actual parameter that is specified when a function block is called must have the same data type as the formal parameter.
Specifying the Actual Parameters
The actual parameters used when a function (FC) or function block (FB) is called are generally specified symbolically. Absolute addressing of actual parameters is possible only for an address whose maximum size is a double word (for example, I 1.0, MB2, QW4, ID0). When you call a function, all formal parameters must be supplied with actual parameters. You only need to declare the actual parameters when these are different to the parameters of the previous call (actual parameters remain stored in the instance data block after the processing of the function block has been completed). When you call a function block, the Call instruction copies one of the following items into the instance data block of the function block, depending on the data type of the actual parameter and on the declaration of the formal parameter (IN, OUT, IN_OUT):
S The value of the actual parameter S A pointer to the address of the actual parameter S A pointer to the L stack of the calling block where the value of the actual
parameter has been buffered
17-3
Calling an FB with Instance DB and Block Parameters
The call can take place once the following details are entered:
S The name of the function block S The name of the instance data block and S The parameters (if the actual parameter is a data block, the complete
absolute address must always be specified, for example DB1.DBW2). The call uses either with an absolute or a symbolic address. Absolute Call: CALL FBx,DBy (pass parameters); x = block number y = data block number Symbolic Call: CALL fbname,datablockname (pass parameters); fbname = symbolic block name datablockname = symbolic data block name
Examples
The following example shows the call of function block FB40 with instance data block DB41. In this example, the formal parameters have the following data types: IN1: BOOL IN2: WORD OUT1: DWORD
STL CALL IN1:= IN2:= OUT1:= L FB40,DB41 I1.0 MW2 MD20 MD20
Explanation Call of FB40 with instance data block DB41. IN1 (formal parameter) is supplied with I 1.0 (actual parameter). IN2 (formal parameter) is supplied with MW2 (actual parameter). OUT1 (formal parameter) is supplied with MD20 (actual parameter). With this instruction, the program accesses the formal parameter OUT1.
The following example shows the call of function block FB50 with instance data block DB51. In this example, the formal parameters have the following data types: IN10: BOOL OUT11: STRUCT V1: BOOL V2: INT END_STRUCT
17-4
STL CALL IN10:= FB50,DB51 I1.0
Explanation Call of FB50 with instance data block DB51. IN10 (formal parameter) is supplied with I 1.0 (actual parameter). Here it is not possible to specify an absolute actual parameter (for example, MW10) because the formal parameter OUT11 was defined as a structure. Instead, the symbolic actual parameter ACTPA11 is specified. Please note that ACTPA11 has the same structure as the formal parameter OUT11.
OUT11:= ACTPA11
Access to the values of the structure OUT11 in FB50 would be made as follows:
STL A L OUT11.V1 OUT11.V2
Explanation Perform an AND logic operation on the bit OUT11.V1. Load word OUT11.V2 into accumulator 1.
Calling Multiple Instances
S The instance name (= name of a static variable of the type FB z) and S The Parameters
The call always has a symbolic designation. CALL Instance Name (pass parameters);
STL
Explanation
FUNCTION_BLOCK FB 11 Source file VAR loc_inst : FB 10; Declaration of a multiple instance with data type FB10 END_VAR BEGIN NETWORK CALL #loc_inst ( Call of the multiple instance with syntax in_bool := M Parameter pass 0.0); (in_bool in this case is a variable declared in FB10)
17-5
Calling an FC with Block Parameters
S The name of the fucntion block and S The parameters

The call is addressed either with an absolute or a symbolic name. Absolute Call: CALL FCx (pass parameters); x = block number Symbolic Call: CALL fcname (pass parameters); fcname = symbolic block name
Example
The following example shows the call of function FC80 with block parameters. In this example, the formal parameters have the following data types: INC1: BOOL INC2: INT OUT: WORD
STL CALL FC80 INC1:= M 1.0 INC2:= IW2 OUT:= QW4
Explanation Call FC80. INC1 (formal parameter) is supplied with M 1.0 (actual parameter). INC2 (formal parameter) is supplied with IW2 (actual parameter). OUT (formal parameter) is supplied with QW4 (actual parameter).
Calling an FC That Delivers a Return Value
You can create a function (FC) that delivers a return value (RET_VAL). For example, if you want to create a floating-point math function, you can use this return value as an output for the result of your function. When you call this function in your program, you provide the output RET_VAL with a double word location to accommodate the 32-bit result of your floating-point math function.
17-6
17.3 Calling Functions and Function Blocks with CC and UC
Description
You can use the following instructions to call functions (FCs) and function blocks (FBs) that you have created for your program in the same way as using the Call instruction. Using these instructions, you cannot transfer parameters.
S Conditional Call (CC): Calls the function or function block that you
indicate as an address if the result of logic operation is 1.
S Unconditional Call (UC): Calls the function or function block that you
indicate as an address regardless of the result of logic operation or any other condition. It is not possible for function blocks which are called with either a CC or a UC instruction to have associated data blocks.
Addressing Format
A CC or UC instruction can call a function (FC) or a function block (FB) using direct or memory indirect addressing or via an FC or FB transferred as a parameter (see Tables 17-1 and 17-2). The address is FC plus the number of the FC.
Table 17-1 FC or FB Part of Address FC FB Addresses of CC and UC Instructions: Direct and Indirect Addressing Maximum Range of Address Number according to Addressing Type Direct [DBW] [DIW] [LW] [MW] Memory Indirect
0 to 65,535
0 to 65,534
Table 17-2
Addresses of CC and UC Instructions: FC Transferred as Parameter Address Parameter Data Types BLOCK_FC 1 BLOCK_FB 1
Name of the formal parameter or a symbolic name

1
Parameters of type BLOCK_FC or BLOCK_FB cannot be used with the CC command in FCs and FBs.
Example
To call an FC that you had created and given the number 12, you would use one of the following instructions, depending on whether you want the call to be conditional or not: CC FC12 (Call FC12 if the RLO is 1.) UC FC12 (Call FC12 no matter what the RLO is.)
17-7
Assigning Actual Parameters
Depending on the data type there are various ways to assign actual parameters to the formal parameters when you call a function or a function block. The following table is compiled according to the length of the data type.
Table 17-3
Assigning Actual Parameters
Data Type of Formal F l Parameter P t
Example of Assigning an Actual Parameter Direct Input (Value) TRUE Input of a Shared Data Element M 100.0 I 0.0 Q 0.0 DBX 3.0 Symbolic Input1 #OK_BIT
BOOL (Bit)
BYTE (Byte)
B#16#1F
MB 100 IB 0 QB 0
#TYP_BYTE
CHAR WORD (Word)
K W#16#1F12 2#0001_1111_0001_0010 C#32 B#(5,25)
DBB 1 MW 100 IW 0 QW 0 DBW 2
#TYP_CHAR #TYP_WORD
INT (Integer)
27 25
#TYP_INT
S5TIME (S5 Time) DATE (IEC Date) DWORD (Double Word)
S5T#10MS D#19951224 DW#16#FFFF_0F02 2#0001_1111_0001_0010_0001 _1111_0001_0010 B#(5,4,59,8) MD 100 ID 0 QD 0 DBD 4
#TYP_S5_TIME #TYP_DATE #TYP_DWORD
DINT (Double Integer) REAL (FloatingPoint Number) TIME (IEC Time) TIME_OF_DAY (IEC Time-of-Day)
L#170 L#-350 1.23 T#20MS TOD#23:59:12.3
#TYP_DINT
#TYP_REAL #TYP_TIME #TYP_TOD
17-8
Table 17-3
Assigning Actual Parameters, continued
Data Type of Formal Parameter
Example of Assigning an Actual Parameter Direct Input (Value) Not possible (Variable must be declared, for example, temporary variable) P#M0.0 BYTE20
20 bytes 2 ... ... from bit memory 0.0 3 Prefix for ANY pointer
Input of a Shared Data Element
Symbolic Input1 #TYP_8_BYTE
DATE_AND_TIME (IEC Date and Time)
ANY (Data type of any type and size)
E 0.0 MB 5 AW 2 (Use of any STEP 7 shared addresses possible)
#TYP_ANYTYP (Declaration of arrays and structures)
P#DB58.DBX16.0 BYTE14
14 bytes 2 ... ... in DB58 from data bit 16.0 3 Prefix for ANY pointer
1
2 3
Prerequisite: In the case of shared data, the name (= symbol) must be declared in the symbol table before it can be used as an actual parameter. In the case of local data, the name (= symbol) must be declared in the declaration table of the block before it can be used as an actual parameter. Local data symbols must be preceded by a hash #. Length specification can include elementary data types, for example BOOL, BYTE, WORD or DWORD or complex types, for example DATE_AND_TIME. Always enter a bit address; in length specifications enter 0 as the bit address (exception: BOOL).
Conditional Call in STL
In order to call an SFC conditionally, you can follow a sequence similar to the following:
STL A #OK_BIT_MEMORY JCNB m001 CALL SFC 28 OB_NO := 10 SDT := #OUT_TIME_DATE PERIOD := W#16#1201 RET_VAL := MW 200 m001: A BR = M 202.3
Explanation Condition for the call If the condition is not fulfilled (RLO=0), the call of the SFC is jumped and the RLO in the status bit is saved.
Check status bit BR
17-9
17.4 Working with Master Control Relay Functions
Description
The Master Control Relay (MCR) is an American relay ladder logic master switch for energizing and de-energizing power flow (current path). A de-energized current path corresponds to an instruction sequence that writes a zero value instead of the calculated value, or, to an instruction sequence that leaves the existing memory value unchanged. Operations triggered by the following bit logic and transfer instructions are dependent on the MCR:
S = S S S R S T (used with byte, word, or double word)

The T instruction used with byte, word, or double word, and the = instruction write a 0 to the memory if the MCR is 0. The S and R instructions leave the existing value unchanged.
Table 17-4 Signal State of MCR 0 Writes 0 (Imitates a relay that falls to its quiet state when voltage is removed) 1 Normal execution Operations Dependent on MCR and How They React to Its Signal State = S or R Does not write (Imitates a latching relay that remains in its current state when voltage is removed) Normal execution Writes 0 (Imitates a component that, on loss of voltage, produces a value of 0) Normal execution T
17-10
17.5 Master Control Relay Instructions
Overview
You can use the following statements to implement a master control relay:
S MCRA S MCRD S MCR( S )MCR

Description: MCRA, MCRD
Activate MCR Area Deactivate MCR Area Save RLO in MCR Stack, Begin MCR Area End MCR Area
The following instructions activate or deactivate an MCR area, that is, they specify which instructions in your program depend on the MCR (see also Figure 17-1):
S Activate MCR Area: MCRA S Deactivate MCR Area: MCRD

The instructions that are programmed between the MCRA and the MCRD statements depend on the signal state of the MCR bit. The instructions that are programmed outside an MCRA-MCRD sequence do not depend on the signal state of the MCR bit. If an MCRD instruction is missing, the instructions programmed between an MCRA instruction and a BEU instruction depend on the MCR bit (see Figure 17-1). You must program the MCR dependency of functions (FCs) and function blocks (FBs) in the blocks themselves, that is, if such a function or function block is called from an MCRA-MCRD sequence, all the commands within that sequence are not automatically dependent on the MCR bit. To make the instructions in a called block dependent on the MCR bit, you must use the MCRA instruction in the block that is called. Danger Never use the MCR instruction as an emergency off or personnel safety device.
17-11

OB1 MCRA

FBx MCRA CALL FCy

FCy MCRA

MCRD CALL FBx MCRA BEU

MCRD
BEU
Instructions do not depend on the MCR bit Instructions depend on the MCR bit
Figure 17-1
Activating and Deactivating a Master Control Relay Area
17-12
Description: MCR(, )MCR
The following instructions turn the Master Control Relay function on and off:
S Save RLO in MCR Stack, Begin MCR: MCR( S End MCR: )MCR
You can nest MCR( and )MCR instructions. The maximum nesting depth is eight, that is, you can have a maximum of eight MCR( instructions in sequence before you insert an )MCR instruction. You must program an equal number of MCR( and )MCR instructions (see Figure 17-3). When MCR( instructions are nested, the MCR bit of the deeper nesting levels is formed. To form this MCR bit, the MCR( instruction combines the current RLO with the current MCR bit according to the And truth table. The )MCR instruction terminates a nesting level by restoring the MCR bit from the higher level. The )MCR instruction of the highest level sets the MCR bit to 1. If you use MCR( and )MCR in your program, you must always use them in pairs.
Example
Figure 17-2 shows how to implement a Master Control Relay. If the MCR bit is 1, then the MCR contact is closed. The signal states of outputs Q 4.0 and Q 4.1 are calculated according to the signal state of inputs I 1.0 to I 1.3 and their logic combinations. If the MCR bit is 0, then the MCR contact is opened. The outputs Q 4.0 and Q 4.1 are reset to 0, regardless of the signal states of inputs I 1.0 to I 1.3.
STL MCR contact
Relay Logic Diagram
MCRA A I 2.0 MCR( O I 1.0 O I 1.1 = Q 4.0 A I 1.2 A I 1.3 = Q 4.1 )MCR MCRD
Power rail I 2.0
I 1.0
I 1.1
I 1.2 I 1.3
Q 4.0 MCR coil Master Control Relay implemented with the MCR( and )MCR instructions
Q 4.1
Area which is controlled by the MCR (Master Control Relay), implemented with MCRA and MCRD instructions
Figure 17-2
Implementation of a Master Control Relay
17-13
Figure 17-3 shows the nesting application of the instructions.
STL
Signal State
Result of Check
RLO
MCR Bit of Level 1 2 3
MCRA A I 1.1 MCR ( A I 1.2 MCR ( A I 1.3 MCR (
1 1 0
1 1 0
1 1
*
1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 **
S M 1.0 )MCR
This bit (M 1.0) remains unchanged regardless of any previous logic string because the MCR bit = 0.
S M 1.1 )MCR
This bit (M 1.1) is changed due to the previous logic string and the function of the S instruction because the MCR = 1.
)MCR MCRD
The MCR bit of the deeper nesting level is formed. To form this MCR bit, the MCR( instruction combines the current RLO with the MCR bit of the current nesting level according to the And truth table. When the )MCR instruction ends a nesting level, the instruction restores the MCR bit of the next higher level.
**
Figure 17-3
Nesting Application of MCR Instructions
17-14
Important Notes on Using MCR Functions

Take care with blocks in which the Master Control Relay was activated with MCRA:
S If the MCR is deactivated, the value 0 is written by all assignments in

program segments between (MCR<) and (MCR>).
S The MCR is deactivated if the RLO was =0 before an (MCR<) instruction. Danger PLC in STOP or undefined runtime characteristics! The compiler also uses write access to local data behind the temporary variables defined in VAR_TEMP for calculating addresses. Formal parameter access S Access to components of complex FC parameters of the type STRUCT, UDT, ARRAY, STRING S Access to components of complex FB parameters of the type STRUCT, UDT, ARRAY, STRING from the IN_OUT area in a version 2 block. S Access to parameters of a version 2 function block if its address is greater than 8180.0. S Access in a version 2 function block to a parameter of the type BLOCK_DB opens DB0. Any subsequent data access sets the CPU to STOP. T 0, C 0, FC0 or FB0 are always used for TIMER, COUNTER, BLOCK_FC, and BLOCK_FB. Parameter passing
S Calls in which parameters are transferred.

KOP/FUP S T branches and midline outputs in Ladder or FBD starting with RLO=0.
Remedy: Free the above commands from their dependence on the MCR: 1. Deactivate the Master Control Relay using the Master Control Relay Deactivate instruction before the statement or network in question. 2. Activate the Master Control Relay again mit Master Control Relay Activate instruction after the statement or network in question.
17-15
17.6 Ending Blocks
Description
A Block End instruction is by itself a programming statement that terminates the scanning of a block. You can use either of the following types of Block End instructions to end a block:
S Block End Unconditional (BEU): This instruction ends scanning in the

current block and returns control to the block that called the one that has been terminated. When the program encounters a BEU instruction, it terminates the current block, regardless of the result of logic operation.
S Block End Conditional (BEC): This instruction ends scanning in the

current block and returns control to the block that called the one that has been terminated. When the program encounters a BEC instruction, it terminates the current block only if the result of logic operation is 1 (RLO = 1). If the RLO is 0, the program does not execute the Block End Conditional (BEC) statement. The RLO is set to 1 and program scanning continues within the current block.
17-16
Appendix
Alphabetical Listing of Instructions Programming Examples Source Files Examples and Reserved Key Words References
A B C D
Q-2
Alphabetical Listing of Instructions

Chapter Overview
Section A.1 A.2 Description Listing with (German) SIMATIC and International Mnemonics Alphabetical Listing with International Names
A
Page A-2 A-12
A-1
A.1
Listing with (German) SIMATIC and International Mnemonics

Table A-1 provides an alphabetical listing of the mnemonic abbreviations of the statement list instructions. Next to each German abbreviation are the equivalent international abbreviation, the full international name and the page on which the instruction is explained.
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations International Abbreviation + = ) +AR1 +AR2 +D -D *D /D ==D +I -I *I /I ==I +R -R *R /R ==R ABS ACOS ASIN ATAN OPN BEU BEC BLD BTD BTI CALL Name Add Integer Constant (8, 16, 32-Bit) Assign Nesting Closed Add Accumulator 1 to Address Register 1 Add Accumulator 1 to Address Register 2 Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) Subtract Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit) Divide Accumulator 2 by Accumulator 1 as Doubel Integer (32-Bit) Compare Double Integer (32-Bit) >, <, >=, <=, ==, <> Add Accumulator 1 and Accumulator 2 as Integer (16-Bit) Subtract Accumulator 1 from Accumulator 2 as Integer (16-Bit) Multiply Accumulator 1 by Accumulator 2 as Integer (16-Bit) Divide Accumulator 2 by Accumulator 1 as Integer (16-Bit) Compare Integer (16-Bit) >, <, >=, <=, ==, <> Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP) Subtract Accumulator 1 from Accumulator 2 as Real (32-Bit IEEE FP) Multiply Accumulator 1 by Accumulator 2 as Real (32 Bit IEEE FP) Divide Accumulator 2 by Accumulator 1 as Real (32-Bit IEEE FP) Compare Real >, <, >=, <=, ==, <> Absolute Value of a Real (32-Bit IEEE FP) Arc Cosine of a Floating-Point Number (32-Bit IEEE FP) Arc Sine of a Floating-Point Number (32-Bit IEEE FP) Arc Tangent of a Floating-Point Number (32-Bit IEEE FP) Call a Data Block Block End Unconditional Block End Conditional Program Display Instruction BCD to Double Integer (32-Bit) BCD to Integer (16-Bit) Call Page No. 9-6 5-24 5-14 4-7 4-7 9-2 9-2 9-2 9-2 17-3 9-2 9-2 9-2 9-2 17-3 10-2 10-2 10-2 10-2 17-5 10-6 10-7 10-7 10-7 21-2 17-16 17-16 4-2 18-4 18-2 17-3
SIMATIC Abbreviation + = ) +AR1 +AR2 +D -D *D /D ==D +I -I *I /I ==I +R -R *R /R ==R ABS ACOS ASIN ATAN AUF BEA BEB BLD BTD BTI CALL
A-2
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont. International Abbreviation CC CLR COS DEC DTB DTR ENT EXP FN FP FR FR INC INVD INVI ITB ITD L L L L L L L Conditional Call Clear RLO (= 0) Cosine of a Floating-Point Number (32-Bit IEEE FP) Decrement Accumulator 1 Double Integer (32-Bit) to BCD Double Integer (32-Bit) to Real (32-Bit IEEE FP) Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3 Exponential Value of a Floating-Point Number (32-Bit IEEE FP) to Base E Edge Negative Edge Positive Enable Counter (Free, FR C 0 to C 255) Enable Timer (Free, FR T 0 to T 255) Increment Accumulator 1 Ones Complement Double Integer (32-Bit) Ones Complement Integer (16-Bit) Integer (16-Bit) to BCD Integer (16-Bit) to Double Integer (32-Bit) Load Load Length of Shared Data Block into Accumulator 1 (L DBLG) Load Number of Shared Data Block into Accumulator 1 (L DBNO) Load Length of Instance Data Block into Accumulator 1 (L DILG) Load Number of Instance Data Block into Accumulator 1 (L DINO) Load Status Word into Accumulator 1 (L STW) Load Current Timer Value into Accumulator 1 as Integer (where the number of the current timer can be in the range of 0 to 255, for example: L T 32) Load Current Counter Value into Accumulator 1 as Integer (where the number of the current counter can be in the range of 0 to 255, for example: L C 15) Load Address Register 1 from Accumulator 1 (if no address is indicated) Load Address Register 1 from ... (from address indicated) Load Address Register 1 from Address Register 2 (LAR1 AR2) Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit) Load Address Register 2 from Accumulator 1 (if no address is indicated) Name Page No. 17-7 5-26 10-7 4-6 12-6 12-7 4-3 10-12 5-17 5-16 6-5 7-3 4-6 12-14 12-14 12-5 12-6 8-3 8-12 15-2 8-12 8-12 15-2 8-12 15-2 8-6 8-7
SIMATIC Abbreviation CC CLR COS DEC DTB DTR ENT EXP FN FP FR FR INC INVD INVI ITB ITD L L L L L L L
7-6 8-8 8-11 8-11 8-11 8-11 8-11
LAR1 LAR1 LAR1 LAR1 LAR2
LAR1 LAR1 LAR1 LAR1 LAR2
A-3
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont. International Abbreviation LAR2 LAR2 LC Name Load Address Register 2 from ... (from address indicated) Load Address Register 2 with Double Integer (32-Bit, LAR2 P#area byte.bit) Load Current Counter Value into Accumulator 1 as BCD (where the number of the current counter can be in the range of 0 to 255, for example: LC C 15) Load Current Timer Value into Accumulator 1 as BCD (where the number of the current timer can be in the range of 0 to 255, for example: LC T 32) Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 3 Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP) Loop Save RLO in MCR Stack, Begin MCR Restore RLO, End MCR Activate MCR Area Deactivate MCR Area Division Remainder Double Integer (32-Bit) Twos Complement Double Integer (32-Bit) Twos Complement Integer (16-Bit) Negate Real Number Null Operation 0 Null Operation 1 Negate RLO Or Or with Nesting Open Or Double Word (32-Bit) Or Not Or Not with Nesting Open Or Word (16-Bit) Accumulator 1 <--- Accumulator 2, Accumulator 2 <--- Accumulator 3, Accumulator 3 <--- Accumulator 4 Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3, Accumulator 1 ---> Accumulator 2 Reset Reset Counter (where the current counter can have a number in the range of 0 to 255, for example: R C 15) Reset Timer (where the current timer can have a number in the range of 0 to 255, for example: R T 32) Rotate Left Double Word (32-Bit) Rotate Accumulator 1 Left via CC 1 (32-Bit) Page No. 8-11 8-11 8-9
SIMATIC Abbreviation LAR2 LAR2 LC
LC
LC
7-7 8-9 4-3 10-11 16-8 17-11 17-11 17-11 17-11 9-5 12-14 12-14 12-14 4-2 4-2 5-26 5-10 5-14 13-6 5-8 5-14 13-3 4-2 4-2 5-22 6-5 7-4 14-8 14-6
LEAVE LN LOOP MCR( )MCR MCRA MCRD MOD NEGD NEGI NEGR NOP 0 NOP 1 NOT O O( OD ON ON( OW POP PUSH R R R RLD RLDA
LEAVE LN LOOP MCR( MCR) MCRA MCRD MOD NEGD NEGI NEGR NOP 0 NOP 1 NOT O O( OD ON ON( OW POP PUSH R R R RLD RLDA
A-4
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont. International Abbreviation RND RND+ RNDRRD RRDA S S SF SAVE SD SET SP SIN SLD SLW JU JC JCB JBI JNBI JCN JNB JL JM JMZ JN JO JP JPZ JOS JUO JZ SQR SQRT SRD SRW Round Round to Upper Double Integer Round to Lower Double Integer Rotate Right Double Word (32-Bit) Rotate Accumulator 1 Right via CC 1 (32-Bit) Set Set Counter Preset Value (where the current counter can have a number in the range of 0 to 255, for example: S C 15) Off-Delay Timer Save RLO in BR Register On-Delay Timer Set RLO (= 1) Pulse Timer Sine of a Floating-Point Number (32-Bit IEEE FP) Shift Left Double Word (32-Bit) Shift Left Word (16-Bit) Jump Unconditional Jump if RLO = 1 Jump if RLO = 1 with BR Jump if BR = 1 Jump if BR = 0 Jump if RLO = 0 Jump if RLO = 0 with BR Jump to Labels Jump if Minus Jump if Minus or 0 Jump if Not 0 Jump if OV = 1 Jump if Plus Jump if Plus or 0 Jump if OS = 1 Jump if Unordered Jump if 0 Square of a Floating-Point Number (32-Bit IEEE PF) Square Root of a Floating-Point Number (32-Bit IEEE PF) Shift Right Double Word (32-Bit) Shift Right Word (16-Bit) Name Page No. 12-9 12-10 12-11 14-8 14-6 5-21 7-3 6-15 5-26 6-11 5-26 6-7 10-7 14-2 14-2 16-3 16-4 16-4 16-4 16-4 16-4 16-4 16-3 16-6 16-6 16-6 16-5 16-6 16-6 16-5 16-6 16-6 10-9 10-9 14-3 14-2
SIMATIC Abbreviation RND RND+ RNDRRD RRDA S S SA SAVE SE SET SI SIN SLD SLW SPA SPB SPBB SPBI SPBIN SPBN SPBNB SPL SPM SPMZ SPN SPO SPP SPPZ SPS SPU SPZ SQR SQRT SRD SRW
A-5
Table A-1
Alphabetical Listing with the SIMATIC and the International Mnemonic Abbreviations, cont. International Abbreviation SS SSD SSI SE T T CAD TAK TAN CAR TAR1 TAR1 TAR1 TAR2 TAR2 CAW CDB TRUNC A A( UC AD AN AN( AW X X( XN XN( XOD XOW CD CU Retentive On-Delay Timer Shift Sign Double Integer (32-Bit) Shift Sign Integer (16-Bit) Extended Pulse Timer Transfer Transfer Accumulator 1 to Status Word (T STW) Change Byte Sequence in Accumulator 1 (32-Bit) Toggle Accumulator 1 with Accumulator 2 Tangent of a Floating-Point Number (32-Bit IEEE FP) Exchange Address Register 1 with Address Register 2 Transfer Address Register 1 to Accumulator 1 (if no address is indicated) Transfer Address Register 1 to ... (to address indicated) Transfer Address Register 1 to Address Register 2 (T AR1 AR2) Transfer Address Register 2 to Accumulator 1 (if no address is indicated) Transfer Address Register 2 to ... (to address indicated) Change Byte Sequence in Accumulator 1 (16-Bit) Exchange Shared Data Block and Instance Data Block Truncate And And with Nesting Open Unconditional Call And Double Word (32-Bit) And Not And Not with Nesting Open And Word (16-Bit) Exclusive Or Exclusive Or with Nesting Open Exclusive Or Not Exclusive Or Not with Nesting Open Exclusive Or Double Word (32-Bit) Exclusive Or Word (16-Bit) Counter Down Counter Up Name Page No. 6-13 14-4 14-4 6-9 8-3 8-6 12-13 4-2 10-7 8-11 8-11 8-11 8-11 8-11 8-11 12-13 15-2 12-12 5-10 5-14 17-7 13-6 5-8 5-14 13-3 5-10 5-14 5-8 5-14 13-6 13-3 7-5 7-5
SIMATIC Abbreviation SS SSD SSI SV T T TAD TAK TAN TAR TAR1 TAR1 TAR1 TAR2 TAR2 TAW TDB TRUNC U U( UC UD UN UN( UW X X( XN XN( XOD XOW ZR ZV
A-6
Table A-2 provides an alphabetical listing of the mnemonic abbreviations of the statement list instructions. Next to each international abbreviation are the equivalent (German) SIMATIC abbreviation, the full international name and the page on which the instruction is explained.
Table A-2 Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations SIMATIC Abbreviation + = ) +AR1 +AR2 +D -D *D /D ==D +I -I *I /I ==I +R -R *R /R ==R U U( ABS ACOS UD UN UN( ASIN ATAN UW BEB BEA Name Add Integer Constant (8, 16, 32-Bit) Assign Nesting Closed Add Accumulator 1 to Address Register 1 Add Accumulator 1 to Address Register 2 Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) Subtract Accumulator 1 from Accumulator 2 as Double Integer (32-Bit) Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit) Divide Accumulator 2 by Accumulator 1 as Double Integer (32-Bit) Compare Double Integer (32-Bit) >, <, >=, <=, ==, <> Add Accumulator 1 and Accumulator 2 as Integer (16-Bit) Subtract Accumulator 1 from Accumulator 2 as Integer (16-Bit) Multiply Accumulator 1 by Accumulator 2 as Integer (16-Bit) Divide Accumulator 2 by Accumulator 1 as Integer (16-Bit) Compare Integer (16-Bit) >, <, >=, <=, ==, <> Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP) Subtract Accumulator 1 from Accumulator 2 as Real (32-Bit IEEE FP) Multiply Accumulator 1 by Accumulator 2 as Real (32-Bit IEEE FP) Divide Accumulator 2 by Accumulator 1 as Real (32-Bit IEEE FP) Compare Real >, <, >=, <=, ==, <> And And with Nesting Open Absolute Value of a Real (32-Bit IEEE FP) Arc Cosine of a Floating-Point Number (32-Bit IEEE FP) And Double Word (32-Bit) And Not And Not with Nesting Open Arc Sine of a Floating-Point Number (32-Bit IEEE FP) Arc Tangent of a Floating-Point Number (32-Bit IEEE FP) And Word (16-Bit) Block End Conditional Block End Unconditional Page No. 15-6 11-24 11-14 10-7 10-7 15-2 15-2 15-2 15-2 17-3 15-2 15-2 15-2 15-2 17-3 16-2 16-2 16-2 16-2 17-5 11-10 11-14 16-6 16-7 19-6 11-9 11-14 16-7 16-7 19-3 23-15 23-15
International Abbreviation + = ) +AR1 +AR2 +D -D *D /D ==D +I -I *I /I ==I +R -R *R /R ==R A A( ABS ACOS AD AN AN( ASIN ATAN AW BEC BEU
A-7
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont. SIMATIC Abbreviation BLD BTD BTI TAD CALL TAR TAW CC ZR TDB CLR COS ZV DEC DTB DTR ENT EXP FN FP FR FR INC INVD INVI ITB ITD SPBI SPB SPBB SPBN SPL SPM SPMZ SPN SPBNB Program Display Instruction BCD to Double Integer (32-Bit) BCD to Integer (16-Bit) Change Byte Sequence in Accumulator 1 (32-Bit) Call Exchange Address Register 1 with Address Register 2 Change Byte Sequence in Accumulator 1 (16-Bit) Conditional Call Counter Down Exchange Shared Data Block and Instance Data Block Clear RLO (= 0) Cosine of a Floating-Point Number (32-Bit IEEE FP) Counter Up Decrement Accumulator 1 Double Integer (32-Bit) to BCD Double Integer (32-Bit) to Real (32-Bit IEEE FP) Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3 Exponential Value of a Floating-Point Number (32-Bit IEEE FP) to base E Edge Negative Edge Positive Enable Counter (Free, FR C 0 to C 255) Enable Timer (Free, FR T 0 to T 255) Increment Accumulator 1 Ones Complement Double Integer (32-Bit) Ones Complement Integer (16-Bit) Integer (16-Bit) to BCD Integer (16-Bit) to Double Integer Jump if BR = 1 Jump if RLO = 1 Jump if RLO = 1 with BR Jump if RLO = 0 Jump to Labels Jump if Minus Jump if Minus or 0 Jump if Not 0 Jump if RLO = 0 with BR Name Page No. 10-2 18-4 18-2 18-13 23-3 14-11 18-13 23-7 13-5 21-2 11-26 16-7 13-5 10-6 18-6 18-7 10-3 16-12 11-17 11-16 12-5 13-3 10-6 18-14 18-14 18-5 18-6 22-4 22-4 22-4 22-4 22-3 22-6 22-6 22-6 22-4
International Abbreviation BLD BTD BTI CAD CALL CAR CAW CC CD CDB CLR COS CU DEC DTB DTR ENT EXP FN FP FR FR INC INVD INVI ITB ITD JBI JC JCB JCN JL JM JMZ JN JNB
A-8
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont. SIMATIC Abbreviation SPBIN SPO SPS SPP SPPZ SPA SPU SPZ L L L L L L L Jump if BR = 0 Jump if OV = 1 Jump if OS = 1 Jump if Plus Jump if Plus or 0 Jump Unconditional Jump if Unordered Jump if 0 Load Load Length of Shared Data Block into Accumulator 1 (L DBLG) Load Number of Shared Data Block into Accumulator 1 (L DBNO) Load Length of Instance Data Block into Accumulator 1 (L DILG) Load Number of Instance Data Block into Accumulator 1 (L DINO) Load Status Word into Accumulator 1 (L STW) Load Current Timer Value into Accumulator 1 as Integer (where the number of the current timer can be in the range of 0 to 255, for example: L T 32) Load Current Counter Value into Accumulator 1 as Integer (where the number of the current counter can be in the range of 0 to 255, for example: L C 15) Load Address Register 1 from Accumulator 1 (if no address is indicated) Load Address Register 1 from ... (from address indicated) Load Address Register 1 from Address Register 2 (LAR1 AR2) Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit) Load Address Register 2 from Accumulator 1 (if no address is indicated) Load Address Register 2 from ... (from address indicated) Load Address Register 2 with Double Integer (32-Bit, LAR2 P#area byte.bit) Load Current Counter Value into Accumulator 1 as BCD (where the number of the current counter can be in the range of 0 to 255, for example: LC C 15) Load Current Timer Value into Accumulator 1 as BCD (where the number of the current timer can be in the range of 0 to 255, for example: LC T 32) Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 3 Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP) Name Page No. 22-4 22-5 22-5 22-5 22-6 22-3 22-6 22-6 14-3 14-12 21-2 14-12 14-12 21-2 14-12 21-2 14-6 14-7
International Abbreviation JNBI JO JOS JP JPZ JU JUO JZ L L L L L L L
13-6 14-8 14-11 14-11 14-11 14-11 14-11 14-11 14-11 14-9
LAR1 LAR1 LAR1 LAR1 LAR2 LAR2 LAR2 LC
LAR1 LAR1 LAR1 LAR1 LAR2 LAR2 LAR2 LC
LC
LC
13-7 14-10 10-3 16-11
LEAVE LN
LEAVE LN
A-9
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont. SIMATIC Abbreviation LOOP MCR( )MCR MCRA MCRD MOD NEGD NEGI NEGR NOP 0 NOP 1 NOT O O( OD ON ON( AUF OW POP PUSH R R R RLD RLDA RND RND+ RNDRRD RRDA S S SAVE Loop Save RLO in MCR Stack, Begin MCR Restore RLO, End MCR Activate MCR Area Deactivate MCR Area Division Remainder Double Integer (32-Bit) Twos Complement Double Integer (32-Bit) Twos Complement Integer (16-Bit) Negate Real Number (32-Bit IEEE FP) Null Operation 0 Null Operation 1 Negate RLO Or Or with Nesting Open Or Double Word (32-Bit) Or Not Or Not with Nesting Open Open a Data Block Or Word (16-Bit) Accumulator 1 <--- Accumulator 2, Accumulator 2 <--- Accumulator 3, Accumulator 3 <--- Accumulator 4 Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3, Accumulator 1 ---> Accumulator 2 Reset Reset Counter (where the current counter can have a number in the range of 0 to 255, for example: R C 15) Reset Timer (where the current timer can have a number in the range of 0 to 255, for example: R T 32) Rotate Left Double Word (32-Bit) Rotate Accumulator 1 Left via CC 1 (32-Bit) Round Round to Upper Double Integer Round to Lower Double Integer Rotate Right Double Word (32-Bit) Rotate Accumulator 1 Right via CC 1 (32-Bit) Set Set Counter Preset Value (where the current counter can have a number in the range of 0 to 255, for example: S C 15) Save RLO in BR Register Name Page No. 22-8 23-11 23-11 23-11 23-11 15-5 18-14 18-14 18-14 10-2 10-2 11-26 11-10 11-14 19-6 11-9 11-14 21-2 19-3 10-2 10-2 11-22 12-5 13-4 20-6 20-6 18-9 18-10 18-11 20-8 20-6 11-21 13-3 11-26
International Abbreviation LOOP MCR( MCR) MCRA MCRD MOD NEGD NEGI NEGR NOP 0 NOP 1 NOT O O( OD ON ON( OPN OW POP PUSH R R R RLD RLDA RND RND+ RNDRRD RRDA S S SAVE
A-10
Table A-2
Alphabetical Listing with the International and the SIMATIC Mnemonic Abbreviations, cont. SIMATIC Abbreviation SE SV SET SA SIN SLD SLW SI SQR SQRT SRD SRW SS SSD SSI T T TAK TAN TAR1 TAR1 TAR1 TAR2 TAR2 TRUNC UC X X( XN XN( XOD XOW On-Delay Timer Extended Pulse Timer Set RLO (= 1) Off-Delay Timer Sine of a Floating-Point Number (32-Bit IEEE FP) Shift Left Double Word (32-Bit) Shift Left Word (16-Bit) Pulse Timer Square of a Floating-Point Number (32-Bit IEEE PF) Square Root of a Floating-Point Number (32-Bit IEEE PF) Shift Right Double Word (32-Bit) Shift Right Word (16-Bit) Retentive On-Delay Timer Shift Sign Double Integer (32-Bit) Shift Sign Integer (16-Bit) Transfer Transfer Accumulator 1 to Status Word (T STW) Toggle Accumulator 1 with Accumulator 2 Tangent of a Floating-Point Number (32-Bit IEEE FP) Transfer Address Register 1 to Accumulator 1 (if no address is indicated) Transfer Address Register 1 to ... (to address indicated) Transfer Address Register 1 to Address Register 2 (T AR1 AR2) Transfer Address Register 2 to Accumulator 1 (if no address is indicated) Transfer Address Register 2 to ... (to address indicated) Truncate Unconditional Call Exclusive Or Exclusive Or with Nesting Open Exclusive Or Not Exclusive Or Not with Nesting Open Exclusive Or Double Word (32-Bit) Exclusive Or Word (16-Bit) Name Page No. 12-11 12-9 11-26 12-15 16-7 20-2 20-2 12-7 16-9 16-9 20-3 20-2 12-13 20-4 20-4 14-3 14-6 10-2 16-7 14-11 14-11 14-11 14-11 14-11 18-12 23-7 11-10 11-14 11-9 11-14 19-6 19-3
International Abbreviation SD SE SET SF SIN SLD SLW SP SQR SQRT SRD SRW SS SSD SSI T T TAK TAN TAR1 TAR1 TAR1 TAR2 TAR2 TRUNC UC X X( XN XN( XOD XOW
A-11
A.2
Alphabetical Listing with International Names

Table A-3 provides an alphabetical listing of the full international names of the statement list instructions. Next to each name is its international mnemonic abbreviation and the page on which the instruction is explained.
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name Name Mnemonic Page No. Abbreviation ABS PUSH POP POP LEAVE ENT PUSH MCRA +D +I +R +AR1 +AR2 + A AD AN AN( A( AW ACOS ASIN ATAN = BTD BTI BEC BEU CALL CAW CAD 16-6 10-2 10-2 10-2 10-3 10-3 10-2 23-11 15-2 15-2 16-2 10-7 10-7 15-6 11-10 19-6 11-9 11-14 11-14 19-3 16-7 16-7 16-7 11-24 18-4 18-2 23-15 23-15 23-3 18-13 18-13
Absolute Value of a Real (32-Bit IEEE FP) Accumulator 1 ---> Accumulator 2 Accumulator 1 <--- Accumulator 2 Accumulator 1 <--- Accumulator 2, Accumulator 2 <--- Accumulator 3, Accumulator 3 <--- Accumulator 4 Accumulator 3 ---> Accumulator 2, Accumulator 4 ---> Accumulator 3 Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3 Accumulator 3 ---> Accumulator 4, Accumulator 2 ---> Accumulator 3, Accumulator 1 ---> Accumulator 2 Activate MCR Area Add Accumulator 1 and Accumulator 2 as Double Integer (32-Bit) Add Accumulator 1 and Accumulator 2 as Integer (16-Bit) Add Accumulator 1 and Accumulator 2 as Real (32-Bit IEEE FP) Add Accumulator 1 to Address Register 1 Add Accumulator 1 to Address Register 2 Add Integer Constant (8, 16, 32-Bit) And And Double Word (32-Bit) And Not And Not with Nesting Open And with Nesting Open And Word (16-Bit) Arc Cosine of a Floating-Point Number (32-Bit IEEE FP) Arc Sine of a Floating-Point Number (32-Bit IEEE FP) Arc Tangent of a Floating-Point Number (32-Bit IEEE FP) Assign BCD to Double Integer (32-Bit) BCD to Integer (16-Bit) Block End Conditional Block End Unconditional Call Change Byte Sequence in Accumulator 1 (16-Bit) Change Byte Sequence in Accumulator 1 (32-Bit)
A-12
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name, continued Name Mnemonic Page No. Abbreviation CLR ==D ==I ==R CC COS CD CU MCRD DEC /D /I /R MOD DTB DTR FN FP FR FR CAR CDB X XOD XN XN( X( XOW EXP SE INC ITB ITD JZ JNBI JBI JM 11-26 17-3 17-3 17-3 23-7 16-7 13-5 13-5 23-11 10-6 15-2 15-2 16-2 15-5 18-6 18-7 11-17 11-16 12-5 13-3 14-11 21-2 11-10 19-6 11-9 11-14 11-14 19-3 16-12 12-9 10-6 18-5 18-6 22-6 22-4 22-4 22-6
Clear RLO (= 0) Compare Double Integer (32-Bit) >, <, >=, <=, ==, <> Compare Integer (16-Bit) >, <, >=, <=, ==, <> Compare Real >, <, >=, <=, ==, <> Conditional Call Cosine of a Floating-Point Number (32-Bit IEEE FP) Counter Down Counter Up Deactivate MCR Area Decrement Accumulator 1 Divide Accumulator 2 by Accumulator 1 as Double Integer (32-Bit) Divide Accumulator 2 by Accumulator 1 as Integer (16-Bit) Divide Accumulator 2 by Accumulator 1 as Real (32-Bit IEEE FP) Division Remainder Double Integer (32-Bit) Double Integer (32-Bit) to BCD Double Integer (32-Bit) to Real (32-Bit IEEE FP) Edge Negative Edge Positive Enable Counter (Free, FR C 0 to C 255) Enable Timer (Free, FR T 0 to T 255) Exchange Address Register 1 with Address Register 2 Exchange Shared Data Block and Instance Data Block Exclusive Or Exclusive Or Double Word (32-Bit) Exclusive Or Not Exclusive Or Not with Nesting Open Exclusive Or with Nesting Open Exclusive Or Word (16-Bit) Exponential Value of a Floating-Point Number (32-Bit IEEE FP) to base E Extended Pulse Timer Increment Accumulator 1 Integer (16-Bit) to BCD Integer (16-Bit) to Double Integer Jump if 0 Jump if BR = 0 Jump if BR = 1 Jump if Minus
A-13
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name, continued Name Mnemonic Page No. Abbreviation JMZ JN JOS JO JP JPZ JCN JNB JC JCB JUO JL JU L LAR1 LAR1 LAR1 LAR1 LAR2 LAR2 LAR2 L LC LC L L L L L L LOOP *D 22-6 22-6 22-5 22-5 22-6 22-6 22-4 22-4 22-4 22-4 22-6 22-3 22-3 14-3 14-11 14-11 14-11 14-11 14-11 14-11 14-11 13-6 14-8 14-9 13-7 14-10 14-7 14-12 21-2 14-12 21-2 14-12 21-2 14-12 21-2 14-6 22-8 15-2
Jump if Minus or 0 Jump if Not 0 Jump if OS = 1 Jump if OV = 1 Jump if Plus Jump if Plus or 0 Jump if RLO = 0 Jump if RLO = 0 with BR Jump if RLO = 1 Jump if RLO = 1 with BR Jump if Unordered Jump to Labels Jump Unconditional Load Load Address Register 1 from ... (from address indicated) Load Address Register 1 from Accumulator 1 (if no address is indicated) Load Address Register 1 from Address Register 2 (LAR1 AR2) Load Address Register 1 with Double Integer (32-Bit, LAR1 P#area byte.bit) Load Address Register 2 from ... (from address indicated) Load Address Register 2 from Accumulator 1 (if no address is indicated) Load Address Register 2 with Double Integer (32-Bit, LAR2 P#area byte.bit) Load Current Counter Value into Accumulator 1 as Integer (where the number of the current counter can be in the range of 0 to 255, for example: L C 15) Load Current Counter Value into Accumulator 1 as BCD (where the number of the current counter can be in the range of 0 to 255, for example: LC C 15) Load Current Timer Value into Accumulator 1 as BCD (where the number of the current timer can be in the range of 0 to 255, for example: LC T 32) Load Current Timer Value into Accumulator 1 as Integer (where the number of the current timer can be in the range of 0 to 255, for example: L T 32) Load Length of Instance Data Block into Accumulator 1 (L DILG) Load Length of Shared Data Block into Accumulator 1 (L DBLG) Load Number of Instance Data Block into Accumulator 1 (L DINO) Load Number of Shared Data Block into Accumulator 1 (L DBNO) Load Status Word into Accumulator 1 (L STW) Loop Multiply Accumulator 1 by Accumulator 2 as Double Integer (32-Bit)
A-14
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name, continued Name Mnemonic Page No. Abbreviation *I *R LN NEGR NOT ) NOP 0 NOP 1 SF SD INVD INVI OPN O OD ON ON( O( OW BLD SP R R R )MCR SS RLDA RRDA RLD RRD RND RNDRND+ SAVE MCR( S 15-2 16-2 16-11 18-14 11-26 11-14 10-2 10-2 12-15 12-11 18-14 18-14 21-2 11-10 19-6 11-9 11-14 11-14 19-3 10-2 12-7 11-22 12-5 13-4 23-11 12-13 20-8 20-6 20-6 20-8 18-9 18-11 18-10 11-26 23-11 11-21
Multiply Accumulator 1 by Accumulator 2 as Integer (16-Bit) Multiply Accumulator 1 by Accumulator 2 as Real (32-Bit IEEE FP) Natural Logarithm of a Floating-Point Number (32-Bit IEEE FP) Negate Real Number (32-Bit IEEE FP) Negate RLO Nesting Closed Null Operation 0 Null Operation 1 Off-Delay Timer On-Delay Timer Ones Complement Double Integer (32-Bit) Ones Complement Integer (16-Bit) Open a Data Block Or Or Double Word (32-Bit) Or Not Or Not with Nesting Open Or with Nesting Open OR Word (16-Bit) Program Display Instruction Pulse Timer Reset Reset Counter (where the current counter can have a number in the range of 0 to 255, for example: R C 15) Reset Timer (where the current timer can have a number in the range of 0 to 255, for example: R T 32) Restore RLO, End MCR Retentive On-Delay Timer Rotate Accumulator 1 Left via CC 1 (32-Bit) Rotate Accumulator 1 Right via CC 1 (32-Bit) Rotate Left Double Word (32-Bit) Rotate Right Double Word (32-Bit) Round Round to Lower Double Integer Round to Upper Double Integer Save RLO in BR Register Save RLO in MCR Stack, Begin MCR Set
A-15
Table A-3
Statement List Instructions Arranged Alphabetically by International Full Name, continued Name Mnemonic Page No. Abbreviation S SET SLD SLW SRD SRW SSD SSI SIN SQR SQRT -D -I -R TAN TAK T T TAR1 TAR1 TAR1 TAR2 TAR2 TRUNC NEGD NEGI UC 13-3 11-26 20-2 20-2 20-3 20-2 20-4 20-4 16-7 16-9 16-9 15-2 15-2 16-2 16-7 10-2 14-3 14-6 14-11 14-11 14-11 14-11 14-11 18-12 18-14 18-14 23-7
Set Counter Preset Value (where the current counter can have a number in the range of 0 to 255, for example: S C 15) Set RLO (= 1) Shift Left Double Word (32-Bit) Shift Left Word (16-Bit) Shift Right Double Word (32-Bit) Shift Right Word (16-Bit) Shift Sign Double Integer (32-Bit) Shift Sign Integer (16-Bit) Sine of a Floating-Point Number (32-Bit IEEE FP) Square of a Floating-Point Number (32-Bit IEEE PF) Square Root of a Floating-Point Number (32-Bit IEEE PF) Subtract Accumulator 1 from Accumulator 2 as Double Integer (32-Bit) Subtract Accumulator 1 from Accumulator 2 as Integer (16-Bit) Subtract Accumulator 1 from Accumulator 2 as Real (32-Bit IEEE FP) Tangent of a Floating-Point Number (32-Bit IEEE FP) Toggle Accumulator 1 with Accumulator 2 Transfer Transfer Accumulator 1 to Status Word (T STW) Transfer Address Register 1 to ... (to address indicated) Transfer Address Register 1 to Accumulator 1 (if no address is indicated) Transfer Address Register 1 to Address Register 2 (T AR1 AR2) Transfer Address Register 2 to ... (to address indicated) Transfer Address Register 2 to Accumulator 1 (if no address is indicated) Truncate Twos Complement Double Integer (32-Bit) Twos Complement Integer (16-Bit) Unconditional Call
A-16
Programming Examples
Chapter Overview
Section B.1 B.2 B.3 B.4 B.5 B.6 Overview Bit Logic Instructions Timer Instructions Counter and Comparison Instructions Integer Math Instructions Word Logic Instructions Description
B
Page B-2 B-3 B-7 B-10 B-12 B-14
B-1
B.1
Overview
Practical Applications
Each statement list instruction described in this manual triggers a specific operation. When you combine these instructions into a program, you can accomplish a wide variety of automation tasks. This chapter provides the following examples of practical applications of the statement list instructions:
S Controlling a conveyor belt using bit logic instructions S Detecting direction of movement on a conveyor belt using bit logic
instructions
S Generating a clock pulse using timer instructions S Keeping track of storage space using counter and comparison instructions S Solving a problem using integer math instructions S Setting the length of time for heating an oven
When you create an ASCII file that will be imported into the STL editor, you must follow the conventions outlined in Appendix C.
Instructions Used
The examples in this chapter use the following instructions:
S And (A) and And Not (AN) S Assign (=) S Block End (BE) and Block End Conditional (BEC) S Compare Integer (16-bit, <=, >=) S Counter Down (CD) and Counter Up (CU) S Edge Positive (FP) S Extended Pulse Timer (SE) S Increment Accumulator 1 (INC) S Integer Four-function Math (16 BITS)
Add Accumulators 1 and 2 As Integer (+I) Divide Accumulator 2 by Accumulator 1 As Integer (/I) Multiply Accumulators 1 and 2 As Integers (I)
S Load (L) and Transfer (T) S Negate RLO (NOT) S Or (O) and Or Not (ON) S Set (S) and Reset (R) S Word Logic (And Word, Or Word)
B-2
B.2
Controlling a Conveyor Belt
Figure B-1 shows a conveyor belt that can be activated electrically. There are two push button switches at the beginning of the belt: S1 for START and S2 for STOP. There are also two push button switches at the end of the belt: S3 for START and S4 for STOP. It it possible to start or stop the belt from either end. Also, sensor S5 stops the belt when an item on the belt reaches the end.
Symbolic Programming
You can write a program to control the conveyor belt shown in Figure B-1 using symbols that represent the various components of the conveyor system. If you choose this method, you need to make a symbol table to correlate the symbols you choose with absolute values (see Table B-1). Table B-3 compares a statement list program that uses symbols as addresses to a program that uses absolute values as addresses. You define the symbols in the symbol table (see STEP 7 Online Help).
Table B-1 Elements of Symbolic Programming for Conveyor Belt System Absolute Address I 1.1 I 1.2 I 1.3 I 1.4 I 1.5 Q 4.0 S1 S2 S3 S4 S5 MOTOR_ON Symbol Symbol Table I 1.1 I 1.2 I 1.3 I 1.4 I 1.5 Q 4.0 S1 S2 S3 S4 S5 MOTOR_ON
System Component Push Button Start Switch Push Button Stop Switch Push Button Start Switch Push Button Stop Switch Sensor Motor
Sensor S5
MOTOR_ON Figure B-1 Conveyor Belt System
S1 S2
` Start ` Stop
S3 S4
` Start ` Stop
B-3
Absolute Programming
You can write a program to control the conveyor belt shown in Figure B-1 using absolute values that represent the different components of the conveyor system (see Table B-2). Table B-3 compares a statement list program that uses absolute values as addresses to a program that uses symbols as addresses. An explanation of the program follows the tables.
Table B-2 Elements of Absolute Programming for Conveyor Belt System System Component Push Button Start Switch Push Button Stop Switch Push Button Start Switch Push Button Stop Switch Sensor Motor Absolute Address I 1.1 I 1.2 I 1.3 I 1.4 I 1.5 Q 4.0
Table B-3
Symbolic and Absolute Programs to Control a Conveyor Belt Symbolic Program O O S O O ON R S1 S3 MOTOR_ON S2 S4 S5 MOTOR_ON Absolute Program O O S O O ON R I 1.1 I 1.3 Q 4.0 I 1.2 I 1.4 I 1.5 Q 4.0
STL O O S O O ON R I I Q I I I Q 1.1 1.3 4.0 1.2 1.4 1.5 4.0
Explanation Pressing either start switch turns the motor on.
Pressing either stop switch or opening the normally closed contact at the end of the belt turns the motor off.
B-4
Detecting the Direction of a Conveyor Belt
Figure B-2 shows a conveyor belt that is equipped with two photoelectric barriers (PEB1 and PEB2) that are designed to detect the direction in which a package is moving on the belt. Each photoelectric light barrier functions like a normally open contact (see Section 5.1).
Symbolic Programming
You can write a program to activate a direction display for the conveyor belt system shown in Figure B-2 using symbols that represent the various components of the conveyor system, including the photoelectric barriers that detect direction. If you choose this method, you need to make a symbol table to correlate the symbols you choose with absolute values (see Table B-4). Table B-6 compares a statement list program that uses symbols as addresses to a program that uses absolute values as addresses. You define the symbols in the symbol table (see the STEP 7 Online Help).
Table B-4 Elements of Symbolic Programming for Detecting Direction Absolute Address I 0.0 I 0.1 Q 4.0 Q 4.1 M 0.0 M 0.1 Symbol PEB1 PEB2 RIGHT LEFT PMB1 PMB2 Symbol Table I 0.0 I 0.1 Q 4.0 Q 4.1 M 0.0 M 0.1 PEB1 PEB2 RIGHT LEFT PMB1 PMB2
System Component Photo electric barrier 1 Photo electric barrier 2 Display for movement to right Display for movement to left Pulse memory bit 1 Pulse memory bit 2
Q 4.0
PEB2
PEB1
Q 4.1
Figure B-2
Conveyor Belt System with Photoelectric Light Barriers for Detecting Direction
B-5
Absolute Programming
You can write a program to control the direction display for the conveyor belt shown in Figure B-2 using absolute values that represent the photoelectric barriers that detect direction (see Table B-5). Table B-6 compares a statement list program that uses absolute values as addresses to a program that uses symbols as addresses. An explanation of the program follows the figure.
Table B-5 Elements of Absolute Programming for Detecting Direction System Component Photo electric barrier 1 Photo electric barrier 2 Display for movement to right Display for movement to left Pulse memory bit 1 Pulse memory bit 2 Absolute Address I 0.0 I 0.1 Q 4.0 Q 4.1 M 0.0 M 0.1
Table B-6
Symbolic and Absolute Programs to Detect Direction Symbolic Program A FP AN S A FP AN S AN AN R R I PEB1 PMB1 PEB2 LEFT PEB2 PMB2 PEB1 RIGHT PEB1 PEB2 RIGHT LEFT Absolute Program A FP AN S A FP AN S AN AN R R I 0.0 M 0.0 I 0.1 Q 4.1 I 0.1 M 0.1 I 0.0 Q 4.0 I 0.0 I 0.1 Q 4.0 Q 4.1
STL A FP AN S A FP AN S AN AN R R I M I Q I M I Q I I Q Q 0.0 0.0 0.1 4.1 0.1 0.1 0.0 4.0 0.0 0.1 4.0 4.1
Explanation If there is a transition in signal state from 0 to 1 (positive edge) at input I 0.0 and, at the same time, the signal state at input I 0.1 is 0, then the package on the belt is moving to the left. If there is a transition in signal state from 0 to 1 (positive edge) at input I 0.1 and, at the same time, the signal state at input I 0.0 is 0, then the package on the belt is moving to the right. If one of the photoelectric light barriers is broken, this means that there is a package between the barriers. If neither photoelectric barrier is broken, then there is no package between the barriers. The direction pointer shuts off.
B-6
B.3
Timer Instructions
You can use a clock pulse generator or flasher relay when you need to produce a signal that repeats periodically. A clock pulse generator is common in a signalling system that controls the flashing of indicator lamps. When you use the S7-300, you can implement the clock pulse generator function by using time-driven processing in special organization blocks. The example shown in the following statement list program, however, illustrates the use of timer functions to generate a clock pulse. The following example shows how to implement a freewheeling clock pulse generator by using a timer (pulse duty factor 1:1). The frequency is divided into the values listed in Table B-7.
Clock Pulse Generator
STL AN L SE NOT BEC L INC T T 1 S5T#250ms T 1
Explanation If timer T 1 has expired, load the time value 250 ms into T 1 and start T 1 as an extended-pulse timer. Negate (invert) the result of logic operation. If the timer is running, end the current block. If the timer has expired, load the contents of memory byte MB100, increment the contents by 1, and transfer the result to memory byte MB100.
MB100 1 MB100
A signal check of timer T 1 produces the result of logic operation.
1 0 250 ms Figure B-3 RLO for AN T 1 Statement in the Clock Pulse Timer Example
As soon as the time runs out, the timer is restarted. Therefore, the signal check made by the statement AN T 1 produces a signal state of 1 only briefly.
1 0 250 ms Figure B-4 Negated RLO Bit of Timer T 1 in the Clock Pulse Timer Example
Every 250 ms the RLO bit is 0. Figure B-4 shows what the negated (inverted) RLO bit looks like. Then the BEC statement does not end the processing of the block. Instead, the contents of memory byte MB100 is incremented by 1. The contents of memory byte MB100 changes every 250 ms as follows: 0 !1!2!3! ... !254!255!0!1 ...
B-7
Achieving a Specific Frequency
Table B-7 lists the frequencies that you can achieve from the individual bits of memory byte MB100. The statement list program that follows the table shows how you can use the frequencies that are generated.
Table B-7 Bits of MB100 M 100.0 M 100.1 M 100.2 M 100.3 M 100.4 M 100.5 M 100.6 M 100.7 Frequencies for Clock Pulse Timer Example Frequency in Hertz 2.0 1.0 0.5 0.25 0.125 0.0625 0.03125 0.015625 Duration 0.5 s (250 ms on/250 ms off) 1 s (0.5 s on/0.5 s off) 2 s (1 s on/1 s off 4 s (2 s on/2 s off) 8 s (4 s on/4 s off) 16 s (8 s on/8 s off) 32 s (16 s on/16 s off) 64 s (32 s on/32 s off)
STL A A = M 10.0 M 100.1 Q 4.0
Explanation M 10.0 = 1 when a fault occurs. The fault lamp blinks at a frequency of 1 Hz when a fault occurs.
B-8
Table B-8 lists the signal states of the bits of memory byte MB100. Figure B-5 shows the RLO of memory bit M100.1.
Table B-8 Scan Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 Signal States of the Bits of Memory Byte MB100 Signal State of Bits of Memory Byte MB100 7 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Time Value in ms 250 250 250 250 250 250 250 250 250 250 250 250 250
T M 100.1 1 0 Time 0 250 ms 0.5 s 0.75 s 1 s 1.25 s 1.5 s
Frequency + 1 + 1 + 1Hz 1 s T Figure B-5 Signal State of Bit 1 MB100 (M 100.1)
B-9
B.4
Counter and Comparison Instructions
Storage Area with Counter and Comparator
Figure B-6 shows a system with two conveyor belts and a temporary storage area in between them. Conveyor belt 1 delivers packages to the storage area. A photoelectric barrier at the end of conveyor belt 1 near the storage area determines how many packages are delivered to the storage area. Conveyor belt 2 transports packages from the temporary storage area to a loading dock where trucks take the packages away for delivery to customers. A photoelectric barrier at the end of conveyor belt 2 near the storage area determines how many packages leave the storage area to go to the loading dock. A display panel with five lamps indicates the fill level of the temporary storage area. The sample program that follows Figure B-6 is the program that activates the indicator lamps on the display panel.
Display Panel
Storage area empty (Q 4.0)
Storage area not empty (Q 4.1)
Storage area 50% full (Q 4.2)
Storage area 90% full (Q 4.3)
Storage area filled to capacity (Q 4.4)
I 0.0 Packages in
Temporary storage for 100 packages
I 0.1 Packages out
Conveyor belt 1 Photoelectric barrier 1
Conveyor belt 2 Photoelectric barrier 2
Figure B-6
Storage Area with Counter and Comparator
B-10
STL A I 0.0 CU C 1 A CD AN = A = L L <=I = L >=I = L L >=I = I 0.1 C 1 C 1 Q 4.0 C 1 Q 4.1 +50 C 1 Q 4.2 +90 Q 4.3 C 1 100 Q 4.4
Explanation Each pulse generated by photoelectric barrier 1 increases the count value of counter C 1 by one, thereby counting the number of packages going into the storage area. Each pulse generated by photoelectric barrier 2 decreases the count value of counter C 1 by one, thereby counting the packages that leave the storage area. If the count value is 0, the indicator lamp for Storage area empty comes on. If the count value is not 0, the indicator lamp for Storage area not empty comes on. If 50 is less than or equal to the count value, the indicator lamp for Storage area 50% full comes on. If the count value is greater than or equal to 90, the indicator lamp for Storage area 90% full comes on. If the count value is greater than or equal to 100, the indicator lamp for Storage area filled to capacity comes on. (You could also use output Q 4.4 to lock conveyor belt 1.)
B-11
B.5
Solving a Math Problem
The following sample program (applicable for the S7-300 only) shows you how to use three integer math instructions, along with Load and Transfer, to produce the same result as the following equation:
MD4 + (IW0 ) DBW3) MW2 15
STL L L IW0 DB5.DBW3
Explanation Load the value from input word IW0 into accumulator 1. Load the value from shared data word DBW3 of DB5 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Add the contents of the low words of accumulators 1 and 2. The result is stored in the low word of accumulator 1. The contents of accumulator 2 and the high word of accumulator 1 remain unchanged. Load the constant value +15 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Multiply the contents of the low word of accumulator 2 by the contents of the low word of accumulator 1. The result is stored in accumulator 1. The contents of accumulator 2 remain unchanged. Load the value from memory word MW2 into accumulator 1. The old contents of accumulator 1 are shifted to accumulator 2. Divide the contents of the low word of accumulator 2 by the contents of the low word of accumulator 1. The result is stored in accumulator 1. The contents of accumulator 2 remain unchanged. Transfer the final result to memory double word MD4. The contents of both accumulators remain unchanged.
+I
L I
+15
MW2
/I
MD4
B-12
Figure B-7 shows the relationship of the program to the equation.
Accumulator 1 L IW0 (IW0)
Accumulator 2 (Old contents)
DBW3
+I
(DBW3) + (IW0) + (DBW3)
(IW0)
(IW0)
L I
+15
15 [(IW0) + (DBW3)] 15
(IW0) + (DBW3)
(IW0) + (DBW3)
MW2
MW2 / (IW0 ) DBW3) MW2 15
[(IW0) + (DBW3)] 15 (IW0 ) DBW3)
/I
15
MD4
(IW0 ) DBW3) MW2 MD4 +
15
(IW0 ) DBW3)
15
(IW0 ) DBW5) MW2
15
Figure B-7
Relationship of Integer Math Statements to an Equation (S7-300)
B-13
B.6

The operator of the oven shown in Figure B-8 starts the oven heating by pushing the start push button. The operator can set the length of time for heating by using the thumbwheel switches shown in the figure. The value that the operator sets indicates seconds in binary coded decimal (BCD) format. Table B-9 lists the components of the heating system and their corresponding absolute addresses used in the sample program that follows Figure B-8.
Table B-9 Heating System Components and Corresponding Absolute Addresses System Component Start push button Thumbwheel for ones Thumbwheel for tens Thumbwheel for hundreds Heating starts Absolute Address in STL Program I 0.7 I 1.0 to I 1.3 I 1.4 to I 1.7 I 0.0 to I 0.3 Q 4.0
Heating an Oven
Oven

4 4 7.... XXXX IB0 Start push button I 0.7 ...0 0001 7... 1001 IB1
Thumbwheels for setting BCD digits
4 ...0 0001 Bits IW0 Bytes
Heat Q 4.0
Figure B-8
STL A T 1 = Q 4.0 BEC L AW OW A SE BE
Using the Inputs and Outputs for the Time-Limited Heating Process
Explanation If the timer is running, then turn on the heat. If the timer is running, then end processing here. This prevents timer T 1 from being restarted if the push button is pressed. Mask input bits I 0.4 through I 0.7 (that is, reset them to 0). The time value in seconds is in the low word of accumulator 1 in binary coded decimal format. Assign the time base as seconds in bits 12 and 13 of the low word of accumulator 1. Start timer T 1 as an extended pulse timer if the push button is pressed. End the program network.
IW0 W#16#0FFF W#16#2000 I 0.7 T 1
B-14
Source Files - Examples and Reserved Keywords
Definition
A keyword is a reserved identifier which cannot be used as a general identifier. To use a keyword as a global symbol it must be marked as scan cycle checkpoint (SCC). To use a keyword as a local symbol it must be marked with #.
Overview
Table C-1 lists all keywords reserved for STEP 7.

Table C-1 Keywords Keywords A AB AD ANY AO AR1 AR2 ARRAY AUTHOR AW B BEGIN BIE BLOCK_DB BLOCK_FB BLOCK_FC BLOCK_SDB BOOL BYTE
C CALL CHAR COUNTER
DATA_BLOCK DATE DATE_AND_TIME DB DBB DBD DBLG DBNO DBW DBX
C-1
Source Files Examples and Reserved Keywords
Table C-1
Keywords, continued Keywords DI DIB DID DILG DINO DINT DIW DIX DT DWORD
E EB ED END_Data_Block END_Function END_Function_Block END_Organization_Block END_Struct END_System_Function END_System_Function_Block END_Type END_VAR EW
FALSE FAMILY FB FC FUNCTION FUNCTION_BLOCK
I IB ID INT IW
KA KNOW_HOW_PROTECT KP
L LB LD LW
M MB MD MW
NAME NETWORK NI NO
OB OF ORGANIZATION_BLOCK
PA PAB PAD
C-2
Table C-1
Keywords, continued Keywords
OS OV
PAW PE PEB PED PEW PI PIB PID PIW PQ PQB PQD PQW POINTER
Q QB QD QW
READ_ONLY REAL RET_VAL
S5T S5TIME SDB SFB SFC STANDARD STRING STRUCT STW SYSTEM_FUNCTION SYSTEM_FUNCTION_BLOCK
T TIME TIME_OF_DAY TIMER TITLE TOD TRUE TYPE
UDT UNLINKED UO
VAR VAR_IN_OUT VAR_INPUT VAR_OUTPUT VAR_TEMP VERSION
C-3
Table C-1
Keywords, continued Keywords VOID
WORD
C-4
References
/30/ /70/ /71/ /72/ Getting Started: Working with STEP 7 V5.0 Manual: S7-300 Programmable Controller, Hardware and Installation
D
Reference Manual: S7-300, M7-300 Programmable Controllers Module Specifications Instruction List: S7-300 Programmable Controller
/100/ Manual: S7-400/M7-400 Programmable Controllers, Hardware and Installation /101/ Reference Manual: S7-400/M7-400 Programmable Controllers Module Specifications /102/ Instruction List: S7-400 Programmable Controller /231/ Manual: Configuring Hardware and Communication Connections, STEP 7 V5.0 /233/ Reference Manual: Ladder Logic (LAD) for S7-300 and S7-400 Programming /234/ Manual: Programming with STEP 7 V5.0 /235/ Reference Manual: System Software for S7-300 and S7-400 System and Standard Functions /236/ Reference Manual: Function Block Diagram (FBD) for S7-300 and 400, Programming /250/ Manual: Structured Control Language (SCL) for S7-300/S7-400, Programming /251/ Manual: S7-GRAPH for S7-300 and S7-400, Programming Sequential Control Systems /252/ Manual: S7-HiGraph for S7-300 and S7-400, Programming State Graphs /253/ Manual: C Programming for S7-300 and S7-400, Writing C Programs /254/ Manual: Continuous Function Charts (CFC) for S7 and M7, Programming Continuous Function Charts /270/ Manual: S7-PDIAG for S7-300 and S7-400 Configuring Process Diagnostics for LAD, STL, and FBD /271/ Manual: NETPRO, Configuring Networks
D-1
References
/800/ DOCPRO Creating Wiring Diagrams (CD only) /801/ TeleService for S7, C7 and M7 Remote Maintenance for Automation Systems (CD only) /802/ PLC Simulation for S7-300 and S7-400 (CD only) /803/ Reference Manual: Standard Software for S7-300 and S7-400, STEP 7 Standard Functions, Part 2
D-2
Glossary
A
Absolute Addressing In absolute addressing, the memory location of the address to be processed is given.
Accumulator
Accumulators are registers in the CPU which act as intermediate buffers for load, transfer, comparison, math, and conversion operations.
Actual Parameter
Actual parameters replace the formal parameters when function blocks (FBs) and functions (FCs) are called. Example: The formal parameter Start is replaced by the actual parameter I3.6.
Address
An address is part of a STEP 7 statement and specifies what the processor should execute the instruction on. Addresses can be absolute or symbolic.
Address Identifier
An address identifier is the part of the address which contains various data. The data can include elements such as a value itself (data object) or the size of a value with which the instruction can, for example, perform a logic operation. In the instruction statement L IB10 IB is the address identifier (I indicates the memory input area and B indicates a byte in that area).
Address Register
The address register is part of the registers in the communication part of the CPU. They act as pointers for register indirect addressing (possible in STL).
Array
An array is a complex data type which consists of data elements of the same type. These data elements can be elementary or complex.
Glossary-1
Glossary
B
Bit Result (BR) The bit result is the link between bit and word-oriented processing. This is an efficient method to allow the binary interpretation of the result of a word instruction and to include it in a series of logic operations.
C
Call Hierarchy All blocks must be called first before they can be processed. The sequence and nesting of these calls within an organized block is called the call hierarchy.
Condition Codes CC 1 and CC 0
The CC 1 and CC 0 bits (condition codes) provide information on the following results or bits:
S Result of a math operation S Result of a comparison S Result of a digital operation S Bits that have been shifted out by a shift or rotate command
CPU A CPU (central processing unit) is the central module in a programmable controller in which the user program is stored and processed. It consists of an operating system, processing unit, and communication interfaces.
Current Path
Characteristic of the Ladder Logic programming language. Current paths contain contacts and coils. Complex elements (for example, math functions) can also be inserted into current paths in the form of boxes. Current paths are connected to power rails.
D
Data Block (DB) Data blocks (DBs) are areas in a user program which store user data. There are shared data blocks which can be accessed by all logic blocks and there are instance data blocks which are associated with a certain function block (FB) call. In contrast to all other blocks, data blocks do not contain instructions.
Glossary-2
Glossary
Data, Static
Static data are local data of a function block which are stored in the instance data block and, therefore, remain intact until the function block is processed again.
Data Type
A data type defines how the value of a variable or a constant should be used in the user program. In SIMATIC STEP 7 two data types are available to the user (IEC 11313):
S Elementary data types S Complex data types

Data Type, Complex Complex data types are created by the user with the data type declaration. They do not have their own name and cannot, therefore, be used again. They can either be arrays or structures. The data types STRING and DATE AND TIME are classed as complex data types.
Data Type, Elementary
Elementary data types are preset data types according to IEC 11313. Examples:
S Data type BOOL defines a binary variable (Bit) S Data type INT defines a 16-bit fixed-point variable.
Declaration
The declaration section is used for the declaration of the local data of a logic block when programming in the Text Editor.
Direct Addressing
In direct addressing, the address contains the memory location of a value which is to be used by the instruction. Example: The location Q4.0 defines bit 0 in byte 4 of the process-image output table.
F
First Check Bit First check of the result of logic operation.
Folder
Directory of the user interface of the SIMATIC Manager which can be opened and can hold other directories or objects.
Glossary-3
Glossary
Formal Parameter
A formal parameter is a placeholder for the actual parameter in logic blocks. In function blocks (FBs) and functions (FCs) the formal parameters are declared by the user, in system function blocks (SFBs) and system functions (SFCs) they are already available. When a block is called, formal parameters are assigned actual parameters, so the called block works with the current values. The formal parameters are classed as local data. They can be input, output, or in/out parameters.
Function (FC)
According to the International Electrotechnical Commissions IEC 11313 standard, functions are logic blocks without a memory (meaning they do not have static data). A function allows you to transfer parameters in the user program, which means they are suitable for programming frequently recurring, complex functions, such as calculations. Important: As a function has no memory, you must continue processing the calculated values directly after the function has been called.
Function Block (FB)
According to the International Electrotechnical Commissions IEC 11313 standard, function blocks are logic blocks with a memory (meaning they have static data). A function block allows you to transfer parameters in the user program, which means they are suitable for programming frequently recurring, complex functions, such as closed-loop control and operating mode selection. As a function block has a memory (instance data block), you can access its parameters (for example, outputs) at any time and at any point in the user program.
Function Block Diagram (FBD)
Function Block Diagram (FBD) is one of the programming languages in STEP 5 and STEP 7. FBD represents logic in the boxes familiar from Boolean algebra. In addition, complex functions (for example, math functions) can be represented in direct connection with the logic box. Programs created with FBD can also be translated into other programming languages (for example, Ladder Logic).
I
Immediate Addressing In immediate addressing, the address contains the value with which the instruction works. Example: L.27 means load constant 27 into accumulator.
Input, Incremental
When a block is input incrementally, each line or element is checked immediately for errors (for example, syntax errors). If an error is detected, it is marked and must be corrected before programming is completed. Incremental input is possible in STL (Statement List), LAD (Ladder Logic), and FBD (Function Block Diagram).
Glossary-4
Glossary
Instance
An instance is the call of a function block. An instance data block is assigned to each call.
Instance Data Block (DB)
An instance data block stores the formal parameters and the static data of function blocks. An instance data block can be assigned to one function block call or a call hierarchy of function blocks.
Instruction
An instruction is part of a STEP 7 statement; it specifies what the processor should do.
K
Keyword Keywords are used when programming with source files to identify the start and end of a block and to select sections in the declaration section of blocks, the start of block comments and the start of titles.
L
Ladder Logic (LAD) Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Its representation is standardized in compliance with DIN 19239 (international standard IEC 1131-1). Ladder Logic representation corresponds to the representation of relay ladder logic diagrams. In contrast to Statement List (STL), LAD has a restricted set of instructions.
Logic Block
Logic blocks are blocks within SIMATIC S7 that contain a part of the STEP 7 user program. In contrast, data blocks (DBs) only contain data. There are the following types of logic blocks: organization blocks (OBs), function blocks (FBs), functions (FCs), system function blocks (SFBs), and system functions (SFCs). Blocks are stored in the Blocks folder under the S7 Program folder.
Logic String
A logic string is that portion of a user program which begins with an FC bit that has a signal state of 0 and which ends when an instruction or event resets the FC bit to 0. When the CPU executes the first instruction in a logic string, the FC bit is set to 1. Certain instructions such as output instructions (for example, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bit above.
Glossary-5
Glossary
M
Master Control Relay The Master Control Relay (MCR) is an American relay ladder logic master switch for energizing and de-energizing power flow (current path). A de-energized current path corresponds to an instruction sequence that writes a zero value instead of the calculated value, or, to an instruction sequence that leaves the existing memory value unchanged.
Memory Area
In SIMATIC S7 a CPU has three memory areas:
S Load memory S Work memory S System memory

Memory Indirect Addressing A type of addressing in which the address of an instruction indicates the location of the value with which the instruction is to work.
Mnemonic Representation
Mnemonic representation is an abbreviated form for displaying the names of addresses and programming instructions in the program (for example, I stands for input). STEP 7 supports the international representation (based on the English language), and the SIMATIC representation (based on the German abbreviations of the instruction set and the SIMATIC addressing conventions).
N
Nesting Stack The nesting stack is a storage byte used by the nesting instructions A(, O(, X(, AN(, ON(, XN(. A total of eight bit logic instructions can be stacked.
Network
Networks subdivide LAD and FBD blocks into complete current paths and Statement List (STL) blocks into clear units.
O
OR Bit The OR bit is needed if you perform a logical AND before OR operation. The OR bit shows these instructions that a previously executed AND function has supplied the value 1, thus forestalling the result of the logical OR operation. Any other bit-processing command resets the OR bit (see Section 5.4).
Glossary-6
Glossary
Overflow Bit
The status bit OV stands for overflow. An overflow can occur, for example, after a math operation.
P
Pointer You can use a pointer to identify the address of a variable. A pointer contains an identifier instead of a value. If you allocate an actual parameter type, you provide the memory address. With STEP 7 you can either enter the pointer in pointer format or simply as an identifier (for example, M 50.0). In the following example, the pointer format is shown with which data from M 50.0 is accessed: P#M50.0
Project
A project is a folder for all objects in an automation task, irrespective of the number of stations, modules, and how they are connected in networks.
R
Reference Data Reference data are used to check your S7 program and include the cross-reference list, the assignment lists, the program structure, the list of unused addresses, and the list of addresses without symbols.
Register Indirect Addressing
A type of addressing in which the address of an instruction indicates indirectly via an address register and an offset the memory location of the value with which the instruction is to work.
Result of Logic Operation (RLO)
The result of logic operation (RLO) is the result of the logic string which is used to process other binary signals. The execution of certain instructions depends entirely on their preceding RLO.
S
S7 Program A folder for blocks, source files, and charts for S7 programmable controllers. The S7 program also includes the symbol table.
Shared Data Block (DB)
A shared data block is a DB whose address is loaded in the DB address register when it is opened. It provides storage and data for all logic blocks (FCs, FBs, or OBs) that are being executed.
Glossary-7
Glossary
In contrast, an instance DB is designed to be used as specific storage and data for the FB with which it has been associated.
SIMATIC Manager
The SIMATIC Manager is the graphical user interface for SIMATIC users under Windows 95.
Source File
A source file (text file) is part of a program created either with a graphic or a text-oriented editor and is compiled into an executable S7 user program or the machine code for M7. An S7 source file is stored in the Sources folder under the S7 program folder.
Statement
A statement is the smallest independent part of a user program created in a textual language. The statement represents a command for the processor.
Statement List (STL)
Statement List (STL) is a textual representation of the STEP 7 programming language, similar to machine code. STL is the assembler language of STEP 5 and STEP 7. If you program in STL, the individual statements represent the actual steps in which the CPU executes the program.
Station
A station is a device which can be connected to one or more subnets; for example, the programmable controller, programming device, and operator station.
Status Bit
The status bit stores the value of a bit that is referenced. The status of a bit instruction that has read access to the memory (A, AN, O, ON, X, XN) is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that has write access to the memory (S, R, =) is the same as the value of the bit to which the instruction writes or, if no writing takes place, the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access the memory. Such instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.
Status Word
The status word is part of the register of the CPU. It contains status information and error information which is displayed when specific STEP 7 commands are executed. The status bits can be read and written on by the user, the error bits can only be read.
STL Source File
A source file programmed in Statement List; corresponds to a source or text file.
Glossary-8
Glossary
Stored Overflow Bit
The status bit OS stands for stored overflow bit of the status word. An overflow can take place, for example, after a math operation.
Symbol
A symbol is a name which can be defined by the user subject to syntax guidelines. After it has been declared (for example, as a variable, data type, jump label, block etc) the symbol can be used for programming and for operator interface functions. Example: Address: I 5.0, data type: BOOL, Symbol: momentary contact switch / emergency stop.
Symbol Table
A table in which the symbols of addresses for shared data and blocks are allocated. Examples: Emergency Stop (symbol) -I 1.7 (address) or closed-loop control (symbol) - SFB24 (block).
Symbolic Addressing
In symbolic addressing, the address being processed is designated with a symbol (as opposed to an absolute address).
System Function (SFC)
A system function is a function (without a memory) that is integrated in the S7 operating system and can, if necessary, be called from the STEP 7 user program like a function (FC).
System Function Block (SFB)
A system function block (SFB) is a function (with a memory) that is integrated in the S7 operating system and can, if necessary, be called from the STEP 7 user program like a function block (FB).
U
User Data Types (UDTs) User data types are special data structures which you can create yourself and use in the entire user program after they have been defined. They can be used like elementary or complex data types in the variable declaration of logic blocks (FCs, FBs, OBs) or as a template for creating data blocks with the same data structure.
User Program
The user program contains all the statements and declarations and all the data for signal processing which can be used to control a device or a process. It is part of a programmable module (CPU, FM) and can be structured with smaller units (blocks).
User Program Structure
The user program structure describes the call hierarchy of the blocks within an S7 program and provides an overview of the blocks used and their dependency.
Glossary-9
Glossary
V
Variable Declaration The variable declaration includes a symbolic name, a data type and, optionally, an initial value, an address and a comment.
Variable Declaration Table
The variable declaration table is used for declaring the local data of a logic block, when programming takes place in the Incremental Editor.
Variable Table (VAT)
The variable table is used to collect together the variables that you want to monitor and modify and set their relevant formats.
Glossary-10
Index
Symbols
)MCR. See Restore RLO, End MCR instruction +. See Instructions, integer math, adding an integer to accumulator 1 +I. See Four-function math, Adding two 16-bit integers; Instructions, integer math, adding two 16-bit integers +R. See Floating-point math, Adding two floating-point numbers =. See Assign (=) instruction Accumulators adding a constant to an address register, 4-7 adding an integer to accumulator 1, 9-6 description of, 2-10 functions Accumulator 2 to Accumulator 1 (POP), 4-2 Decrement Accumulator 1 (DEC), 4-6 Increment Accumulator 1 (INC), 4-6 handling the contents of, 4-24-6 information interchange using Load and Transfer instructions, 8-2 loading the status word into, 8-6 operation of, 2-10 with comparison instructions, 11-2 with floating-point math instructions, 10-210-3 with integer math instructions, 9-29-3 with Load and Transfer instructions, 8-2 with word logic instructions, 13-2, 13-3, 13-6 operations Accumulator 1 to Accumulator 2 (PUSH), 4-2 Decrement Accumulator 1 (DEC), 4-6 Increment Accumulator 1 (INC), 4-6 reversing the order of bytes within accumulator 1 Change Byte Sequence in Accumulator 1, 16 bits (CAW) instruction, 12-13 Change Byte Sequence in Accumulator 1, 32 bits (CAD) instruction, 12-13 time value in, 6-4 Toggle ACCU 1 with ACCU 2, 4-2 Toggle the contents of, 4-2 transferring the contents of to the status word, 8-6
A
ABS. See Absolute value, forming the absolute value of a real (floatingpoint ) number Absolute addressing, practical application, B-4 Absolute value definition of, 10-6 forming the absolute value of a real (floating-point) number, 10-6 Accumulator 1 to Accumulator 2 (PUSH), 4-2 Accumulator 2 to Accumulator 1 (POP), 4-2 Accumulator operations and address register instructions, 4-24-6 Accumulator 1 to Accumulator 2 (PUSH), 4-2 Accumulator 2 to Accumulator 1 (POP), 4-2 Decrement Accumulator 1 (DEC), 4-6 Decrement Accumulator 1 (DEC), 4-6 Increment Accumulator 1 (INC), 4-6 Increment Accumulator 1 (INC), 4-6 Toggle ACCU 1 with ACCU 2, 4-2
Index-1
Index
ACOS. See Secant Activate MCR Area (MCRA) instruction, 17-1117-12 Actual parameter, 17-2, 17-3 Actual parameters, assignment, 17-8 AD. See And Double Word instruction Address assigning addresses to a Call (CALL) instruction, 17-3 bits of the status word as, 5-13 constants as, 13-2 description of, 2-2 label for a jump instruction, 16-2 label for a loop instruction, 16-2 of instructions Assign (=), 5-25 Conditional Call (CC), 17-7 counter, 7-10 Edge Negative (FN), 5-19 Edge Positive (FP), 5-19 Load (L) and Transfer (T), 8-38-5 Open a Data Block (OPN), 15-2 Reset (R), 5-23 Set (S), 5-23 Timer, 6-17 Unconditional Call (UC), 17-7 symbolic, 17-3 types address identifier and location, 2-52-6 constants, 2-3, 13-2 data block, 2-4 function (FC), 2-5 function block (FB), 2-5 location in status word, 2-3 symbolic, 2-4 system function (SFC), 2-5 system function block (SFB), 2-5 Address register, adding a real number to an address register, 4-7 Address registers, 3-6 loading and transferring between, 8-118-12
Addressing absolute, 17-3, B-4 area-crossing register indirect, 3-113-14 area-internal register indirect, 3-73-9 constants, 2-3 direct, 3-2 immediate, 3-2 memory indirect, 3-33-5 pointer format area-crossing register indirect, 3-133-14 area-internal register indirect, 3-8 areainternal register indirect, 3-93-10 memory indirect, 3-43-5 ranges, 2-9 symbolic, 2-4, 17-3, B-3 And (A), using counters as bit operands, 7-2 And (A) instruction, 5-3 And before Or, 5-155-16 And Double Word (AD) instruction, 13-713-8 And Not (AN), using counters as bit operands, 7-2 And Not (AN) instruction, 5-3 And Word (AW) instruction, 13-413-5 combining accumulator and constant, 13-413-5 ANY, 17-9 Arc cosine (ACOS), 10-1310-15 Arc sine (ASIN), 10-1310-14 Arc tangent (ATAN), 10-13 Area-crossing register indirect addressing, 3-113-15 Area-internal register indirect addressing, 3-73-9 Areas of memory address ranges, 2-9 bit memory, 2-8 counter, 2-8 data block, 2-8 I/O (external I/O), 2-8 local data, 2-8 peripheral I/O. See Areas of memory, I/O (external I/O) process image input, 2-8 process image output, 2-8 timer, 2-8 ASIN. See Cosecant Assign (=) instruction, 5-20, 5-245-25 Assigning addresses to a Call (CALL) instruction, 17-3 ATAN. See Cotangent AW. See And Word instruction
Index-2
Index
B
BCD to Double Integer (BTD) conversion instruction, 12-4 BCD to Integer (BTI) conversion instruction, 12-312-4 BCDF. See Errors, binary coded decimal conversion BEC. See Blocks, ending: Block End Conditional instruction Beginning a logic string, 2-122-13 BEU. See Blocks, ending: Block End Unconditional instruction Binary coded decimal (BCD) format loading a count in, 8-10 loading a time in, 8-9 Binary coded decimal (BCD) numbers converting, 12-212-9 structure of a BCD number converted from a 32-bit integer, 12-6 structure of a BCD number to be converted from integer, 12-5 structure of a BCD number to be converted to integer, 12-3 structure of a32-bit BCD number to be converted to double integer, 12-4 Binary result (BR), bit of status word, 2-16 Bit logic instructions, And (A), using counters as Boolean operands, 7-2 Bit logic Boolean, 5-25-12 practical applications, B-3B-6
Bit logic instructions, 5-25-5 And Not (AN), using counters as Boolean operands, 7-2 Assign (=), 5-20, 5-245-25 Clear RLO (CLR), 5-265-27 Edge Negative (FN), 5-165-19 Edge Positive (FP), 5-165-19 Exclusive Or (X), using counters as Boolean operands, 7-2 Exclusive Or Not (XN), using counters as Boolean operands, 7-2 Negate RLO (NOT), 5-26 Or (O), using counters as Boolean operands, 7-2 Or Not (ON), using counters as Boolean operands, 7-2 practical applications, B-3B-6 Reset (R), 5-20, 5-215-23, 7-87-9 counter, 7-4 timer, 6-6 Save RLO in BR Register (SAVE), 5-26 Set (S), 5-20, 5-215-23 counter, 7-3, 7-87-9 Set RLO (SET), 5-26, 5-27 using counters as bit operands, 7-2 Bit memory area of memory, 2-8 address ranges, 2-9 Blocks, ending Block End Conditional (BEC) instruction, 17-16 Block End Unconditional (BEU) instruction, 17-16 Boolean bit logic, 5-25-12 And (A) instruction, 5-3 And Not (AN) instruction, 5-3 checking condition codes (CC 1 and CC 0), 2-142-15 checking for overflow, 5-125-13 nesting expressions, 5-145-15 output of logic string, 5-20 BR. See Binary result BTD. See BCD to Double Integer conversion instruction BTI. See BCD to Integer conversion instruction
Index-3
Index
C
CAD. See Change Byte Sequence in Accumulator 1 conversion instruction, 32 bits CALL. See Call instruction Call instruction, 17-317-5 Calling a function that delivers a return value, 17-6 Calling a program segment multiple times, 16-8 CAW. See Change Byte Sequence in Accumulator 1 conversion instruction, 16 bits CC. See Conditional Call instruction CC 1 and CC 0. See Condition codes CD. See Count Down instruction CDB. See Exchange Shared DB and Instance DB instruction Change Byte Sequence in Accumulator 1 conversion instruction 16 bits (CAW), 12-13 32 bits (CAD), 12-13 Checking condition codes (CC 1 and CC 0), 2-142-15 Clearing RLO (CRL) instruction, 5-265-27 the result of logic operation, 5-265-27 CLR. See Clear RLO instruction Comparing two integers, 11-311-5 two real numbers, 11-511-6 Comparison instructions, 11-211-3 Compare Double Integer, 11-311-5 Compare Integer, 11-311-5 Compare Real Number, 11-5 criteria for comparisons, 11-2 operation of accumulators, 11-2 practical applications, B-10B-11 Complements, forming, 12-14
Condition codes (CC 1 and CC 0) as affected by Compare instructions, 11-4, 11-5 as affected by floating-point math instructions, 10-4 as affected by integer math instructions, 9-4 as affected by the shift and rotate instructions, 14-2 as affected by word logic instructions, 13-2 bits of status word, 2-142-15 instructions that evaluate CC 1 and CC 0, 11-6 relationship to conditional jump instructions, 16-6 Conditional Call (CC) instruction, 17-7 Conditional jump instructions Jump If BR = 0 (JNBI), 16-5 Jump If BR = 1 (JBI), 16-5 Jump If Minus (JM), 16-6 Jump If Minus or Zero (JMZ), 16-6 Jump If Not Zero (JN), 16-6 Jump If OS = 1 (JOS), 16-5 Jump If OV = 1 (JO), 16-5 Jump If Plus (JP), 16-6 Jump If Plus or Zero (JPZ), 16-6, 16-7 Jump If RLO = 0 (JCN), 16-4 Jump If RLO = 0 with BR (JNB), 16-4 Jump If RLO = 1 (JC), 16-4 Jump If RLO = 1 with BR (JCB), 16-4 Jump If Unordered (JUO), 16-6 Jump If Zero (JZ), 16-6 relationship of condition codes CC 1 and CC 0, 16-6
Index-4
Index
Constants adding an integer constant to accumulator 1, 9-6 as addresses of word logic instructions, 13-2, 13-413-7 Decrement Accumulator 1 by an 8-bit constant, 4-6 Decrementing Accumulator 1 by an 8-bit constant, 4-6 Incrementing Accumulator 1 by an 8-bit constant, 4-6 used as address, 2-3 Conversion instructions BCD to Double Integer (BTD), 12-4 BCD to Integer (BTI), 12-312-4 Change Byte Sequence in Accumulator 1 16 bits (CAW), 12-13 32 bits (CAD), 12-13 Double Integer to BCD (DTB), 12-6 Double Integer to Real (DTR), 12-7 Integer to BCD (ITB), 12-5 Integer to Double Integer (ITD), 12-6 Negate Real Number (NEGR), 12-1412-15 Ones Complement Double Integer (INVD), 12-14 Ones Complement Integer (INVI), 12-14 overview of number conversion and rounding, 12-12 Round (RND), 12-9 Round to Lower Double Integer (RND), 12-11 Round to Upper Double Integer (RND+), 12-10 Truncate (TRUNC), 12-12 Twos Complement Double Integer (NEGD), 12-14 Twos Complement Integer (NEGI), 12-1412-15 Converting 32-bit floating-point numbers to 32-bit integers, 12-812-12 binary coded decimal numbers and integers, 12-212-9 numbers, 12-12 COS. See Cosine Cosine (COS), 10-13 Count Down (CD) instruction, 7-5 Count Up (CU) instruction, 7-5 Count value, format, 7-67-7
Counters area of memory, 2-8 address ranges, 2-9 components, 7-2 count instructions, bit logic instructions, 7-2 count value, format, 7-67-7 definition of, 7-2 enabling, 7-4, 7-87-9 instructions used with counters, 7-27-9 bit logic, 5-225-23, 7-2 Count Down (CD), 7-2, 7-5 Count Up (CU), 7-2, 7-5 Enable (FR), 7-2, 7-4 Load Current Counter Value into Accumulator 1 as Binary Coded Decimal (LC), 7-2, 8-10 Load Current Counter Value into Accumulator 1 as Integer, 7-2 practical applications, B-10B-11 Reset (R), 7-2, 7-4, 7-87-9 Set (S), 7-2, 7-3, 7-87-9 resetting, 7-2, 7-4, 7-87-9 setting, 7-2, 7-3, 7-87-9 types Count Down (CD), 7-2, 7-87-9 Count Up (CU), 7-2, 7-87-9 CPU, registers, 3-63-11 nesting stack, 2-10 operation of accumulators, 2-10 pointers, 3-6 status word, 2-122-16 time value in accumulator 1, 6-4 CU. See Count Up instruction
Index-5
Index
D
Data block (DB) area of memory, 2-8 address ranges, 2-9 instance, 17-3 lengths and numbers, loading, 15-315-4 loading the length of a shared data block into accumulator 1 (L DBLG), 8-12, 15-3 loading the length of an instance data block into accumulator 1 (L DILG), 8-12, 15-3 loading the number of a shared data block into accumulator 1 (L DBNO), 8-12, 15-315-4 loading the number of an instance data block into accumulator 1 (L DINO), 8-12, 15-3 registers, exchanging, 15-2 Data block (DB) instructions Exchange Shared DB and Instance DB (CDB), 15-2 Load Length of Instance Data Block in Accumulator 1 (DILG), 15-3 Load Length of Shared Data Block in Accumulator 1 (DBLG), 15-3 Load Number of Instance Data Block in Accumulator 1 (DINO), 15-3 Load Number of Shared Data Block in Accumulator 1 (DBNO), 15-315-4 Open a Data Block (OPN), 15-2 Data types ANY, 17-9 for actual and formal parameters, 17-3 DBLG. See Load Length of Shared DB in Accumulator 1 instruction DBNO. See Load Number of Shared DB in Accumulator 1 instruction Deactivate MCR Area (MCRD) instruction, 17-1117-12 DEC. See Decrement Accumulator 1 Decrement Accumulator 1 (DEC), 4-6 DILG. See Load Length of Instance DB in Accumulator 1 instruction DINO. See Load Number of Instance DB in Accumulator 1 instruction Direct addressing, 3-2 Double Integer to BCD (DTB) conversion instruction, 12-6 Double Integer to Real (DTR) conversion instruction, 12-7 Double integers, comparing two, 11-311-5 DTB. See Double Integer to BCD conversion instruction
DTR. See Double Integer to Real conversion instruction
E
Edge Negative (FN) instruction, 5-165-19 Edge Positive (FP) instruction, 5-165-19 Enable (FR) instruction counters, 7-4, 7-87-9 timers, 6-6 Enable output (ENO). See Binary result Ending blocks Block End Conditional (BEC) instruction, 17-16 Block End Unconditional (BEU) instruction, 17-16 Errors, binary coded decimal conversion (BCDF), 12-3, 12-4 Examples, practical applications of instructions, B-2B-14 Exchange Shared DB and Instance DB (CDB) instruction, 15-2 Exchange the contents of accumulators, 4-2 Exclusive Or (X), using counters as Boolean operands, 7-2 Exclusive Or Not (XN), using counters as Boolean operands, 7-2 Exclusive Or Word (XOW) instruction, 13-3, 13-413-5 combining accumulator and constant, 13-413-5 EXP. See Exponential value to base E Exponential value to base E, EXP, 10-12 Extended Pulse Timer (SE), 6-5, 6-96-10
F
FBs. See Function blocks FCs. See Functions First check (FC) bit of status word, 2-122-13 result of, 2-12
Index-6
Index
Floating-point math Adding two floating-point numbers (+R), 10-3, 10-4 instructions forming the absolute value of a real number (ABS), 10-6 overview of four-function math, 10-2 relationship to accumulators, 10-210-3 valid ranges of result, 10-4 Floating-point math, extended operations arc cosine (ACOS), 10-1310-15 arc tangent (ATAN), 10-13 Floating-point math, extended math operations, arc sine (ASIN), 10-1310-14 FN. See Edge Negative instruction Formal parameter, 17-2 Formal parameters, 17-3 Format count value, 7-67-7 time value, 6-4 Forming complements, 12-14 Four-function math, Adding two 16-bit integers (+I), 9-3 FP. See Edge Positive instruction FR. See Enable instruction Function (FC) as address of an instruction, 2-5 calling FCs with the Call (CALL) instruction, 17-317-5 calling FCs with the Conditional Call (CC) instruction, 17-7 calling FCs with the Unconditional Call (UC) instruction, 17-7 dependency on Master Control Relay (MCR), 17-11 Function block (FB) as address of an instruction, 2-5 calling FBs with the Call (CALL) instruction, 17-317-5 calling FBs with the Conditional Call (CC) instruction, 17-7 calling FBs with the Unconditional Call (UC) instruction, 17-7 dependency on Master Control Relay (MCR), 17-11
I
I/O (external I/O) area of memory, 2-8 address ranges, 2-9 Image registers. See Process-image Immediate addessing, 3-2 INC. See Increment Accumulator 1 Increment Accumulator 1 (INC), 4-6 Instruction statement addressing constants, 2-3 symbolic, 2-4 structure of, 2-22-7 Instructions accumulator operation and address register, 4-24-6 alphabetical listing, international names, A-12A-16 bit logic, practical applications, B-3B-6 comparison, 11-211-8 criteria for comparison, 11-2 operation of accumulators, 11-2 practical applications, B-10B-11 conversion, overview of number conversion and rounding, 12-12 counter, 7-27-13 practical applications, B-10B-11 dependent on the Master Control Relay (MCR), 17-11 dependent on the Master control Relay (MCR), 17-10 floating-point math overview of four-function math, 10-2 relationship to accumulators, 10-210-3 valid ranges of results, 10-4 integer math overview of four-function math instructions, 9-2 practical applications, B-12B-13 relationship to accumulators, 9-29-3 valid ranges of results, 9-4 jump, unconditional, 16-316-4 Load (L) and Transfer (T), 8-28-12 area-crossing indirect addressing, 8-5
Index-7
Index
byte, word, or double word as address, 8-5 definition of, 8-2 direct addressing, 8-4 immediate addressing, 8-3 indirect addressing, 8-4 information interchange, 8-2 loading and transferring between address registers (LAR and TAR), 8-118-12 loading bits of the status word into accumulator 1, 8-6 loading the status word into accumulator 1, 8-6 transferring the contents of accumulator 1 to the status word, 8-6 loading and transferring between address registers (LAR and TAR), 8-118-12 logic control, 16-216-11 See also Jump instructions Loop (LOOP), 16-8 providing a label as address, 16-8 using efficiently, 16-9 practical applications, B-2B-14 program control, assigning addresses to a call, 17-3 rotate, 14-614-8 shift, 14-214-6 signed numbers, 14-4 unsigned numbers, 14-214-3 shift and rotate, 14-214-6 that evaluate the condition codes (CC 1 and CC 0), 9-4, 10-4 that evaluate the overflow bit (OV) of the status word, 9-4, 10-4 that evaluate the stored overflow bit (OS) of the status word, 9-4, 10-4 timer, 6-26-17 practical applications, B-7B-10 Transfer (T). See Load (L) and Transfer (T) instructions word logic, 13-213-8 16-bit, 13-313-8 32-bit, 13-613-8 accumulator administration, 13-2, 13-3, 13-6 constants as addresses, 13-2 influence on status word bits, 13-2 practical applications, B-14 Instructions that affect the status word, 5-10 Integer math, adding a real to an address register, 4-7
Integer math instructions adding an integer constant to accumulator 1, 9-6 adding two 16-bit integers (+I), 9-3 overview of four-function math instructions, 9-2 practical applications, B-12B-13 relationship to accumulators, 9-29-3 valid ranges of results, 9-4 Integer to BCD (ITB) conversion instruction, 12-5 Integer to Double Integer (ITD) conversion instruction, 12-6 Integers adding to accumulator 1, 9-6 comparing two, 11-311-5 converting, 12-212-9 International names for instructions, alphabetical listing, A-12A-16 International names of the statement list (STL) instructions, A-12 INVD. See Ones Complement Double Integer conversion instruction Inverting numbers bit by bit, 12-14 INVI. See Ones Complement Integer conversion instruction ITB. See Integer to BCD conversion instruction ITD. See Integer to Double Integer conversion instruction
J
JBI. See Jump If BR = 1 instruction JC. See Jump If RLO = 1 instruction JCB. See Jump If RLO = 1 with BR instruction JCN. See Jump If RLO = 0 instruction JL. See Jump to List instruction JM. See Jump If Minus instruction JMZ. See Jump If Minus or Zero instruction JN. See Jump If Not Zero instruction JNB. See Jump If RLO = 0 with BR instruction JNBI. See Jump If BR = 0 instruction JO. See Jump If OV = 1 instruction JOS. See Jump If OS = 1 instruction JP. See Jump If Plus instruction JPZ. See Jump If Plus or Zero instruction JU. See Jump Unconditional instruction Jump If BR = 0 (JNBI) instruction, 16-5 Jump If BR = 1 (JBI) instruction, 16-5 Jump If Minus (JM) instruction, 16-6
Index-8
Index
Jump If Minus or Zero (JMZ) instruction, 16-6 Jump If Not Zero (JN) instruction, 16-6 Jump If OS = 1 (JOS) instruction, 16-5 Jump If OV = 1 (JO) instruction, 16-5 Jump If Plus (JP) instruction, 16-6 Jump If Plus or Zero (JPZ) instruction, 16-6, 16-7 Jump If RLO = 0 (JCN) instruction, 16-4 Jump If RLO = 0 with BR (JNB) instruction, 16-4 Jump If RLO = 1 (JC) instruction, 16-4 Jump If RLO = 1 with BR (JCB) instruction, 16-4 Jump If Unordered (JUO) instruction, 16-6 Jump If Zero (JZ) instruction, 16-6 Jump instructions, 16-316-10 condition based on BR, OV, or OS bit of status word, 16-5 condition based on result in condition code bits (CC 1 and CC 0) of status word, 16-616-7 condition based on result of logic operation (RLO), 16-416-5 conditional Jump If BR = 0 (JNBI), 16-5 Jump If BR = 1 (JBI), 16-5 Jump If Minus (JM), 16-6 Jump If Minus or Zero (JMZ), 16-6 Jump If Not Zero (JN), 16-6 Jump If OS = 1 (JOS), 16-5 Jump If OV = 1 (JO), 16-5 Jump If Plus (JP), 16-6 Jump If Plus or Zero (JPZ), 16-6, 16-7 Jump If RLO = 0 (JCN), 16-4 Jump If RLO = 0 with BR (JNB), 16-4 Jump If RLO = 1 (JC), 16-4 Jump If RLO = 1 with BR (JCB), 16-4 Jump If Unordered (JUO), 16-6 Jump If Zero (JZ), 16-6 label as address, 16-2 overview of, 16-2 unconditional, 16-316-4 Jump to List (JL), 16-3 Jump Unconditional (JU), 16-3 Jump to List (JL) instruction, 16-3 Jump Unconditional (JU) instruction, 16-3 JUO. See Jump If Unordered instruction JZ. See Jump If Zero instruction
K
Keywords, definition, C-1
L
L. See Load and Transfer instructions Label, as address of a jump or loop instruction, 16-2 LAR. See Loading and transferring between address registers LC. See Load Current Value into Accumulator 1 as Binary Coded Decimal LN. See Natural Logarithm Load (L) and Transfer (T) instructions, 8-28-12 See also Instructions, Load (L) and Transfer (T) area-crossing indirect addressing, 8-5 byte, word, or double word as address, 8-5 definition of, 8-2 direct addressing, 8-4 immediate addressing, 8-3 indirect addressing, 8-4 information interchange, 8-2 between modules and memory areas, 8-2 by way of the accumulator, 8-2 Load Current Counter Value into Accumulator 1 as Binary Coded Decimal (LC), 8-10 loading and transferring between address registers (LAR and TAR), 8-118-12 loading bits of the status word into accumulator 1, 8-6 loading the length of a shared data block into accumulator 1 (L DBLG), 8-12 loading the length of an instance data block into accumulator 1 (L DILG), 8-12 loading the number of a shared data block into accumulator 1 (L DBNO), 8-12 loading the number of an instance data block into accumulator 1 (L DINO), 8-12 loading the status into accumulator 1, 8-6 transferring the contents of accumulator 1 to the status word, 8-6 Load Current Value into Accumulator 1 as Binary Coded Decimal counter, 7-2 timer, 6-2
Index-9
Index
Load Length of Instance DB in Accumulator 1 (DILG) instruction, 15-3 Load Length of Shared DB in Accumulator 1 (DBLG) instruction, 15-3 Load Number of Instance DB in Accumulator 1 (DINO) instruction, 15-3 Load Number of Shared DB in Accumulator 1 (DBNO) instruction, 15-315-4 Loading a count value format, 7-6 in binary coded decimal (BCD) format (LC counter word), 8-10 in binary form (L counter word), 8-8 Loading a time value format, 6-3 in binary coded decimal (BCD) format (LC timer word), 8-9 in binary form (L timer word), 8-7 range, 6-5 Loading and transferring between address registers, 8-118-12 Loading data block lengths and numbers, 15-315-4 Loading the length of a data block into accumulator 1 instance data block (L DILG), 8-12 shared data block (L DBLG), 8-12 Loading the number of a data block into accumulator 1 instance data block (L DINO), 8-12 shared data block (L DBNO), 8-12 Local data, area of memory, 2-8 address ranges, 2-9 Logic control instructions, 16-216-11 See also Jump and Loop instructions Logic string beginning of, 2-122-13 definition of, 2-122-13 output of, 5-20 terminating, 5-20 Loop (LOOP) instruction, 16-8 label as address, 16-2, 16-8 using efficiently, 16-9
Master Control Relay (MCR) instructions, 17-1017-15 See also Program control instructions nesting, 17-1317-15 MCR functions, Important notes, 17-15 MCR(. See Save RLO in MCR Stack, Begin MCR instruction MCRA. See Activate MCR Area instruction MCRD. See Deactivate MCR Area instruction Memory areas address ranges, 2-9 bit memory, 2-8 counter, 2-8 data block, 2-8 I/O (external I/O), 2-8 local data, 2-8 process image input, 2-8 process image output, 2-8 timer, 2-8 Memory indirect addressing, 3-33-5 Multiplying a number by 1, 12-14
N
Natural Logarithm (LN), 10-11 Negate Real Number (NEGR) conversion instruction, 12-1412-15 Negate RLO (NOT) instruction, 5-26 Negating numbers, 12-14 Negating the result of logic operation, 5-26 Negative edge transitions, 5-165-19 NEGD. See Twos Complement Double Integer conversion instruction NEGI. See Twos Complement Integer conversion instruction NEGR. See Negate Real Number conversion instruction Nesting expressions, 5-145-17 And before Or, 5-155-16 Nesting stack, 2-10, 5-14 Normally closed contact, 5-7 Normally open contact, 5-6 NOT. See Negate RLO instruction
M
Master Control Relay (MCR) dependency on, 17-10, 17-11 effect on Set (S) and Reset (R) instructions, 5-215-22, 17-10 implementation of, 17-13 Important notes, 17-15
Index-10
Index
O
Off-Delay Timer (SF), 6-5, 6-156-16 On-Delay Timer (SD), 6-5, 6-116-12 Ones Complement Double Integer (INVD) conversion instruction, 12-14 Ones Complement Integer (INVI) conversion instruction, 12-14 Open a Data Block (OPN) instruction, 15-2 Operand. See Address OPN. See Open a Data Block instruction OR, bit of status word, 2-14 Or (O), using counters as bit operands, 7-2 Or branch, nesting expressions, 5-145-17 Or Not (ON), using counters as bit operands, 7-2 Or Word (OW) instruction, 13-3, 13-413-5 combining accumulator and constant, 13-413-5 Order of processing And with Or instructions, 5-155-16 OS. See Stored overflow Output of a logic string, 5-20 OV. See Overflow Overflow (OV) as affected by comparing two real numbers, 11-5 as affected by floating-point math instructions, 10-4 as affected by integer math instructions, 9-4 as affected by the shift and rotate instructions, 14-2 as affected by word logic instructions, 13-2 bit of status word, 2-14
Process image input area of memory, 2-8 Process image output area of memory, 2-8 Process-image input area of memory, address ranges, 2-9 Process-image output area of memory, address ranges, 2-9 Processing order for And with Or instructions, 5-155-16 Program control instructions Activate MCR Area, 17-1117-12 assigning addresses to a Call (CALL) instruction, 17-3 Block End Conditional (BEC), 17-16 Block End Unconditional (BEU), 17-16 Call (CALL), 17-317-5 Conditional Call (CC), 17-7 Deactivate MCR Area, 17-1117-12 Master Control Relay (MCR) functions, 17-1017-15 Restore RLO, End MCR: )MCR, 17-1117-12, 17-1317-14 Save RLO in MCR Stack, Begin MCR: MCR(, 17-1117-12, 17-1317-14 Unconditional Call (UC), 17-7 Programming, practical applications, B-2B-14 Pulse Timer (SP), 6-56-6, 6-76-8 PUSH. See Accumulator 1 to Accumulator 2
R
R. See Reset instruction Real number comparing two real numbers, 11-5 forming the absolute value, 10-6 Registers address, 3-6 CPU, 3-63-11 Exchange Shared DB and Instance DB (CDB) instruction, 15-2 exchanging data block registers, 15-2 image. See Process-image Reset (R) instruction, 5-20, 5-215-23 counters, 7-4, 7-87-9 timers, 6-6 Resetting a counter, 7-4 a timer, 6-6
P
Parallel branch, nesting expressions, 5-145-17 Parameters actual, 17-3 formal, 17-3 Pointer format area-crossing register indirect addressing, 3-133-14 areainternal register indirect addressing, 3-9 memory indirect addressing, 3-43-5 POP. See Accumulator 2 to Accumulator 1 Positive edge transitions, 5-165-19
Index-11
Index
Restore RLO, End MCR instruction: )MCR, 17-1117-12, 17-1317-14 Result of logic operation (RLO) bit of status word, 2-13 clearing, 5-265-27 instructions that do not affect the RLO, 4-6 negating, 5-26 relationship to Block End instructions, 17-16 saving, 5-26 setting, 5-26, 5-27 stored in nesting stack, 5-14 transitions of, 5-165-19 with Assign (=) instruction, 5-245-25 Retentive On-Delay Timer (SS), 6-5, 6-136-14 Return value, calling a function that delivers a return value, 17-6 Reversing the order of bytes within accumulator 1, 12-13 RLD. See Rotate instructions, Rotate Left Double Word RLDA. See Rotate instructions, Rotate Accumulator 1 Left via CC 1 RLO. See Result of Logic Operation RND. See Round conversion instruction RND+. See Round to Upper Double Integer conversion instruction RND. See Round to Lower Double Integer conversion instruction Rotate instructions, 14-614-8 Rotate Accumulator 1 Left via CC 1 (RLDA), 14-8 Rotate Accumulator 1 Right via CC 1 (RRDA), 14-8 Rotate Left Double Word (RLD), 14-714-8 Rotate Right Double Word (RRD), 14-7 Round (RND) conversion instruction, 12-9 Round to Lower Double Integer (RND) conversion instruction, 12-11 Round to Upper Double Integer (RND+) conversion instruction, 12-10 Rounding 32-bit floating-point numbers to double integers, 12-812-11 numbers, overview, 12-12 real numbers to double integers, 12-812-11 RRD. See Rotate instructions, Rotate Right Double Word RRDA. See Rotate instructions, Rotate Accumulator 1 Right via CC 1
S
S. See Set instruction S5 TIME time base, 6-46-5 time value, 6-3 SAVE. See Save RLO in BR Register instruction Save RLO in BR Register (SAVE) instruction, 5-26 Save RLO in MCR Stack, Begin MCR instruction: MCR(, 17-1117-12, 17-1317-14 Saving, the result of logic operation, 5-26 SD. See OnDelay Timer SE. See Extended Pulse Timer SET. See Set RLO instruction Set (S) instruction, 5-20, 5-215-23 counters, 7-3 Set RLO (SET) instruction, 5-26, 5-27 Setting a counter, 7-3, 7-87-9 the result of logic operation, 5-26, 5-27 SF. See OffDelay Timer SFBs. See System function blocks SFCs. See System functions Shift and rotate instructions, 14-214-8 Shift instructions, 14-214-6 effect on condition codes CC 1 and CC 0 and on the Overflow bit(OV) of the status word, 14-2 method of operation, 14-2 Shift Left Double Word (SLD, 32 bits), 14-2 Shift Left Word (SLW, 16 bits), 14-2 Shift Right Double Word (SRD, 32 bits), 14-2, 14-3 Shift Right Word (SRW, 16 bits), 14-2 Shift Sign Double Integer (SSD, 32 bits), 14-4 Shift Sign Integer (SSI, 16 bits), 14-4 signed numbers, 14-4 unsigned numbers, 14-214-3 SIMATIC and International mnemonic abbreviations of the statement list (STL) instructions, A-2, A-7 SIN. See Sine Sine (SIN), 10-13 SLD. See Shift instructions, Shift Left Double Word SLW. See Shift instructions, Shift Left Word
Index-12
Index
SP. See Pulse Timer SQR. See Square SQRT. See Square root Square (SQR), 10-9 Square root (SQRT), 10-9 SRD. See Shift instructions, Shift Right Double Word SRW. See Shift instructions, Shift Right Word SS. See Retentive OnDelay Timer SSD. See Shift instructions, Shift Sign Double Integer SSI. See Shift instructions, Shift Sign Integer STA. See Status, bit of status word Starting a logic string, 2-122-13 Starting a timer, 6-5 Statement. See Instruction statement Statement list (STL), 1-1 definition of, 1-1 Status (STA), bit of status word, 2-13 Status word binary result (BR) bit, 2-16 bits affected by floating-point math instructions, 10-4 bits affected by integer math instructions, 9-4 bits affected by the shift and rotate instructions, 14-2 condition code bits (CC 1 and CC 0), overflow bit (OV) as affected by word logic instructions, 13-2 condition code bits CC 1 and CC 0, relationship to conditional jump instructions, 16-6 condition codes (CC 1 and CC 0), 2-142-15 condition codes CC 1 and CC 0 after a Compare instruction, 11-4, 11-5 description of, 2-122-16 evaluation of 32-bit integer math result, 9-4 first check (FC) bit, 2-122-13 indication of valid range for integer math result, 9-4 instructions that affect the status word, 5-10 instructions that evaluate the bits of the status word, 11-6 OR bit, 2-14 overflow (OV) bit, 2-14 overflow bit (OV) after a Compare Real number instruction, 11-5 reading using the Load (L) instruction, 8-6
result of logic operation (RLO) bit, 2-13 status (STA) bit, 2-13 stored overflow (OS) bit, 2-14 stored overflow bit (OS) after a Compare Real number instruction, 11-5 transferring the contents of accumulator 1 to it, 8-6 STL instructions, alphabetical listing arranged by International full name, A-12A-16 arranged by the International mnemonic abbreviations, A-7A-11 arranged by the SIMATIC mnemonic abbreviations, A-2A-11 Stored overflow (OS) as affected by floating-point math instructions, 10-4 as affected by integer math instructions, 9-4 bit of status word, 2-14 Stored overflow (OV), as affected by comparing two real numbers, 11-5 Structure of an instruction statement, 2-22-7 STW. See Status word Swapping, data block registers, 15-2 Symbolic addresses, 17-3 Symbolic addressing, 2-4, 17-3 practical example, B-3 System function blocks (SFBs), as address of an instruction, 2-5 System functions (SFCs), as address of an instruction, 2-5
T
T. See Load and Transfer instructions TAK. See Toggle Accumulator 1 with Accumulator 2 TAN. See Tangent Tangent (TAN), 10-13 TAR. See Loading and transferring between address registers Terminating a logic string, 5-20 Terminating the scanning of a block, 17-16 Time base for S5 TIME, 6-46-5 Time resolution. See Time base for S5 TIME
Index-13
Index
Time value format in accumulator 1, 6-4 range, 6-36-4 syntax, 6-3 Timers area of memory, 2-8 address ranges, 2-9 components, 6-36-4 definition of, 6-2 enabling, 6-6 instructions used with, 6-26-17 instructions used with timers bit logic, 5-225-23 Enable (FR), 6-6 Extended Pulse Timer (SE), 6-5, 6-96-10 Off-Delay Timer (SF), 6-5, 6-156-16 On-Delay Timer (SD), 6-5, 6-116-12 practical applications, B-7B-10 Pulse Timer (SP), 6-56-6, 6-76-8 Reset (R), 6-6 Retentive On-Delay Timer (SS), 6-5, 6-136-14 location in memory, 6-3 number supported, 6-3 resetting, 6-6 resolution. See Time base for S5 TIME starting, 6-5 time base for S5 TIME, 6-46-5 time value, 6-3 range, 6-36-4 syntax, 6-3 types, 6-2 Extended Pulse (SE), 6-2, 6-5, 6-96-10 Off-Delay (SF), 6-2, 6-5, 6-156-16 On-Delay (SD), 6-2, 6-5, 6-116-12 overview, 6-18 Pulse (SP), 6-2, 6-56-6, 6-76-8 Retentive On-Delay (SS), 6-2, 6-5, 6-136-14 Toggle Accumulator 1 with Accumulator 2. See TAK
Toggle the contents of Accumulator 1 with Accumulator 2, 4-2 Transfer (T) instruction. See Load (L) and Transfer (T) instructions Transferring the contents of accumulator 1 to the status word, 8-6 Transitional contacts, 5-165-19 TRUNC. See Truncate conversion instruction Truncate (TRUNC) conversion instruction, 12-12 Twos Complement Double Integer (NEGD) conversion instruction, 12-14 Twos Complement Integer (NEGI) conversion instruction, 12-1412-15
U
UC. See Unconditional Call instruction Unconditional Call (UC) instruction, 17-7 Unconditional jump instructions Jump to List (JL), 16-3 Jump Unconditional (JU), 16-3
W
Word logic instructions, 13-213-8 16-bit, 13-313-8 32-bit, 13-613-8 accumulator administration, 13-2, 13-3, 13-6 And Double Word (AD), 13-713-8 And Word (AW), 13-4, 13-5 Exclusive Or Word (XOW), 13-3 Or Word (OW), 13-3, 13-4 practical applications, B-14
X
X. See Exclusive Or instruction XN. See Exclusive Or Not instruction
Index-14
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Statement List (STL) For S7-300 and S7-400 Programming Simatic S7

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Preface, Contents Product Overview Structure and Components of Instructions and Statements

Statement List (STL) for S7-300 and S7-400 Programming

Note the following:

SIMATICR, SIMATIC HMIR

and SIMATIC NETR are registered trademarks of SIEMENS AG.

Copyright E Siemens AG 1998 All rights reserved

Statement List (STL) for S7-300/S7-400

Scope of the Manual

Compliance with Standards

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Documentation STEP 7 Basic Information with

S From S5 to S7, Converter Manual

S Standard and System Functions for

Online Helps Help on STEP 7

Order Number Part of the STEP 7 Standard software.

Context-sensitive reference informa- Part of the STEP 7 Stantion. dard software.

Accessing the Online Help

You can display the online help in the following ways:

S Help on STEP 7 via the menu command Help > Contents.

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

SIMATIC Customer Support Online Services

S General current information can be obtained:

S in Johnson City (TN), USA

Courses for SIMATIC Products

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Questionnaires on the Manual and Online Help

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

11-1 11-2 11-3 11-5 12-1 12-2 12-8

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

What is Statement List?

The Programming Language STL

The Programming Package

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Structure and Components of Instructions and Statements

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Structure and Components of Instructions and Statements

S A statement made up of an instruction alone (for example, NOT, see

S A statement made up of an instruction and an address (see Tables 2-1

Statement group 1 Instruction alone Figure 2-1

Statement group 2 Instruction + address

Basic Groups of Statements

S A constant, the value of a timer or counter, or an ASCII character string

S A bit in the status word of the programmable logic controller (for

S A function (FC), function block (FB), integrated system function (SFC),

S An address identifier and a location within the memory area that is

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Structure and Components of Instructions and Statements

Locations in the Status Word

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Structure and Components of Instructions and Statements

A Data Block and a Location within the Data Block

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Structure and Components of Instructions and Statements

FCs, FBs, SFCs, and SFBs

S An address identifier that indicates a memory area but no size of a data

S An address identifier that indicates the size of a data object but no

Statement List (STL) for S7-300/S7-400 C79000-G7076-C565-01

Structure and Components of Instructions and Statements

Number or Location of Number